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4.26M
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5.16M
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }
module EgressUnit_12( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File FIFOFixer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.util.property class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule { private def fifoMap(seq: Seq[TLSlaveParameters]) = { val (flatManagers, keepManagers) = seq.partition(policy) // We need to be careful if one flatManager and one keepManager share an existing domain // Erring on the side of caution, we will also flatten the keepManager in this case val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0 val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted // Calculate what the FIFO domains look like after the fixer is applied val flatMap = flatDomains.map { x => (x, 0) }.toMap val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap val map = flatMap ++ keepMap val fixMap = seq.map { m => m.fifoId match { case None => if (policy(m)) Some(0) else None case Some(id) => Some(map(id)) // also flattens some who did not ask } } // Compress the FIFO domain space of those we are combining val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap val splatMap = seq.map { m => m.fifoId match { case None => None case Some(id) => reMap.lift(id) } } (fixMap, splatMap) } val node = new AdapterNode(TLImp)( { cp => cp }, { mp => val (fixMap, _) = fifoMap(mp.managers) mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) }) }) with TLFormatNode { override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers) // Do we need to serialize the request to this manager? val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B) // Compact the IDs of the cases we serialize val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap { case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None } val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0 val a_id = if (compacted.isEmpty) 0.U else edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address) val a_noDomain = a_id === 0.U if (false) { println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}") println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}") println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}") println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}") println("") } // Count beats val a_first = edgeIn.first(in.a) val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck // Keep one bit for each source recording if there is an outstanding request that must be made FIFO // Sources unused in the stall signal calculation should be pruned by DCE val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B })) when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO } when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B } val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c => val a_sel = c.sourceId.contains(in.a.bits.source) val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO) val track = flight.slice(c.sourceId.start, c.sourceId.end) a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id) } val stall = stalls.foldLeft(false.B)(_||_) out.a <> in.a in.d <> out.d out.a.valid := in.a.valid && (a_notFIFO || !stall) in.a.ready := out.a.ready && (a_notFIFO || !stall) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> out.b out.c <> in .c out.e <> in .e } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } //Functional cover properties property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction") val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W)) val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W)) val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W)) when (a_first && in.a.fire && !a_notFIFO) { SourceIdSet := UIntToOH(in.a.bits.source) } when (d_first && in.d.fire) { SourceIdClear := UIntToOH(in.d.bits.source) } SourceIdFIFOed := SourceIdFIFOed | SourceIdSet val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U) property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs") //property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs") property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty") property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed") property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped") } } } object TLFIFOFixer { // Which slaves should have their FIFOness combined? // NOTE: this transformation is still only applied for masters with requestFifo type Policy = TLSlaveParameters => Boolean import RegionType._ val all: Policy = m => true val allFIFO: Policy = m => m.fifoId.isDefined val allVolatile: Policy = m => m.regionType <= VOLATILE def apply(policy: Policy = all)(implicit p: Parameters): TLNode = { val fixer = LazyModule(new TLFIFOFixer(policy)) fixer.node } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `β†’`: target of arrow is generated by source * * {{{ * (from the other node) * β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€[[InwardNode.uiParams]]─────────────┐ * ↓ β”‚ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ β”‚ * [[InwardNode.accPI]] β”‚ β”‚ β”‚ * β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ ↓ β”‚ * ↓ β”‚ β”‚ β”‚ * (immobilize after elaboration) (inward port from [[OutwardNode]]) β”‚ ↓ β”‚ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] β”‚ * β”‚ β”‚ ↑ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[OutwardNode.doParams]] β”‚ β”‚ * β”‚ β”‚ β”‚ (from the other node) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ └────────┬─────────────── β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ (from the other node) β”‚ ↓ β”‚ * β”‚ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] β”‚ [[MixedNode.edgesIn]]───┐ β”‚ * β”‚ ↑ ↑ β”‚ β”‚ ↓ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ [[MixedNode.in]] β”‚ * β”‚ β”‚ β”‚ β”‚ ↓ ↑ β”‚ * β”‚ (solve star connection) β”‚ β”‚ β”‚ [[MixedNode.bundleIn]]β”€β”€β”˜ β”‚ * β”œβ”€β”€β”€[[MixedNode.resolveStar]]→─┼────────────────────────────── └────────────────────────────────────┐ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.bundleOut]]─┐ β”‚ β”‚ * β”‚ β”‚ β”‚ ↑ ↓ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.out]] β”‚ β”‚ * β”‚ ↓ ↓ β”‚ ↑ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]β”€β”€β”˜ β”‚ β”‚ * β”‚ β”‚ (from the other node) ↑ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.outer.edgeO]] β”‚ β”‚ * β”‚ β”‚ β”‚ (based on protocol) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * (immobilize after elaboration)β”‚ ↓ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.oBindings]]β”€β”˜ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] β”‚ β”‚ * ↑ (inward port from [[OutwardNode]]) β”‚ β”‚ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.accPO]] β”‚ ↓ β”‚ β”‚ β”‚ * (binding node when elaboration) β”‚ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ * β”‚ ↑ β”‚ β”‚ * β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ * β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLFIFOFixer_4( // @[FIFOFixer.scala:50:9] input clock, // @[FIFOFixer.scala:50:9] input reset, // @[FIFOFixer.scala:50:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [21:0] _a_notFIFO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _a_notFIFO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59] wire _stalls_a_sel_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _stalls_a_sel_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _stalls_id_T_6 = 1'h1; // @[FIFOFixer.scala:85:59] wire [128:0] _allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [20:0] auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9] wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [7:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29] wire [7:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source; // @[Parameters.scala:52:29] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [20:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [20:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [21:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_2 = _a_id_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _a_id_T_3 = _a_id_T_2; // @[Parameters.scala:137:46] wire _a_id_T_4 = _a_id_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire _a_id_T_10 = _a_id_T_4; // @[Mux.scala:30:73] wire [20:0] _a_id_T_5 = {anonIn_a_bits_address[20:17], anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [21:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_7 = _a_id_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _a_id_T_8 = _a_id_T_7; // @[Parameters.scala:137:46] wire _a_id_T_9 = _a_id_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] _a_id_T_11 = {_a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _a_id_T_12 = {1'h0, _a_id_T_10} | _a_id_T_11; // @[Mux.scala:30:73] wire [1:0] a_id = _a_id_T_12; // @[Mux.scala:30:73] wire a_noDomain = a_id == 2'h0; // @[Mux.scala:30:73] wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_5; // @[Decoupled.scala:51:35] wire _stalls_id_T; // @[Decoupled.scala:51:35] assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35] wire _stalls_id_T_4; // @[Decoupled.scala:51:35] assign _stalls_id_T_4 = _T_5; // @[Decoupled.scala:51:35] wire [12:0] _a_first_beats1_decode_T = 13'h3F << anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] _d_first_beats1_decode_T = 13'h3F << anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg flight_0; // @[FIFOFixer.scala:79:27] reg flight_1; // @[FIFOFixer.scala:79:27] reg flight_2; // @[FIFOFixer.scala:79:27] reg flight_3; // @[FIFOFixer.scala:79:27] reg flight_4; // @[FIFOFixer.scala:79:27] reg flight_5; // @[FIFOFixer.scala:79:27] reg flight_6; // @[FIFOFixer.scala:79:27] reg flight_7; // @[FIFOFixer.scala:79:27] reg flight_8; // @[FIFOFixer.scala:79:27] reg flight_9; // @[FIFOFixer.scala:79:27] reg flight_10; // @[FIFOFixer.scala:79:27] reg flight_11; // @[FIFOFixer.scala:79:27] reg flight_12; // @[FIFOFixer.scala:79:27] reg flight_13; // @[FIFOFixer.scala:79:27] reg flight_14; // @[FIFOFixer.scala:79:27] reg flight_15; // @[FIFOFixer.scala:79:27] reg flight_16; // @[FIFOFixer.scala:79:27] reg flight_17; // @[FIFOFixer.scala:79:27] reg flight_18; // @[FIFOFixer.scala:79:27] reg flight_19; // @[FIFOFixer.scala:79:27] reg flight_20; // @[FIFOFixer.scala:79:27] reg flight_21; // @[FIFOFixer.scala:79:27] reg flight_22; // @[FIFOFixer.scala:79:27] reg flight_23; // @[FIFOFixer.scala:79:27] reg flight_24; // @[FIFOFixer.scala:79:27] reg flight_25; // @[FIFOFixer.scala:79:27] reg flight_26; // @[FIFOFixer.scala:79:27] reg flight_27; // @[FIFOFixer.scala:79:27] reg flight_28; // @[FIFOFixer.scala:79:27] reg flight_29; // @[FIFOFixer.scala:79:27] reg flight_30; // @[FIFOFixer.scala:79:27] reg flight_31; // @[FIFOFixer.scala:79:27] reg flight_32; // @[FIFOFixer.scala:79:27] reg flight_33; // @[FIFOFixer.scala:79:27] reg flight_34; // @[FIFOFixer.scala:79:27] reg flight_35; // @[FIFOFixer.scala:79:27] reg flight_36; // @[FIFOFixer.scala:79:27] reg flight_37; // @[FIFOFixer.scala:79:27] reg flight_38; // @[FIFOFixer.scala:79:27] reg flight_39; // @[FIFOFixer.scala:79:27] reg flight_40; // @[FIFOFixer.scala:79:27] reg flight_41; // @[FIFOFixer.scala:79:27] reg flight_42; // @[FIFOFixer.scala:79:27] reg flight_43; // @[FIFOFixer.scala:79:27] reg flight_44; // @[FIFOFixer.scala:79:27] reg flight_45; // @[FIFOFixer.scala:79:27] reg flight_46; // @[FIFOFixer.scala:79:27] reg flight_47; // @[FIFOFixer.scala:79:27] reg flight_48; // @[FIFOFixer.scala:79:27] reg flight_49; // @[FIFOFixer.scala:79:27] reg flight_50; // @[FIFOFixer.scala:79:27] reg flight_51; // @[FIFOFixer.scala:79:27] reg flight_52; // @[FIFOFixer.scala:79:27] reg flight_53; // @[FIFOFixer.scala:79:27] reg flight_54; // @[FIFOFixer.scala:79:27] reg flight_55; // @[FIFOFixer.scala:79:27] reg flight_56; // @[FIFOFixer.scala:79:27] reg flight_57; // @[FIFOFixer.scala:79:27] reg flight_58; // @[FIFOFixer.scala:79:27] reg flight_59; // @[FIFOFixer.scala:79:27] reg flight_60; // @[FIFOFixer.scala:79:27] reg flight_61; // @[FIFOFixer.scala:79:27] reg flight_62; // @[FIFOFixer.scala:79:27] reg flight_63; // @[FIFOFixer.scala:79:27] reg flight_64; // @[FIFOFixer.scala:79:27] reg flight_65; // @[FIFOFixer.scala:79:27] reg flight_66; // @[FIFOFixer.scala:79:27] reg flight_67; // @[FIFOFixer.scala:79:27] reg flight_68; // @[FIFOFixer.scala:79:27] reg flight_69; // @[FIFOFixer.scala:79:27] reg flight_70; // @[FIFOFixer.scala:79:27] reg flight_71; // @[FIFOFixer.scala:79:27] reg flight_72; // @[FIFOFixer.scala:79:27] reg flight_73; // @[FIFOFixer.scala:79:27] reg flight_74; // @[FIFOFixer.scala:79:27] reg flight_75; // @[FIFOFixer.scala:79:27] reg flight_76; // @[FIFOFixer.scala:79:27] reg flight_77; // @[FIFOFixer.scala:79:27] reg flight_78; // @[FIFOFixer.scala:79:27] reg flight_79; // @[FIFOFixer.scala:79:27] reg flight_80; // @[FIFOFixer.scala:79:27] reg flight_81; // @[FIFOFixer.scala:79:27] reg flight_82; // @[FIFOFixer.scala:79:27] reg flight_83; // @[FIFOFixer.scala:79:27] reg flight_84; // @[FIFOFixer.scala:79:27] reg flight_85; // @[FIFOFixer.scala:79:27] reg flight_86; // @[FIFOFixer.scala:79:27] reg flight_87; // @[FIFOFixer.scala:79:27] reg flight_88; // @[FIFOFixer.scala:79:27] reg flight_89; // @[FIFOFixer.scala:79:27] reg flight_90; // @[FIFOFixer.scala:79:27] reg flight_91; // @[FIFOFixer.scala:79:27] reg flight_92; // @[FIFOFixer.scala:79:27] reg flight_93; // @[FIFOFixer.scala:79:27] reg flight_94; // @[FIFOFixer.scala:79:27] reg flight_95; // @[FIFOFixer.scala:79:27] reg flight_96; // @[FIFOFixer.scala:79:27] reg flight_97; // @[FIFOFixer.scala:79:27] reg flight_98; // @[FIFOFixer.scala:79:27] reg flight_99; // @[FIFOFixer.scala:79:27] reg flight_100; // @[FIFOFixer.scala:79:27] reg flight_101; // @[FIFOFixer.scala:79:27] reg flight_102; // @[FIFOFixer.scala:79:27] reg flight_103; // @[FIFOFixer.scala:79:27] reg flight_104; // @[FIFOFixer.scala:79:27] reg flight_105; // @[FIFOFixer.scala:79:27] reg flight_106; // @[FIFOFixer.scala:79:27] reg flight_107; // @[FIFOFixer.scala:79:27] reg flight_108; // @[FIFOFixer.scala:79:27] reg flight_109; // @[FIFOFixer.scala:79:27] reg flight_110; // @[FIFOFixer.scala:79:27] reg flight_111; // @[FIFOFixer.scala:79:27] reg flight_112; // @[FIFOFixer.scala:79:27] reg flight_113; // @[FIFOFixer.scala:79:27] reg flight_114; // @[FIFOFixer.scala:79:27] reg flight_115; // @[FIFOFixer.scala:79:27] reg flight_116; // @[FIFOFixer.scala:79:27] reg flight_117; // @[FIFOFixer.scala:79:27] reg flight_118; // @[FIFOFixer.scala:79:27] reg flight_119; // @[FIFOFixer.scala:79:27] reg flight_120; // @[FIFOFixer.scala:79:27] reg flight_121; // @[FIFOFixer.scala:79:27] reg flight_122; // @[FIFOFixer.scala:79:27] reg flight_123; // @[FIFOFixer.scala:79:27] reg flight_124; // @[FIFOFixer.scala:79:27] reg flight_125; // @[FIFOFixer.scala:79:27] reg flight_126; // @[FIFOFixer.scala:79:27] reg flight_127; // @[FIFOFixer.scala:79:27] reg flight_128; // @[FIFOFixer.scala:79:27] wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _stalls_a_sel_T = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10] wire [4:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10] wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 5'h2; // @[Parameters.scala:54:{10,32}] wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}] wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48] wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35] wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}] reg [1:0] stalls_id; // @[FIFOFixer.scala:85:30] wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15] wire _stalls_T_1 = flight_16 | flight_17; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_2 = _stalls_T_1 | flight_18; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_3 = _stalls_T_2 | flight_19; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_4 = _stalls_T_3 | flight_20; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_5 = _stalls_T_4 | flight_21; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_6 = _stalls_T_5 | flight_22; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_7 = _stalls_T_6 | flight_23; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}] wire _stalls_T_9 = stalls_id != a_id; // @[Mux.scala:30:73] wire _stalls_T_10 = a_noDomain | _stalls_T_9; // @[FIFOFixer.scala:63:29, :88:{65,71}] wire stalls_0 = _stalls_T_8 & _stalls_T_10; // @[FIFOFixer.scala:88:{26,50,65}] wire _stall_T = stalls_0; // @[FIFOFixer.scala:88:50, :91:45] wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6; // @[Parameters.scala:54:{32,67}] wire stalls_a_sel_1 = _stalls_a_sel_T_8; // @[Parameters.scala:54:67, :56:48] wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1; // @[Decoupled.scala:51:35] wire _stalls_id_T_7 = _stalls_id_T_5; // @[FIFOFixer.scala:85:{47,56}] reg [1:0] stalls_id_1; // @[FIFOFixer.scala:85:30] wire _stalls_T_11 = stalls_a_sel_1 & a_first; // @[FIFOFixer.scala:88:15] wire _stalls_T_12 = flight_24 | flight_25; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_13 = _stalls_T_12 | flight_26; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_14 = _stalls_T_13 | flight_27; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_15 = _stalls_T_14 | flight_28; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_16 = _stalls_T_15 | flight_29; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_17 = _stalls_T_16 | flight_30; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_18 = _stalls_T_17 | flight_31; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18; // @[FIFOFixer.scala:88:{15,26,44}] wire _stalls_T_20 = stalls_id_1 != a_id; // @[Mux.scala:30:73] wire _stalls_T_21 = a_noDomain | _stalls_T_20; // @[FIFOFixer.scala:63:29, :88:{65,71}] wire stalls_1 = _stalls_T_19 & _stalls_T_21; // @[FIFOFixer.scala:88:{26,50,65}] wire stall = _stall_T | stalls_1; // @[FIFOFixer.scala:88:50, :91:45] wire _anonOut_a_valid_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50] wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T; // @[FIFOFixer.scala:95:{47,50}] assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1; // @[FIFOFixer.scala:95:{33,47}] assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire _anonIn_a_ready_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50, :96:50] wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T; // @[FIFOFixer.scala:96:{47,50}] assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1; // @[FIFOFixer.scala:96:{33,47}] assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [128:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [128:0] SourceIdSet; // @[FIFOFixer.scala:116:36] wire [128:0] SourceIdClear; // @[FIFOFixer.scala:117:38] wire [255:0] _SourceIdSet_T = 256'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35] assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [255:0] _SourceIdClear_T = 256'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35] assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [128:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35] wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[FIFOFixer.scala:50:9] if (reset) begin // @[FIFOFixer.scala:50:9] a_first_counter <= 3'h0; // @[Edges.scala:229:27] d_first_counter <= 3'h0; // @[Edges.scala:229:27] flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27] SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35] end else begin // @[FIFOFixer.scala:50:9] if (_a_first_T) // @[Decoupled.scala:51:35] a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (_d_first_T) // @[Decoupled.scala:51:35] d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21] flight_0 <= ~(_T_3 & anonIn_d_bits_source == 8'h0) & (_T_1 & anonIn_a_bits_source == 8'h0 | flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_1 <= ~(_T_3 & anonIn_d_bits_source == 8'h1) & (_T_1 & anonIn_a_bits_source == 8'h1 | flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_2 <= ~(_T_3 & anonIn_d_bits_source == 8'h2) & (_T_1 & anonIn_a_bits_source == 8'h2 | flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_3 <= ~(_T_3 & anonIn_d_bits_source == 8'h3) & (_T_1 & anonIn_a_bits_source == 8'h3 | flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_4 <= ~(_T_3 & anonIn_d_bits_source == 8'h4) & (_T_1 & anonIn_a_bits_source == 8'h4 | flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_5 <= ~(_T_3 & anonIn_d_bits_source == 8'h5) & (_T_1 & anonIn_a_bits_source == 8'h5 | flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_6 <= ~(_T_3 & anonIn_d_bits_source == 8'h6) & (_T_1 & anonIn_a_bits_source == 8'h6 | flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_7 <= ~(_T_3 & anonIn_d_bits_source == 8'h7) & (_T_1 & anonIn_a_bits_source == 8'h7 | flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_8 <= ~(_T_3 & anonIn_d_bits_source == 8'h8) & (_T_1 & anonIn_a_bits_source == 8'h8 | flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_9 <= ~(_T_3 & anonIn_d_bits_source == 8'h9) & (_T_1 & anonIn_a_bits_source == 8'h9 | flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_10 <= ~(_T_3 & anonIn_d_bits_source == 8'hA) & (_T_1 & anonIn_a_bits_source == 8'hA | flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_11 <= ~(_T_3 & anonIn_d_bits_source == 8'hB) & (_T_1 & anonIn_a_bits_source == 8'hB | flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_12 <= ~(_T_3 & anonIn_d_bits_source == 8'hC) & (_T_1 & anonIn_a_bits_source == 8'hC | flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_13 <= ~(_T_3 & anonIn_d_bits_source == 8'hD) & (_T_1 & anonIn_a_bits_source == 8'hD | flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_14 <= ~(_T_3 & anonIn_d_bits_source == 8'hE) & (_T_1 & anonIn_a_bits_source == 8'hE | flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_15 <= ~(_T_3 & anonIn_d_bits_source == 8'hF) & (_T_1 & anonIn_a_bits_source == 8'hF | flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_16 <= ~(_T_3 & anonIn_d_bits_source == 8'h10) & (_T_1 & anonIn_a_bits_source == 8'h10 | flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_17 <= ~(_T_3 & anonIn_d_bits_source == 8'h11) & (_T_1 & anonIn_a_bits_source == 8'h11 | flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_18 <= ~(_T_3 & anonIn_d_bits_source == 8'h12) & (_T_1 & anonIn_a_bits_source == 8'h12 | flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_19 <= ~(_T_3 & anonIn_d_bits_source == 8'h13) & (_T_1 & anonIn_a_bits_source == 8'h13 | flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_20 <= ~(_T_3 & anonIn_d_bits_source == 8'h14) & (_T_1 & anonIn_a_bits_source == 8'h14 | flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_21 <= ~(_T_3 & anonIn_d_bits_source == 8'h15) & (_T_1 & anonIn_a_bits_source == 8'h15 | flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_22 <= ~(_T_3 & anonIn_d_bits_source == 8'h16) & (_T_1 & anonIn_a_bits_source == 8'h16 | flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_23 <= ~(_T_3 & anonIn_d_bits_source == 8'h17) & (_T_1 & anonIn_a_bits_source == 8'h17 | flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_24 <= ~(_T_3 & anonIn_d_bits_source == 8'h18) & (_T_1 & anonIn_a_bits_source == 8'h18 | flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_25 <= ~(_T_3 & anonIn_d_bits_source == 8'h19) & (_T_1 & anonIn_a_bits_source == 8'h19 | flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_26 <= ~(_T_3 & anonIn_d_bits_source == 8'h1A) & (_T_1 & anonIn_a_bits_source == 8'h1A | flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_27 <= ~(_T_3 & anonIn_d_bits_source == 8'h1B) & (_T_1 & anonIn_a_bits_source == 8'h1B | flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_28 <= ~(_T_3 & anonIn_d_bits_source == 8'h1C) & (_T_1 & anonIn_a_bits_source == 8'h1C | flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_29 <= ~(_T_3 & anonIn_d_bits_source == 8'h1D) & (_T_1 & anonIn_a_bits_source == 8'h1D | flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_30 <= ~(_T_3 & anonIn_d_bits_source == 8'h1E) & (_T_1 & anonIn_a_bits_source == 8'h1E | flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_31 <= ~(_T_3 & anonIn_d_bits_source == 8'h1F) & (_T_1 & anonIn_a_bits_source == 8'h1F | flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_32 <= ~(_T_3 & anonIn_d_bits_source == 8'h20) & (_T_1 & anonIn_a_bits_source == 8'h20 | flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_33 <= ~(_T_3 & anonIn_d_bits_source == 8'h21) & (_T_1 & anonIn_a_bits_source == 8'h21 | flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_34 <= ~(_T_3 & anonIn_d_bits_source == 8'h22) & (_T_1 & anonIn_a_bits_source == 8'h22 | flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_35 <= ~(_T_3 & anonIn_d_bits_source == 8'h23) & (_T_1 & anonIn_a_bits_source == 8'h23 | flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_36 <= ~(_T_3 & anonIn_d_bits_source == 8'h24) & (_T_1 & anonIn_a_bits_source == 8'h24 | flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_37 <= ~(_T_3 & anonIn_d_bits_source == 8'h25) & (_T_1 & anonIn_a_bits_source == 8'h25 | flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_38 <= ~(_T_3 & anonIn_d_bits_source == 8'h26) & (_T_1 & anonIn_a_bits_source == 8'h26 | flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_39 <= ~(_T_3 & anonIn_d_bits_source == 8'h27) & (_T_1 & anonIn_a_bits_source == 8'h27 | flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_40 <= ~(_T_3 & anonIn_d_bits_source == 8'h28) & (_T_1 & anonIn_a_bits_source == 8'h28 | flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_41 <= ~(_T_3 & anonIn_d_bits_source == 8'h29) & (_T_1 & anonIn_a_bits_source == 8'h29 | flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_42 <= ~(_T_3 & anonIn_d_bits_source == 8'h2A) & (_T_1 & anonIn_a_bits_source == 8'h2A | flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_43 <= ~(_T_3 & anonIn_d_bits_source == 8'h2B) & (_T_1 & anonIn_a_bits_source == 8'h2B | flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_44 <= ~(_T_3 & anonIn_d_bits_source == 8'h2C) & (_T_1 & anonIn_a_bits_source == 8'h2C | flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_45 <= ~(_T_3 & anonIn_d_bits_source == 8'h2D) & (_T_1 & anonIn_a_bits_source == 8'h2D | flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_46 <= ~(_T_3 & anonIn_d_bits_source == 8'h2E) & (_T_1 & anonIn_a_bits_source == 8'h2E | flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_47 <= ~(_T_3 & anonIn_d_bits_source == 8'h2F) & (_T_1 & anonIn_a_bits_source == 8'h2F | flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_48 <= ~(_T_3 & anonIn_d_bits_source == 8'h30) & (_T_1 & anonIn_a_bits_source == 8'h30 | flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_49 <= ~(_T_3 & anonIn_d_bits_source == 8'h31) & (_T_1 & anonIn_a_bits_source == 8'h31 | flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_50 <= ~(_T_3 & anonIn_d_bits_source == 8'h32) & (_T_1 & anonIn_a_bits_source == 8'h32 | flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_51 <= ~(_T_3 & anonIn_d_bits_source == 8'h33) & (_T_1 & anonIn_a_bits_source == 8'h33 | flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_52 <= ~(_T_3 & anonIn_d_bits_source == 8'h34) & (_T_1 & anonIn_a_bits_source == 8'h34 | flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_53 <= ~(_T_3 & anonIn_d_bits_source == 8'h35) & (_T_1 & anonIn_a_bits_source == 8'h35 | flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_54 <= ~(_T_3 & anonIn_d_bits_source == 8'h36) & (_T_1 & anonIn_a_bits_source == 8'h36 | flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_55 <= ~(_T_3 & anonIn_d_bits_source == 8'h37) & (_T_1 & anonIn_a_bits_source == 8'h37 | flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_56 <= ~(_T_3 & anonIn_d_bits_source == 8'h38) & (_T_1 & anonIn_a_bits_source == 8'h38 | flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_57 <= ~(_T_3 & anonIn_d_bits_source == 8'h39) & (_T_1 & anonIn_a_bits_source == 8'h39 | flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_58 <= ~(_T_3 & anonIn_d_bits_source == 8'h3A) & (_T_1 & anonIn_a_bits_source == 8'h3A | flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_59 <= ~(_T_3 & anonIn_d_bits_source == 8'h3B) & (_T_1 & anonIn_a_bits_source == 8'h3B | flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_60 <= ~(_T_3 & anonIn_d_bits_source == 8'h3C) & (_T_1 & anonIn_a_bits_source == 8'h3C | flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_61 <= ~(_T_3 & anonIn_d_bits_source == 8'h3D) & (_T_1 & anonIn_a_bits_source == 8'h3D | flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_62 <= ~(_T_3 & anonIn_d_bits_source == 8'h3E) & (_T_1 & anonIn_a_bits_source == 8'h3E | flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_63 <= ~(_T_3 & anonIn_d_bits_source == 8'h3F) & (_T_1 & anonIn_a_bits_source == 8'h3F | flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_64 <= ~(_T_3 & anonIn_d_bits_source == 8'h40) & (_T_1 & anonIn_a_bits_source == 8'h40 | flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_65 <= ~(_T_3 & anonIn_d_bits_source == 8'h41) & (_T_1 & anonIn_a_bits_source == 8'h41 | flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_66 <= ~(_T_3 & anonIn_d_bits_source == 8'h42) & (_T_1 & anonIn_a_bits_source == 8'h42 | flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_67 <= ~(_T_3 & anonIn_d_bits_source == 8'h43) & (_T_1 & anonIn_a_bits_source == 8'h43 | flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_68 <= ~(_T_3 & anonIn_d_bits_source == 8'h44) & (_T_1 & anonIn_a_bits_source == 8'h44 | flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_69 <= ~(_T_3 & anonIn_d_bits_source == 8'h45) & (_T_1 & anonIn_a_bits_source == 8'h45 | flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_70 <= ~(_T_3 & anonIn_d_bits_source == 8'h46) & (_T_1 & anonIn_a_bits_source == 8'h46 | flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_71 <= ~(_T_3 & anonIn_d_bits_source == 8'h47) & (_T_1 & anonIn_a_bits_source == 8'h47 | flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_72 <= ~(_T_3 & anonIn_d_bits_source == 8'h48) & (_T_1 & anonIn_a_bits_source == 8'h48 | flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_73 <= ~(_T_3 & anonIn_d_bits_source == 8'h49) & (_T_1 & anonIn_a_bits_source == 8'h49 | flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_74 <= ~(_T_3 & anonIn_d_bits_source == 8'h4A) & (_T_1 & anonIn_a_bits_source == 8'h4A | flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_75 <= ~(_T_3 & anonIn_d_bits_source == 8'h4B) & (_T_1 & anonIn_a_bits_source == 8'h4B | flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_76 <= ~(_T_3 & anonIn_d_bits_source == 8'h4C) & (_T_1 & anonIn_a_bits_source == 8'h4C | flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_77 <= ~(_T_3 & anonIn_d_bits_source == 8'h4D) & (_T_1 & anonIn_a_bits_source == 8'h4D | flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_78 <= ~(_T_3 & anonIn_d_bits_source == 8'h4E) & (_T_1 & anonIn_a_bits_source == 8'h4E | flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_79 <= ~(_T_3 & anonIn_d_bits_source == 8'h4F) & (_T_1 & anonIn_a_bits_source == 8'h4F | flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_80 <= ~(_T_3 & anonIn_d_bits_source == 8'h50) & (_T_1 & anonIn_a_bits_source == 8'h50 | flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_81 <= ~(_T_3 & anonIn_d_bits_source == 8'h51) & (_T_1 & anonIn_a_bits_source == 8'h51 | flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_82 <= ~(_T_3 & anonIn_d_bits_source == 8'h52) & (_T_1 & anonIn_a_bits_source == 8'h52 | flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_83 <= ~(_T_3 & anonIn_d_bits_source == 8'h53) & (_T_1 & anonIn_a_bits_source == 8'h53 | flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_84 <= ~(_T_3 & anonIn_d_bits_source == 8'h54) & (_T_1 & anonIn_a_bits_source == 8'h54 | flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_85 <= ~(_T_3 & anonIn_d_bits_source == 8'h55) & (_T_1 & anonIn_a_bits_source == 8'h55 | flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_86 <= ~(_T_3 & anonIn_d_bits_source == 8'h56) & (_T_1 & anonIn_a_bits_source == 8'h56 | flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_87 <= ~(_T_3 & anonIn_d_bits_source == 8'h57) & (_T_1 & anonIn_a_bits_source == 8'h57 | flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_88 <= ~(_T_3 & anonIn_d_bits_source == 8'h58) & (_T_1 & anonIn_a_bits_source == 8'h58 | flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_89 <= ~(_T_3 & anonIn_d_bits_source == 8'h59) & (_T_1 & anonIn_a_bits_source == 8'h59 | flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_90 <= ~(_T_3 & anonIn_d_bits_source == 8'h5A) & (_T_1 & anonIn_a_bits_source == 8'h5A | flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_91 <= ~(_T_3 & anonIn_d_bits_source == 8'h5B) & (_T_1 & anonIn_a_bits_source == 8'h5B | flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_92 <= ~(_T_3 & anonIn_d_bits_source == 8'h5C) & (_T_1 & anonIn_a_bits_source == 8'h5C | flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_93 <= ~(_T_3 & anonIn_d_bits_source == 8'h5D) & (_T_1 & anonIn_a_bits_source == 8'h5D | flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_94 <= ~(_T_3 & anonIn_d_bits_source == 8'h5E) & (_T_1 & anonIn_a_bits_source == 8'h5E | flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_95 <= ~(_T_3 & anonIn_d_bits_source == 8'h5F) & (_T_1 & anonIn_a_bits_source == 8'h5F | flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_96 <= ~(_T_3 & anonIn_d_bits_source == 8'h60) & (_T_1 & anonIn_a_bits_source == 8'h60 | flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_97 <= ~(_T_3 & anonIn_d_bits_source == 8'h61) & (_T_1 & anonIn_a_bits_source == 8'h61 | flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_98 <= ~(_T_3 & anonIn_d_bits_source == 8'h62) & (_T_1 & anonIn_a_bits_source == 8'h62 | flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_99 <= ~(_T_3 & anonIn_d_bits_source == 8'h63) & (_T_1 & anonIn_a_bits_source == 8'h63 | flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_100 <= ~(_T_3 & anonIn_d_bits_source == 8'h64) & (_T_1 & anonIn_a_bits_source == 8'h64 | flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_101 <= ~(_T_3 & anonIn_d_bits_source == 8'h65) & (_T_1 & anonIn_a_bits_source == 8'h65 | flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_102 <= ~(_T_3 & anonIn_d_bits_source == 8'h66) & (_T_1 & anonIn_a_bits_source == 8'h66 | flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_103 <= ~(_T_3 & anonIn_d_bits_source == 8'h67) & (_T_1 & anonIn_a_bits_source == 8'h67 | flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_104 <= ~(_T_3 & anonIn_d_bits_source == 8'h68) & (_T_1 & anonIn_a_bits_source == 8'h68 | flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_105 <= ~(_T_3 & anonIn_d_bits_source == 8'h69) & (_T_1 & anonIn_a_bits_source == 8'h69 | flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_106 <= ~(_T_3 & anonIn_d_bits_source == 8'h6A) & (_T_1 & anonIn_a_bits_source == 8'h6A | flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_107 <= ~(_T_3 & anonIn_d_bits_source == 8'h6B) & (_T_1 & anonIn_a_bits_source == 8'h6B | flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_108 <= ~(_T_3 & anonIn_d_bits_source == 8'h6C) & (_T_1 & anonIn_a_bits_source == 8'h6C | flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_109 <= ~(_T_3 & anonIn_d_bits_source == 8'h6D) & (_T_1 & anonIn_a_bits_source == 8'h6D | flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_110 <= ~(_T_3 & anonIn_d_bits_source == 8'h6E) & (_T_1 & anonIn_a_bits_source == 8'h6E | flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_111 <= ~(_T_3 & anonIn_d_bits_source == 8'h6F) & (_T_1 & anonIn_a_bits_source == 8'h6F | flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_112 <= ~(_T_3 & anonIn_d_bits_source == 8'h70) & (_T_1 & anonIn_a_bits_source == 8'h70 | flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_113 <= ~(_T_3 & anonIn_d_bits_source == 8'h71) & (_T_1 & anonIn_a_bits_source == 8'h71 | flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_114 <= ~(_T_3 & anonIn_d_bits_source == 8'h72) & (_T_1 & anonIn_a_bits_source == 8'h72 | flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_115 <= ~(_T_3 & anonIn_d_bits_source == 8'h73) & (_T_1 & anonIn_a_bits_source == 8'h73 | flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_116 <= ~(_T_3 & anonIn_d_bits_source == 8'h74) & (_T_1 & anonIn_a_bits_source == 8'h74 | flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_117 <= ~(_T_3 & anonIn_d_bits_source == 8'h75) & (_T_1 & anonIn_a_bits_source == 8'h75 | flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_118 <= ~(_T_3 & anonIn_d_bits_source == 8'h76) & (_T_1 & anonIn_a_bits_source == 8'h76 | flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_119 <= ~(_T_3 & anonIn_d_bits_source == 8'h77) & (_T_1 & anonIn_a_bits_source == 8'h77 | flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_120 <= ~(_T_3 & anonIn_d_bits_source == 8'h78) & (_T_1 & anonIn_a_bits_source == 8'h78 | flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_121 <= ~(_T_3 & anonIn_d_bits_source == 8'h79) & (_T_1 & anonIn_a_bits_source == 8'h79 | flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_122 <= ~(_T_3 & anonIn_d_bits_source == 8'h7A) & (_T_1 & anonIn_a_bits_source == 8'h7A | flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_123 <= ~(_T_3 & anonIn_d_bits_source == 8'h7B) & (_T_1 & anonIn_a_bits_source == 8'h7B | flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_124 <= ~(_T_3 & anonIn_d_bits_source == 8'h7C) & (_T_1 & anonIn_a_bits_source == 8'h7C | flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_125 <= ~(_T_3 & anonIn_d_bits_source == 8'h7D) & (_T_1 & anonIn_a_bits_source == 8'h7D | flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_126 <= ~(_T_3 & anonIn_d_bits_source == 8'h7E) & (_T_1 & anonIn_a_bits_source == 8'h7E | flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_127 <= ~(_T_3 & anonIn_d_bits_source == 8'h7F) & (_T_1 & anonIn_a_bits_source == 8'h7F | flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_128 <= ~(_T_3 & anonIn_d_bits_source == 8'h80) & (_T_1 & anonIn_a_bits_source == 8'h80 | flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end if (_stalls_id_T_3) // @[FIFOFixer.scala:85:56] stalls_id <= a_id; // @[Mux.scala:30:73] if (_stalls_id_T_7) // @[FIFOFixer.scala:85:56] stalls_id_1 <= a_id; // @[Mux.scala:30:73] always @(posedge) TLMonitor_33 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_80( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }
module TLNoC_1_router_0ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_29 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_40( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_44 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } }
module IntSyncCrossingSource_n0x0_7( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputBuffer_15( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [36:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [1:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] input io_deq_0_ready, // @[InputUnit.scala:51:14] output io_deq_0_valid, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [36:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] input io_deq_1_ready, // @[InputUnit.scala:51:14] output io_deq_1_valid, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [36:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] input io_deq_2_ready, // @[InputUnit.scala:51:14] output io_deq_2_valid, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [36:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] input io_deq_3_ready, // @[InputUnit.scala:51:14] output io_deq_3_valid, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [36:0] io_deq_3_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [38:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [38:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [38:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [38:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] reg [1:0] heads_0; // @[InputUnit.scala:86:24] reg [1:0] heads_1; // @[InputUnit.scala:86:24] reg [1:0] heads_2; // @[InputUnit.scala:86:24] reg [1:0] heads_3; // @[InputUnit.scala:86:24] reg [1:0] tails_0; // @[InputUnit.scala:87:24] reg [1:0] tails_1; // @[InputUnit.scala:87:24] reg [1:0] tails_2; // @[InputUnit.scala:87:24] reg [1:0] tails_3; // @[InputUnit.scala:87:24] wire _tails_T_12 = io_enq_0_bits_virt_channel_id == 2'h0; // @[Mux.scala:32:36] wire _tails_T_20 = io_enq_0_bits_virt_channel_id == 2'h1; // @[Mux.scala:32:36] wire _tails_T_14 = io_enq_0_bits_virt_channel_id == 2'h2; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_12 & _qs_0_io_enq_ready | _tails_T_20 & _qs_1_io_enq_ready | _tails_T_14 & _qs_2_io_enq_ready | (&io_enq_0_bits_virt_channel_id) & _qs_3_io_enq_ready) & (_tails_T_12 & heads_0 == tails_0 | _tails_T_20 & heads_1 == tails_1 | _tails_T_14 & heads_2 == tails_2 | (&io_enq_0_bits_virt_channel_id) & heads_3 == tails_3); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [3:0][1:0] _GEN = {{tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 2'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 2'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 2'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [3:0] to_q_oh_enc = can_to_q_0 ? 4'h1 : can_to_q_1 ? 4'h2 : can_to_q_2 ? 4'h4 : {can_to_q_3, 3'h0}; // @[OneHot.scala:58:35] wire _GEN_4 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3; // @[package.scala:81:59] wire [1:0] head = (to_q_oh_enc[0] ? heads_0 : 2'h0) | (to_q_oh_enc[1] ? heads_1 : 2'h0) | (to_q_oh_enc[2] ? heads_2 : 2'h0) | (to_q_oh_enc[3] ? heads_3 : 2'h0); // @[OneHot.scala:83:30] wire _GEN_5 = _GEN_4 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_6 = _GEN_4 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_7 = _GEN_4 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_8 = _GEN_4 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire [1:0] _GEN_9 = {_tails_T_14, _tails_T_20}; // @[Mux.scala:30:73, :32:36] wire [1:0] _tails_T_25 = _GEN[io_enq_0_bits_virt_channel_id] == (_GEN_9 | {2{&io_enq_0_bits_virt_channel_id}}) ? _GEN_9 | {2{&io_enq_0_bits_virt_channel_id}} : _GEN[io_enq_0_bits_virt_channel_id] + 2'h1; // @[Mux.scala:30:73, :32:36] wire _to_q_T_2 = to_q_oh_enc[3] | to_q_oh_enc[1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] to_q = {|(to_q_oh_enc[3:2]), _to_q_T_2}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [1:0] _heads_T_11 = {2{to_q_oh_enc[3]}}; // @[OneHot.scala:83:30] wire [1:0] _heads_T_17 = head == (to_q_oh_enc[2:1] | _heads_T_11) ? to_q_oh_enc[2:1] | _heads_T_11 : head + 2'h1; // @[Mux.scala:30:73, :50:70] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 2'h0; // @[InputUnit.scala:86:24] heads_1 <= 2'h1; // @[InputUnit.scala:86:24] heads_2 <= 2'h2; // @[InputUnit.scala:86:24] heads_3 <= 2'h3; // @[InputUnit.scala:86:24] tails_0 <= 2'h0; // @[InputUnit.scala:87:24] tails_1 <= 2'h1; // @[InputUnit.scala:87:24] tails_2 <= 2'h2; // @[InputUnit.scala:87:24] tails_3 <= 2'h3; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_4 & {to_q_oh_enc[3:2], _to_q_T_2} == 3'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27] if (_GEN_4 & to_q == 2'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27] if (_GEN_4 & to_q == 2'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27] if (_GEN_4 & (&to_q)) // @[OneHot.scala:32:10] heads_3 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & (&io_enq_0_bits_virt_channel_id)) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_92( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_109 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }
module IssueSlot_27( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Mem.scala: package saturn.mem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ class LSIQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val op = new VectorMemMacroOp def bound_all = op.mop =/= mopUnit val bound_offset = UInt(pgIdxBits.W) val ld_dep_mask = Vec(vParams.vliqEntries, Bool()) val st_dep_mask = Vec(vParams.vsiqEntries, Bool()) def containsBlock(addr: UInt) = { val cl = addr(pgIdxBits-1,lgCacheBlockBytes) val base_cl = op.base_offset >> lgCacheBlockBytes val bound_cl = bound_offset >> lgCacheBlockBytes (((addr >> pgIdxBits) === op.page) && (base_cl <= cl && bound_cl >= cl)) || bound_all } def overlaps(other: LSIQEntry) = { (op.page === other.op.page) && (bound_all || other.bound_all || ( (op.base_offset <= other.bound_offset && bound_offset >= other.op.base_offset) )) } } class IFQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val head = UInt(log2Ceil(dLenB).W) val tail = UInt(log2Ceil(dLenB).W) val masked = Bool() val last = Bool() val lsiq_id = UInt(lsiqIdBits.W) val page_offset = UInt(pgIdxBits.W) } class MemRequest(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(coreMaxAddrBits.W) val data = UInt((bytes*8).W) val mask = UInt(bytes.W) val tag = UInt(tagBits.W) val store = Bool() } class MemResponse(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) { val data = UInt((bytes*8).W) val tag = UInt(tagBits.W) } class ScalarMemOrderCheckIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val addr = Input(UInt(coreMaxAddrBits.W)) val size = Input(UInt(2.W)) val store = Input(Bool()) val conflict = Output(Bool()) } class VectorMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val load_req = Decoupled(new MemRequest(dLenB, dmemTagBits)) val load_resp = Input(Valid(new MemResponse(dLenB, dmemTagBits))) val store_req = Decoupled(new MemRequest(dLenB, dmemTagBits)) val store_ack = Input(Valid(new MemResponse(dLenB, dmemTagBits))) } class VectorSGMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val req = Vec(vParams.vsgPorts, Decoupled(new MemRequest(1, sgmemTagBits))) val resp = Vec(vParams.vsgPorts, Input(Valid(new MemResponse(1, sgmemTagBits)))) } class VectorMemDatapathIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val lresp = Decoupled(new Bundle { val data = UInt(dLen.W) val debug_id = UInt(debugIdSz.W) }) val sdata = Flipped(Decoupled(new StoreDataMicroOp)) val mask_pop = Decoupled(new CompactorReq(dLenB)) val mask_data = Input(Vec(dLenB, Bool())) val index_pop = Decoupled(new CompactorReq(dLenB)) val index_data = Input(Vec(dLenB, UInt(8.W))) } class VectorMemUnit(sgSize: Option[BigInt] = None)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val enq = Flipped(Decoupled(new VectorMemMacroOp)) val dmem = new VectorMemIO val sgmem = sgSize.map(_ => new VectorSGMemIO) val scalar_check = new ScalarMemOrderCheckIO val vu = new VectorMemDatapathIO val busy = Output(Bool()) }) def ptrIncr(u: UInt, sz: Int): Unit = { val n = u +& 1.U u := Mux(n === sz.U, 0.U, n) } val sgas = sgSize.map { size => Module(new ScatterGatherAddrGen(size)) } val las = Module(new AddrGen) val lifq = Module(new LoadOrderBuffer(vParams.vlifqEntries, vParams.vlrobEntries)) val lcu = Module(new Compactor(dLenB, dLenB, UInt(8.W), true)) val lss = Module(new LoadSegmenter) val scu = Module(new Compactor(dLenB, dLenB, new MaskedByte, false)) val sss = Module(new StoreSegmenter) val sas = Module(new AddrGen) val sifq = Module(new DCEQueue(new IFQEntry, vParams.vsifqEntries)) val liq = Reg(Vec(vParams.vliqEntries, new LSIQEntry)) val liq_valids = RegInit(VecInit.fill(vParams.vliqEntries)(false.B)) val liq_las = RegInit(VecInit.fill(vParams.vliqEntries)(false.B)) val liq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) val liq_las_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) val liq_lss_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W)) val liq_enq_fire = Wire(Bool()) val liq_las_fire = Wire(Bool()) val liq_lss_fire = Wire(Bool()) val liq_enq_ready = !liq_valids(liq_enq_ptr) val liq_las_valid = !liq_las(liq_las_ptr) && liq_valids(liq_las_ptr) val liq_lss_valid = liq_valids(liq_lss_ptr) val siq = Reg(Vec(vParams.vsiqEntries, new LSIQEntry)) val siq_valids = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) val siq_sss = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) val siq_sas = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B)) val siq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) val siq_sss_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) val siq_sas_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) val siq_deq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W)) val siq_enq_fire = Wire(Bool()) val siq_sss_fire = Wire(Bool()) val siq_sas_fire = Wire(Bool()) val siq_deq_fire = Wire(Bool()) val siq_enq_ready = !siq_valids(siq_enq_ptr) val siq_sss_valid = !siq_sss(siq_sss_ptr) && siq_valids(siq_sss_ptr) val siq_sas_valid = !siq_sas(siq_sas_ptr) && siq_valids(siq_sas_ptr) val enq_bound_max = (((io.enq.bits.nf +& 1.U) * io.enq.bits.vl) << io.enq.bits.elem_size) + io.enq.bits.base_offset - 1.U val enq_bound = Mux((enq_bound_max >> pgIdxBits) =/= 0.U, ~(0.U(pgIdxBits.W)), enq_bound_max) when (liq_enq_fire) { liq(liq_enq_ptr).op := io.enq.bits liq(liq_enq_ptr).bound_offset := enq_bound liq(liq_enq_ptr).st_dep_mask := siq_valids liq_las(liq_enq_ptr) := false.B ptrIncr(liq_enq_ptr, vParams.vliqEntries) liq_valids(liq_enq_ptr) := true.B } when (liq_las_fire) { ptrIncr(liq_las_ptr, vParams.vliqEntries) liq_las(liq_las_ptr) := true.B } when (liq_lss_fire) { ptrIncr(liq_lss_ptr, vParams.vliqEntries) liq_valids(liq_lss_ptr) := false.B assert(liq_las(liq_lss_ptr) || (liq_lss_ptr === liq_las_ptr && liq_las_fire)) } when (siq_enq_fire) { siq(siq_enq_ptr).op := io.enq.bits siq(siq_enq_ptr).bound_offset := enq_bound siq(siq_enq_ptr).ld_dep_mask := liq_valids siq_sss(siq_enq_ptr) := false.B siq_sas(siq_enq_ptr) := false.B ptrIncr(siq_enq_ptr, vParams.vsiqEntries) siq_valids(siq_enq_ptr) := true.B } when (siq_sss_fire) { ptrIncr(siq_sss_ptr, vParams.vsiqEntries) siq_sss(siq_sss_ptr) := true.B } when (siq_sas_fire) { ptrIncr(siq_sas_ptr, vParams.vsiqEntries) siq_sas(siq_sas_ptr) := true.B assert(siq_sss(siq_sas_ptr) || (siq_sss_fire && siq_sss_ptr === siq_sas_ptr)) } when (siq_deq_fire) { ptrIncr(siq_deq_ptr, vParams.vsiqEntries) siq_valids(siq_deq_ptr) := false.B assert(siq_sas(siq_deq_ptr) || (siq_sas_fire && siq_sas_ptr === siq_deq_ptr)) } io.enq.ready := Mux(io.enq.bits.store, siq_enq_ready, liq_enq_ready) liq_enq_fire := io.enq.valid && liq_enq_ready && !io.enq.bits.store siq_enq_fire := io.enq.valid && siq_enq_ready && io.enq.bits.store when (liq_lss_fire) { siq.foreach(_.ld_dep_mask(liq_lss_ptr) := false.B) } when (siq_deq_fire) { liq.foreach(_.st_dep_mask(siq_deq_ptr) := false.B) } val scalar_store_conflict = (0 until vParams.vsiqEntries).map { i => siq_valids(i) && (siq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B) }.orR val scalar_load_conflict = (0 until vParams.vliqEntries).map { i => liq_valids(i) && (liq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B) }.orR io.scalar_check.conflict := scalar_store_conflict || (scalar_load_conflict && io.scalar_check.store) // Send indices/masks to las/sas val las_older_than_sas = (liq_las_valid && !liq(liq_las_ptr).st_dep_mask(siq_sas_ptr)) || !siq_sas_valid val maskindex_load = liq_las_valid && las_older_than_sas && !liq(liq_las_ptr).op.fast_sg val maskindex_store = siq_sas_valid && !las_older_than_sas && !siq(siq_sas_ptr).op.fast_sg val maskindex_gather = liq_las_valid && las_older_than_sas && liq(liq_las_ptr).op.fast_sg val maskindex_scatter = siq_sas_valid && !las_older_than_sas && siq(siq_sas_ptr).op.fast_sg las.io.maskindex.index := io.vu.index_data.asUInt sas.io.maskindex.index := io.vu.index_data.asUInt las.io.maskindex.mask := io.vu.mask_data(0) sas.io.maskindex.mask := io.vu.mask_data(0) io.vu.mask_pop.valid := false.B io.vu.mask_pop.bits.head := 0.U io.vu.mask_pop.bits.tail := 1.U io.vu.index_pop.valid := false.B io.vu.index_pop.bits.head := 0.U io.vu.index_pop.bits.tail := 1.U when (maskindex_load) { io.vu.mask_pop.valid := las.io.maskindex.needs_mask && las.io.maskindex.ready io.vu.index_pop.valid := las.io.maskindex.needs_index && las.io.maskindex.ready io.vu.index_pop.bits.tail := 1.U << las.io.maskindex.eew } when (maskindex_store) { io.vu.mask_pop.valid := sas.io.maskindex.needs_mask && sas.io.maskindex.ready io.vu.index_pop.valid := sas.io.maskindex.needs_index && sas.io.maskindex.ready io.vu.index_pop.bits.tail := 1.U << sas.io.maskindex.eew } // scatter/gather paths sgas.foreach { sgas => sgas.io.index_pop.ready := false.B sgas.io.mask_pop.ready := false.B when (maskindex_gather || maskindex_scatter) { io.vu.mask_pop <> sgas.io.mask_pop io.vu.index_pop <> sgas.io.index_pop } sgas.io.index_data := io.vu.index_data sgas.io.mask_data := io.vu.mask_data sgas.io.valid := maskindex_gather || maskindex_scatter sgas.io.lsiq_id := Mux(maskindex_gather, liq_las_ptr, siq_sas_ptr) sgas.io.op := Mux(maskindex_gather, liq(liq_las_ptr).op, siq(siq_sas_ptr).op) sgas.io.req <> io.sgmem.get.req sgas.io.resp <> io.sgmem.get.resp } las.io.maskindex.valid := maskindex_load && (io.vu.mask_pop.ready || !las.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !las.io.maskindex.needs_index) sas.io.maskindex.valid := !maskindex_load && (io.vu.mask_pop.ready || !sas.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !sas.io.maskindex.needs_index) // Load Addr Sequencing val las_order_block = (0 until vParams.vsiqEntries).map { i => val addr_conflict = siq(i).overlaps(liq(liq_las_ptr)) siq_valids(i) && addr_conflict && liq(liq_las_ptr).st_dep_mask(i) }.orR val dae_block = !vParams.enableDAE.B && (!io.vu.lresp.ready || io.vu.lresp.bits.debug_id =/= liq(liq_las_ptr).op.debug_id) las.io.valid := liq_las_valid && !las_order_block && !liq(liq_las_ptr).op.fast_sg && !dae_block las.io.lsiq_id := liq_las_ptr las.io.op := liq(liq_las_ptr).op liq_las_fire := Mux(liq(liq_las_ptr).op.fast_sg, sgas.map(_.io.done && maskindex_gather).getOrElse(false.B), las.io.done) las.io.tag <> lifq.io.reserve las.io.out.ready := lifq.io.reserve.valid lifq.io.entry := las.io.out.bits lifq.io.push.valid := io.dmem.load_resp.valid lifq.io.push.bits.data := io.dmem.load_resp.bits.data lifq.io.push.bits.tag := io.dmem.load_resp.bits.tag val load_arb = Module(new Arbiter(new MemRequest(dLenB, dmemTagBits), 2)) load_arb.io.in(1) <> las.io.req load_arb.io.in(1).bits.store := false.B load_arb.io.in(0) <> lifq.io.replay load_arb.io.in(0).bits.addr := Cat(liq(lifq.io.replay_liq_id).op.page, lifq.io.replay.bits.addr(pgIdxBits-1,0)) when (io.dmem.store_req.valid) { load_arb.io.in(0).valid := false.B lifq.io.replay.ready := false.B } // Load compacting lcu.io.push.valid := lifq.io.deq.valid lcu.io.push.bits.head := lifq.io.deq.bits.head lcu.io.push.bits.tail := lifq.io.deq.bits.tail lcu.io.push_data := lifq.io.deq_data.asTypeOf(Vec(dLenB, UInt(8.W))) lifq.io.deq.ready := lcu.io.push.ready sgas.foreach { sgas => sgas.io.load_resp.ready := false.B when (maskindex_gather && !lifq.io.busy) { sgas.io.load_resp.ready := lcu.io.push.ready lcu.io.push.valid := sgas.io.load_resp.valid lcu.io.push.bits := sgas.io.load_resp.bits lcu.io.push_data := sgas.io.load_data } } // Load segment sequencing lss.io.valid := liq_lss_valid lss.io.op := liq(liq_lss_ptr).op lcu.io.pop <> lss.io.compactor lss.io.compactor_data := lcu.io.pop_data.asUInt io.vu.lresp <> lss.io.resp liq_lss_fire := lss.io.done // Store segment sequencing sss.io.valid := siq_sss_valid sss.io.op := siq(siq_sss_ptr).op scu.io.push <> sss.io.compactor scu.io.push_data := sss.io.compactor_data sss.io.stdata <> io.vu.sdata siq_sss_fire := sss.io.done // Store address sequencing val sas_order_block = (0 until vParams.vliqEntries).map { i => val addr_conflict = liq(i).overlaps(siq(siq_sas_ptr)) liq_valids(i) && addr_conflict && siq(siq_sas_ptr).ld_dep_mask(i) }.orR sas.io.valid := siq_sas_valid && !sas_order_block && !siq(siq_sas_ptr).op.fast_sg sas.io.lsiq_id := siq_sas_ptr sas.io.op := siq(siq_sas_ptr).op siq_sas_fire := Mux(siq(siq_sas_ptr).op.fast_sg, sgas.map(_.io.done && maskindex_scatter).getOrElse(false.B), sas.io.done) val store_req_q = Module(new DCEQueue(new MemRequest(dLenB, dmemTagBits), 2)) store_req_q.io.enq <> sas.io.req store_req_q.io.enq.bits.store := true.B store_req_q.io.enq.bits.data := VecInit(scu.io.pop_data.map(_.data)).asUInt store_req_q.io.enq.bits.mask := VecInit(scu.io.pop_data.map(_.mask)).asUInt & sas.io.req.bits.mask val store_rob = Module(new ReorderBuffer(Bool(), vParams.vsifqEntries)) sas.io.tag <> store_rob.io.reserve store_rob.io.reserve.ready := sas.io.tag.ready && sas.io.req.valid sas.io.out.ready := sifq.io.enq.ready && scu.io.pop.ready sifq.io.enq.valid := sas.io.out.valid && scu.io.pop.ready sifq.io.enq.bits := sas.io.out.bits scu.io.pop.valid := sas.io.out.valid && sifq.io.enq.ready when (scu.io.pop.fire) { for (i <- 0 until dLenB) { assert(scu.io.pop_data(i).debug_id === sas.io.op.debug_id || i.U < scu.io.pop.bits.head || (i.U >= scu.io.pop.bits.tail && scu.io.pop.bits.tail =/= 0.U)) } } scu.io.pop.bits.head := sas.io.out.bits.head scu.io.pop.bits.tail := sas.io.out.bits.tail sgas.foreach { sgas => sgas.io.store_pop.ready := false.B sgas.io.store_data := scu.io.pop_data.map(_.data) when (maskindex_scatter && !store_rob.io.busy) { sgas.io.store_pop.ready := scu.io.pop.ready scu.io.pop.valid := sgas.io.store_pop.valid scu.io.pop.bits := sgas.io.store_pop.bits } } store_rob.io.push.valid := io.dmem.store_ack.valid store_rob.io.push.bits.tag := io.dmem.store_ack.bits.tag store_rob.io.push.bits.data := DontCare sifq.io.deq.ready := sifq.io.deq.bits.masked || store_rob.io.deq.valid store_rob.io.deq.ready := !sifq.io.deq.bits.masked && sifq.io.deq.valid when (store_rob.io.deq.valid) { assert(sifq.io.deq.valid) } siq_deq_fire := sifq.io.deq.fire && sifq.io.deq.bits.last sgas.foreach { sgas => when (maskindex_scatter && sgas.io.valid && sgas.io.done) { siq_deq_fire := true.B } } if (vParams.latencyInject) { val latency = Wire(UInt(32.W)) latency := PlusArg("saturn_mem_latency") val delay_timer = RegInit(0.U(64.W)) delay_timer := delay_timer + 1.U val load_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64)) val store_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64)) load_delay.io.timer := delay_timer store_delay.io.timer := delay_timer load_delay.io.delay := latency store_delay.io.delay := latency load_delay.io.enq <> load_arb.io.out store_delay.io.enq <> store_req_q.io.deq io.dmem.load_req <> load_delay.io.deq io.dmem.store_req <> store_delay.io.deq } else { io.dmem.load_req <> load_arb.io.out io.dmem.store_req <> store_req_q.io.deq } io.dmem.load_req.bits.mask := ~(0.U(dLenB.W)) io.busy := liq_valids.orR || siq_valids.orR }
module VectorMemUnit( // @[Mem.scala:86:7] input clock, // @[Mem.scala:86:7] input reset, // @[Mem.scala:86:7] output io_enq_ready, // @[Mem.scala:87:14] input io_enq_valid, // @[Mem.scala:87:14] input [15:0] io_enq_bits_debug_id, // @[Mem.scala:87:14] input [11:0] io_enq_bits_base_offset, // @[Mem.scala:87:14] input [19:0] io_enq_bits_page, // @[Mem.scala:87:14] input [11:0] io_enq_bits_stride, // @[Mem.scala:87:14] input [2:0] io_enq_bits_segstart, // @[Mem.scala:87:14] input [2:0] io_enq_bits_segend, // @[Mem.scala:87:14] input [6:0] io_enq_bits_vstart, // @[Mem.scala:87:14] input [7:0] io_enq_bits_vl, // @[Mem.scala:87:14] input [1:0] io_enq_bits_mop, // @[Mem.scala:87:14] input io_enq_bits_vm, // @[Mem.scala:87:14] input [2:0] io_enq_bits_nf, // @[Mem.scala:87:14] input [1:0] io_enq_bits_idx_size, // @[Mem.scala:87:14] input [1:0] io_enq_bits_elem_size, // @[Mem.scala:87:14] input io_enq_bits_whole_reg, // @[Mem.scala:87:14] input io_enq_bits_store, // @[Mem.scala:87:14] input io_dmem_load_req_ready, // @[Mem.scala:87:14] output io_dmem_load_req_valid, // @[Mem.scala:87:14] output [39:0] io_dmem_load_req_bits_addr, // @[Mem.scala:87:14] output [3:0] io_dmem_load_req_bits_tag, // @[Mem.scala:87:14] input io_dmem_load_resp_valid, // @[Mem.scala:87:14] input [127:0] io_dmem_load_resp_bits_data, // @[Mem.scala:87:14] input [3:0] io_dmem_load_resp_bits_tag, // @[Mem.scala:87:14] input io_dmem_store_req_ready, // @[Mem.scala:87:14] output io_dmem_store_req_valid, // @[Mem.scala:87:14] output [39:0] io_dmem_store_req_bits_addr, // @[Mem.scala:87:14] output [127:0] io_dmem_store_req_bits_data, // @[Mem.scala:87:14] output [15:0] io_dmem_store_req_bits_mask, // @[Mem.scala:87:14] output [3:0] io_dmem_store_req_bits_tag, // @[Mem.scala:87:14] input io_dmem_store_ack_valid, // @[Mem.scala:87:14] input [3:0] io_dmem_store_ack_bits_tag, // @[Mem.scala:87:14] input [39:0] io_scalar_check_addr, // @[Mem.scala:87:14] input io_scalar_check_store, // @[Mem.scala:87:14] output io_scalar_check_conflict, // @[Mem.scala:87:14] input io_vu_lresp_ready, // @[Mem.scala:87:14] output io_vu_lresp_valid, // @[Mem.scala:87:14] output [127:0] io_vu_lresp_bits_data, // @[Mem.scala:87:14] output [15:0] io_vu_lresp_bits_debug_id, // @[Mem.scala:87:14] output io_vu_sdata_ready, // @[Mem.scala:87:14] input io_vu_sdata_valid, // @[Mem.scala:87:14] input [127:0] io_vu_sdata_bits_stdata, // @[Mem.scala:87:14] input [15:0] io_vu_sdata_bits_stmask, // @[Mem.scala:87:14] input [15:0] io_vu_sdata_bits_debug_id, // @[Mem.scala:87:14] input io_vu_mask_pop_ready, // @[Mem.scala:87:14] output io_vu_mask_pop_valid, // @[Mem.scala:87:14] input io_vu_mask_data_0, // @[Mem.scala:87:14] input io_vu_index_pop_ready, // @[Mem.scala:87:14] output io_vu_index_pop_valid, // @[Mem.scala:87:14] output [3:0] io_vu_index_pop_bits_tail, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_0, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_1, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_2, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_3, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_4, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_5, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_6, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_7, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_8, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_9, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_10, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_11, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_12, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_13, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_14, // @[Mem.scala:87:14] input [7:0] io_vu_index_data_15, // @[Mem.scala:87:14] output io_busy // @[Mem.scala:87:14] ); wire siq_deq_fire; // @[Decoupled.scala:51:35] wire _store_rob_io_reserve_valid; // @[Mem.scala:338:25] wire [3:0] _store_rob_io_reserve_bits; // @[Mem.scala:338:25] wire _store_rob_io_deq_valid; // @[Mem.scala:338:25] wire _store_req_q_io_enq_ready; // @[Mem.scala:332:27] wire _store_req_q_io_deq_valid; // @[Mem.scala:332:27] wire _load_arb_io_in_0_ready; // @[Mem.scala:279:24] wire _load_arb_io_in_1_ready; // @[Mem.scala:279:24] wire _sifq_io_enq_ready; // @[Mem.scala:114:20] wire _sifq_io_deq_valid; // @[Mem.scala:114:20] wire _sifq_io_deq_bits_masked; // @[Mem.scala:114:20] wire _sifq_io_deq_bits_last; // @[Mem.scala:114:20] wire _sas_io_done; // @[Mem.scala:113:19] wire _sas_io_tag_ready; // @[Mem.scala:113:19] wire [1:0] _sas_io_maskindex_eew; // @[Mem.scala:113:19] wire _sas_io_maskindex_needs_mask; // @[Mem.scala:113:19] wire _sas_io_maskindex_needs_index; // @[Mem.scala:113:19] wire _sas_io_maskindex_ready; // @[Mem.scala:113:19] wire _sas_io_req_valid; // @[Mem.scala:113:19] wire [39:0] _sas_io_req_bits_addr; // @[Mem.scala:113:19] wire [15:0] _sas_io_req_bits_mask; // @[Mem.scala:113:19] wire [3:0] _sas_io_req_bits_tag; // @[Mem.scala:113:19] wire _sas_io_out_valid; // @[Mem.scala:113:19] wire [3:0] _sas_io_out_bits_head; // @[Mem.scala:113:19] wire [3:0] _sas_io_out_bits_tail; // @[Mem.scala:113:19] wire _sas_io_out_bits_masked; // @[Mem.scala:113:19] wire _sas_io_out_bits_last; // @[Mem.scala:113:19] wire _sss_io_done; // @[Mem.scala:112:19] wire _sss_io_compactor_valid; // @[Mem.scala:112:19] wire [3:0] _sss_io_compactor_bits_head; // @[Mem.scala:112:19] wire [3:0] _sss_io_compactor_bits_tail; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_0_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_0_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_0_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_1_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_1_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_1_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_2_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_2_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_2_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_3_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_3_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_3_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_4_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_4_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_4_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_5_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_5_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_5_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_6_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_6_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_6_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_7_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_7_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_7_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_8_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_8_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_8_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_9_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_9_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_9_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_10_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_10_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_10_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_11_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_11_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_11_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_12_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_12_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_12_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_13_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_13_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_13_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_14_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_14_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_14_mask; // @[Mem.scala:112:19] wire [15:0] _sss_io_compactor_data_15_debug_id; // @[Mem.scala:112:19] wire [7:0] _sss_io_compactor_data_15_data; // @[Mem.scala:112:19] wire _sss_io_compactor_data_15_mask; // @[Mem.scala:112:19] wire _scu_io_push_ready; // @[Mem.scala:111:19] wire _scu_io_pop_ready; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_0_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_0_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_0_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_1_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_1_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_1_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_2_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_2_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_2_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_3_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_3_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_3_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_4_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_4_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_4_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_5_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_5_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_5_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_6_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_6_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_6_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_7_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_7_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_7_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_8_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_8_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_8_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_9_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_9_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_9_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_10_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_10_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_10_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_11_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_11_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_11_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_12_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_12_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_12_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_13_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_13_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_13_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_14_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_14_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_14_mask; // @[Mem.scala:111:19] wire [15:0] _scu_io_pop_data_15_debug_id; // @[Mem.scala:111:19] wire [7:0] _scu_io_pop_data_15_data; // @[Mem.scala:111:19] wire _scu_io_pop_data_15_mask; // @[Mem.scala:111:19] wire _lss_io_done; // @[Mem.scala:109:19] wire _lss_io_compactor_valid; // @[Mem.scala:109:19] wire [3:0] _lss_io_compactor_bits_head; // @[Mem.scala:109:19] wire [3:0] _lss_io_compactor_bits_tail; // @[Mem.scala:109:19] wire _lcu_io_push_ready; // @[Mem.scala:108:19] wire _lcu_io_pop_ready; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_0; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_1; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_2; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_3; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_4; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_5; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_6; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_7; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_8; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_9; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_10; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_11; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_12; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_13; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_14; // @[Mem.scala:108:19] wire [7:0] _lcu_io_pop_data_15; // @[Mem.scala:108:19] wire _lifq_io_reserve_valid; // @[Mem.scala:107:20] wire [2:0] _lifq_io_reserve_bits; // @[Mem.scala:107:20] wire [1:0] _lifq_io_replay_liq_id; // @[Mem.scala:107:20] wire _lifq_io_replay_valid; // @[Mem.scala:107:20] wire [39:0] _lifq_io_replay_bits_addr; // @[Mem.scala:107:20] wire [3:0] _lifq_io_replay_bits_tag; // @[Mem.scala:107:20] wire _lifq_io_deq_valid; // @[Mem.scala:107:20] wire [3:0] _lifq_io_deq_bits_head; // @[Mem.scala:107:20] wire [3:0] _lifq_io_deq_bits_tail; // @[Mem.scala:107:20] wire [127:0] _lifq_io_deq_data; // @[Mem.scala:107:20] wire _las_io_done; // @[Mem.scala:106:19] wire _las_io_tag_ready; // @[Mem.scala:106:19] wire [1:0] _las_io_maskindex_eew; // @[Mem.scala:106:19] wire _las_io_maskindex_needs_mask; // @[Mem.scala:106:19] wire _las_io_maskindex_needs_index; // @[Mem.scala:106:19] wire _las_io_maskindex_ready; // @[Mem.scala:106:19] wire _las_io_req_valid; // @[Mem.scala:106:19] wire [39:0] _las_io_req_bits_addr; // @[Mem.scala:106:19] wire [3:0] _las_io_req_bits_tag; // @[Mem.scala:106:19] wire [3:0] _las_io_out_bits_head; // @[Mem.scala:106:19] wire [3:0] _las_io_out_bits_tail; // @[Mem.scala:106:19] wire _las_io_out_bits_masked; // @[Mem.scala:106:19] wire [1:0] _las_io_out_bits_lsiq_id; // @[Mem.scala:106:19] wire [11:0] _las_io_out_bits_page_offset; // @[Mem.scala:106:19] reg [15:0] liq_0_op_debug_id; // @[Mem.scala:116:16] reg [11:0] liq_0_op_base_offset; // @[Mem.scala:116:16] reg [19:0] liq_0_op_page; // @[Mem.scala:116:16] reg [11:0] liq_0_op_stride; // @[Mem.scala:116:16] reg [2:0] liq_0_op_segstart; // @[Mem.scala:116:16] reg [2:0] liq_0_op_segend; // @[Mem.scala:116:16] reg [6:0] liq_0_op_vstart; // @[Mem.scala:116:16] reg [7:0] liq_0_op_vl; // @[Mem.scala:116:16] reg [1:0] liq_0_op_mop; // @[Mem.scala:116:16] reg liq_0_op_vm; // @[Mem.scala:116:16] reg [2:0] liq_0_op_nf; // @[Mem.scala:116:16] reg [1:0] liq_0_op_idx_size; // @[Mem.scala:116:16] reg [1:0] liq_0_op_elem_size; // @[Mem.scala:116:16] reg liq_0_op_whole_reg; // @[Mem.scala:116:16] reg liq_0_op_fast_sg; // @[Mem.scala:116:16] reg [11:0] liq_0_bound_offset; // @[Mem.scala:116:16] reg liq_0_st_dep_mask_0; // @[Mem.scala:116:16] reg liq_0_st_dep_mask_1; // @[Mem.scala:116:16] reg liq_0_st_dep_mask_2; // @[Mem.scala:116:16] reg liq_0_st_dep_mask_3; // @[Mem.scala:116:16] reg [15:0] liq_1_op_debug_id; // @[Mem.scala:116:16] reg [11:0] liq_1_op_base_offset; // @[Mem.scala:116:16] reg [19:0] liq_1_op_page; // @[Mem.scala:116:16] reg [11:0] liq_1_op_stride; // @[Mem.scala:116:16] reg [2:0] liq_1_op_segstart; // @[Mem.scala:116:16] reg [2:0] liq_1_op_segend; // @[Mem.scala:116:16] reg [6:0] liq_1_op_vstart; // @[Mem.scala:116:16] reg [7:0] liq_1_op_vl; // @[Mem.scala:116:16] reg [1:0] liq_1_op_mop; // @[Mem.scala:116:16] reg liq_1_op_vm; // @[Mem.scala:116:16] reg [2:0] liq_1_op_nf; // @[Mem.scala:116:16] reg [1:0] liq_1_op_idx_size; // @[Mem.scala:116:16] reg [1:0] liq_1_op_elem_size; // @[Mem.scala:116:16] reg liq_1_op_whole_reg; // @[Mem.scala:116:16] reg liq_1_op_fast_sg; // @[Mem.scala:116:16] reg [11:0] liq_1_bound_offset; // @[Mem.scala:116:16] reg liq_1_st_dep_mask_0; // @[Mem.scala:116:16] reg liq_1_st_dep_mask_1; // @[Mem.scala:116:16] reg liq_1_st_dep_mask_2; // @[Mem.scala:116:16] reg liq_1_st_dep_mask_3; // @[Mem.scala:116:16] reg [15:0] liq_2_op_debug_id; // @[Mem.scala:116:16] reg [11:0] liq_2_op_base_offset; // @[Mem.scala:116:16] reg [19:0] liq_2_op_page; // @[Mem.scala:116:16] reg [11:0] liq_2_op_stride; // @[Mem.scala:116:16] reg [2:0] liq_2_op_segstart; // @[Mem.scala:116:16] reg [2:0] liq_2_op_segend; // @[Mem.scala:116:16] reg [6:0] liq_2_op_vstart; // @[Mem.scala:116:16] reg [7:0] liq_2_op_vl; // @[Mem.scala:116:16] reg [1:0] liq_2_op_mop; // @[Mem.scala:116:16] reg liq_2_op_vm; // @[Mem.scala:116:16] reg [2:0] liq_2_op_nf; // @[Mem.scala:116:16] reg [1:0] liq_2_op_idx_size; // @[Mem.scala:116:16] reg [1:0] liq_2_op_elem_size; // @[Mem.scala:116:16] reg liq_2_op_whole_reg; // @[Mem.scala:116:16] reg liq_2_op_fast_sg; // @[Mem.scala:116:16] reg [11:0] liq_2_bound_offset; // @[Mem.scala:116:16] reg liq_2_st_dep_mask_0; // @[Mem.scala:116:16] reg liq_2_st_dep_mask_1; // @[Mem.scala:116:16] reg liq_2_st_dep_mask_2; // @[Mem.scala:116:16] reg liq_2_st_dep_mask_3; // @[Mem.scala:116:16] reg [15:0] liq_3_op_debug_id; // @[Mem.scala:116:16] reg [11:0] liq_3_op_base_offset; // @[Mem.scala:116:16] reg [19:0] liq_3_op_page; // @[Mem.scala:116:16] reg [11:0] liq_3_op_stride; // @[Mem.scala:116:16] reg [2:0] liq_3_op_segstart; // @[Mem.scala:116:16] reg [2:0] liq_3_op_segend; // @[Mem.scala:116:16] reg [6:0] liq_3_op_vstart; // @[Mem.scala:116:16] reg [7:0] liq_3_op_vl; // @[Mem.scala:116:16] reg [1:0] liq_3_op_mop; // @[Mem.scala:116:16] reg liq_3_op_vm; // @[Mem.scala:116:16] reg [2:0] liq_3_op_nf; // @[Mem.scala:116:16] reg [1:0] liq_3_op_idx_size; // @[Mem.scala:116:16] reg [1:0] liq_3_op_elem_size; // @[Mem.scala:116:16] reg liq_3_op_whole_reg; // @[Mem.scala:116:16] reg liq_3_op_fast_sg; // @[Mem.scala:116:16] reg [11:0] liq_3_bound_offset; // @[Mem.scala:116:16] reg liq_3_st_dep_mask_0; // @[Mem.scala:116:16] reg liq_3_st_dep_mask_1; // @[Mem.scala:116:16] reg liq_3_st_dep_mask_2; // @[Mem.scala:116:16] reg liq_3_st_dep_mask_3; // @[Mem.scala:116:16] reg liq_valids_0; // @[Mem.scala:117:30] reg liq_valids_1; // @[Mem.scala:117:30] reg liq_valids_2; // @[Mem.scala:117:30] reg liq_valids_3; // @[Mem.scala:117:30] reg liq_las_0; // @[Mem.scala:118:30] reg liq_las_1; // @[Mem.scala:118:30] reg liq_las_2; // @[Mem.scala:118:30] reg liq_las_3; // @[Mem.scala:118:30] reg [1:0] liq_enq_ptr; // @[Mem.scala:119:30] reg [1:0] liq_las_ptr; // @[Mem.scala:120:30] reg [1:0] liq_lss_ptr; // @[Mem.scala:121:30] wire [3:0] _GEN = {{liq_valids_3}, {liq_valids_2}, {liq_valids_1}, {liq_valids_0}}; // @[Mem.scala:117:30, :127:23] wire _GEN_0 = _GEN[liq_enq_ptr]; // @[Mem.scala:119:30, :127:23] wire [3:0] _GEN_1 = {{liq_las_3}, {liq_las_2}, {liq_las_1}, {liq_las_0}}; // @[Mem.scala:118:30, :128:23] wire liq_las_valid = ~_GEN_1[liq_las_ptr] & _GEN[liq_las_ptr]; // @[Mem.scala:120:30, :127:23, :128:{23,45}] reg [15:0] siq_0_op_debug_id; // @[Mem.scala:131:16] reg [11:0] siq_0_op_base_offset; // @[Mem.scala:131:16] reg [19:0] siq_0_op_page; // @[Mem.scala:131:16] reg [11:0] siq_0_op_stride; // @[Mem.scala:131:16] reg [2:0] siq_0_op_segstart; // @[Mem.scala:131:16] reg [2:0] siq_0_op_segend; // @[Mem.scala:131:16] reg [6:0] siq_0_op_vstart; // @[Mem.scala:131:16] reg [7:0] siq_0_op_vl; // @[Mem.scala:131:16] reg [1:0] siq_0_op_mop; // @[Mem.scala:131:16] reg siq_0_op_vm; // @[Mem.scala:131:16] reg [2:0] siq_0_op_nf; // @[Mem.scala:131:16] reg [1:0] siq_0_op_idx_size; // @[Mem.scala:131:16] reg [1:0] siq_0_op_elem_size; // @[Mem.scala:131:16] reg siq_0_op_whole_reg; // @[Mem.scala:131:16] reg siq_0_op_fast_sg; // @[Mem.scala:131:16] reg [11:0] siq_0_bound_offset; // @[Mem.scala:131:16] reg siq_0_ld_dep_mask_0; // @[Mem.scala:131:16] reg siq_0_ld_dep_mask_1; // @[Mem.scala:131:16] reg siq_0_ld_dep_mask_2; // @[Mem.scala:131:16] reg siq_0_ld_dep_mask_3; // @[Mem.scala:131:16] reg [15:0] siq_1_op_debug_id; // @[Mem.scala:131:16] reg [11:0] siq_1_op_base_offset; // @[Mem.scala:131:16] reg [19:0] siq_1_op_page; // @[Mem.scala:131:16] reg [11:0] siq_1_op_stride; // @[Mem.scala:131:16] reg [2:0] siq_1_op_segstart; // @[Mem.scala:131:16] reg [2:0] siq_1_op_segend; // @[Mem.scala:131:16] reg [6:0] siq_1_op_vstart; // @[Mem.scala:131:16] reg [7:0] siq_1_op_vl; // @[Mem.scala:131:16] reg [1:0] siq_1_op_mop; // @[Mem.scala:131:16] reg siq_1_op_vm; // @[Mem.scala:131:16] reg [2:0] siq_1_op_nf; // @[Mem.scala:131:16] reg [1:0] siq_1_op_idx_size; // @[Mem.scala:131:16] reg [1:0] siq_1_op_elem_size; // @[Mem.scala:131:16] reg siq_1_op_whole_reg; // @[Mem.scala:131:16] reg siq_1_op_fast_sg; // @[Mem.scala:131:16] reg [11:0] siq_1_bound_offset; // @[Mem.scala:131:16] reg siq_1_ld_dep_mask_0; // @[Mem.scala:131:16] reg siq_1_ld_dep_mask_1; // @[Mem.scala:131:16] reg siq_1_ld_dep_mask_2; // @[Mem.scala:131:16] reg siq_1_ld_dep_mask_3; // @[Mem.scala:131:16] reg [15:0] siq_2_op_debug_id; // @[Mem.scala:131:16] reg [11:0] siq_2_op_base_offset; // @[Mem.scala:131:16] reg [19:0] siq_2_op_page; // @[Mem.scala:131:16] reg [11:0] siq_2_op_stride; // @[Mem.scala:131:16] reg [2:0] siq_2_op_segstart; // @[Mem.scala:131:16] reg [2:0] siq_2_op_segend; // @[Mem.scala:131:16] reg [6:0] siq_2_op_vstart; // @[Mem.scala:131:16] reg [7:0] siq_2_op_vl; // @[Mem.scala:131:16] reg [1:0] siq_2_op_mop; // @[Mem.scala:131:16] reg siq_2_op_vm; // @[Mem.scala:131:16] reg [2:0] siq_2_op_nf; // @[Mem.scala:131:16] reg [1:0] siq_2_op_idx_size; // @[Mem.scala:131:16] reg [1:0] siq_2_op_elem_size; // @[Mem.scala:131:16] reg siq_2_op_whole_reg; // @[Mem.scala:131:16] reg siq_2_op_fast_sg; // @[Mem.scala:131:16] reg [11:0] siq_2_bound_offset; // @[Mem.scala:131:16] reg siq_2_ld_dep_mask_0; // @[Mem.scala:131:16] reg siq_2_ld_dep_mask_1; // @[Mem.scala:131:16] reg siq_2_ld_dep_mask_2; // @[Mem.scala:131:16] reg siq_2_ld_dep_mask_3; // @[Mem.scala:131:16] reg [15:0] siq_3_op_debug_id; // @[Mem.scala:131:16] reg [11:0] siq_3_op_base_offset; // @[Mem.scala:131:16] reg [19:0] siq_3_op_page; // @[Mem.scala:131:16] reg [11:0] siq_3_op_stride; // @[Mem.scala:131:16] reg [2:0] siq_3_op_segstart; // @[Mem.scala:131:16] reg [2:0] siq_3_op_segend; // @[Mem.scala:131:16] reg [6:0] siq_3_op_vstart; // @[Mem.scala:131:16] reg [7:0] siq_3_op_vl; // @[Mem.scala:131:16] reg [1:0] siq_3_op_mop; // @[Mem.scala:131:16] reg siq_3_op_vm; // @[Mem.scala:131:16] reg [2:0] siq_3_op_nf; // @[Mem.scala:131:16] reg [1:0] siq_3_op_idx_size; // @[Mem.scala:131:16] reg [1:0] siq_3_op_elem_size; // @[Mem.scala:131:16] reg siq_3_op_whole_reg; // @[Mem.scala:131:16] reg siq_3_op_fast_sg; // @[Mem.scala:131:16] reg [11:0] siq_3_bound_offset; // @[Mem.scala:131:16] reg siq_3_ld_dep_mask_0; // @[Mem.scala:131:16] reg siq_3_ld_dep_mask_1; // @[Mem.scala:131:16] reg siq_3_ld_dep_mask_2; // @[Mem.scala:131:16] reg siq_3_ld_dep_mask_3; // @[Mem.scala:131:16] reg siq_valids_0; // @[Mem.scala:132:30] reg siq_valids_1; // @[Mem.scala:132:30] reg siq_valids_2; // @[Mem.scala:132:30] reg siq_valids_3; // @[Mem.scala:132:30] reg siq_sss_0; // @[Mem.scala:133:30] reg siq_sss_1; // @[Mem.scala:133:30] reg siq_sss_2; // @[Mem.scala:133:30] reg siq_sss_3; // @[Mem.scala:133:30] reg siq_sas_0; // @[Mem.scala:134:30] reg siq_sas_1; // @[Mem.scala:134:30] reg siq_sas_2; // @[Mem.scala:134:30] reg siq_sas_3; // @[Mem.scala:134:30] reg [1:0] siq_enq_ptr; // @[Mem.scala:135:30] reg [1:0] siq_sss_ptr; // @[Mem.scala:136:30] reg [1:0] siq_sas_ptr; // @[Mem.scala:137:30] reg [1:0] siq_deq_ptr; // @[Mem.scala:138:30] wire [3:0] _GEN_2 = {{siq_valids_3}, {siq_valids_2}, {siq_valids_1}, {siq_valids_0}}; // @[Mem.scala:132:30, :145:23] wire _GEN_3 = _GEN_2[siq_enq_ptr]; // @[Mem.scala:135:30, :145:23] wire [3:0] _GEN_4 = {{siq_sss_3}, {siq_sss_2}, {siq_sss_1}, {siq_sss_0}}; // @[Mem.scala:133:30, :146:23] wire [3:0] _GEN_5 = {{siq_sas_3}, {siq_sas_2}, {siq_sas_1}, {siq_sas_0}}; // @[Mem.scala:134:30, :147:23] wire siq_sas_valid = ~_GEN_5[siq_sas_ptr] & _GEN_2[siq_sas_ptr]; // @[Mem.scala:137:30, :145:23, :147:{23,45}] wire liq_enq_fire = io_enq_valid & ~_GEN_0 & ~io_enq_bits_store; // @[Mem.scala:127:23, :195:{32,49,52}] wire siq_enq_fire = io_enq_valid & ~_GEN_3 & io_enq_bits_store; // @[Mem.scala:145:23, :196:{32,49}] wire [3:0][11:0] _GEN_6 = {{liq_3_op_base_offset}, {liq_2_op_base_offset}, {liq_1_op_base_offset}, {liq_0_op_base_offset}}; // @[Mem.scala:116:16, :211:46] wire [11:0] las_io_op_base_offset = _GEN_6[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0][19:0] _GEN_7 = {{liq_3_op_page}, {liq_2_op_page}, {liq_1_op_page}, {liq_0_op_page}}; // @[Mem.scala:116:16, :211:46] wire [19:0] las_io_op_page = _GEN_7[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0][11:0] _GEN_8 = {{liq_3_op_stride}, {liq_2_op_stride}, {liq_1_op_stride}, {liq_0_op_stride}}; // @[Mem.scala:116:16, :211:46] wire [3:0][2:0] _GEN_9 = {{liq_3_op_segstart}, {liq_2_op_segstart}, {liq_1_op_segstart}, {liq_0_op_segstart}}; // @[Mem.scala:116:16, :211:46] wire [3:0][2:0] _GEN_10 = {{liq_3_op_segend}, {liq_2_op_segend}, {liq_1_op_segend}, {liq_0_op_segend}}; // @[Mem.scala:116:16, :211:46] wire [3:0][6:0] _GEN_11 = {{liq_3_op_vstart}, {liq_2_op_vstart}, {liq_1_op_vstart}, {liq_0_op_vstart}}; // @[Mem.scala:116:16, :211:46] wire [3:0][7:0] _GEN_12 = {{liq_3_op_vl}, {liq_2_op_vl}, {liq_1_op_vl}, {liq_0_op_vl}}; // @[Mem.scala:116:16, :211:46] wire [3:0][1:0] _GEN_13 = {{liq_3_op_mop}, {liq_2_op_mop}, {liq_1_op_mop}, {liq_0_op_mop}}; // @[Mem.scala:116:16, :211:46] wire [1:0] las_io_op_mop = _GEN_13[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_14 = {{liq_3_op_vm}, {liq_2_op_vm}, {liq_1_op_vm}, {liq_0_op_vm}}; // @[Mem.scala:116:16, :211:46] wire [3:0][2:0] _GEN_15 = {{liq_3_op_nf}, {liq_2_op_nf}, {liq_1_op_nf}, {liq_0_op_nf}}; // @[Mem.scala:116:16, :211:46] wire [3:0][1:0] _GEN_16 = {{liq_3_op_idx_size}, {liq_2_op_idx_size}, {liq_1_op_idx_size}, {liq_0_op_idx_size}}; // @[Mem.scala:116:16, :211:46] wire [3:0][1:0] _GEN_17 = {{liq_3_op_elem_size}, {liq_2_op_elem_size}, {liq_1_op_elem_size}, {liq_0_op_elem_size}}; // @[Mem.scala:116:16, :211:46] wire [3:0] _GEN_18 = {{liq_3_op_whole_reg}, {liq_2_op_whole_reg}, {liq_1_op_whole_reg}, {liq_0_op_whole_reg}}; // @[Mem.scala:116:16, :211:46] wire [3:0] _GEN_19 = {{liq_3_op_fast_sg}, {liq_2_op_fast_sg}, {liq_1_op_fast_sg}, {liq_0_op_fast_sg}}; // @[Mem.scala:116:16, :211:46] wire _GEN_20 = _GEN_19[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0][11:0] _GEN_21 = {{liq_3_bound_offset}, {liq_2_bound_offset}, {liq_1_bound_offset}, {liq_0_bound_offset}}; // @[Mem.scala:116:16, :211:46] wire [11:0] _GEN_22 = _GEN_21[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_23 = {{liq_3_st_dep_mask_0}, {liq_2_st_dep_mask_0}, {liq_1_st_dep_mask_0}, {liq_0_st_dep_mask_0}}; // @[Mem.scala:116:16, :211:46] wire _GEN_24 = _GEN_23[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_25 = {{liq_3_st_dep_mask_1}, {liq_2_st_dep_mask_1}, {liq_1_st_dep_mask_1}, {liq_0_st_dep_mask_1}}; // @[Mem.scala:116:16, :211:46] wire _GEN_26 = _GEN_25[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_27 = {{liq_3_st_dep_mask_2}, {liq_2_st_dep_mask_2}, {liq_1_st_dep_mask_2}, {liq_0_st_dep_mask_2}}; // @[Mem.scala:116:16, :211:46] wire _GEN_28 = _GEN_27[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_29 = {{liq_3_st_dep_mask_3}, {liq_2_st_dep_mask_3}, {liq_1_st_dep_mask_3}, {liq_0_st_dep_mask_3}}; // @[Mem.scala:116:16, :211:46] wire _GEN_30 = _GEN_29[liq_las_ptr]; // @[Mem.scala:120:30, :211:46] wire [3:0] _GEN_31 = {{_GEN_30}, {_GEN_28}, {_GEN_26}, {_GEN_24}}; // @[Mem.scala:211:46] wire las_older_than_sas = liq_las_valid & ~_GEN_31[siq_sas_ptr] | ~siq_sas_valid; // @[Mem.scala:128:45, :137:30, :147:45, :211:{43,46,90,93}] wire maskindex_load = liq_las_valid & las_older_than_sas & ~_GEN_20; // @[Mem.scala:128:45, :211:{46,90}, :212:{41,64,67}] wire [3:0][15:0] _GEN_32 = {{siq_3_op_debug_id}, {siq_2_op_debug_id}, {siq_1_op_debug_id}, {siq_0_op_debug_id}}; // @[Mem.scala:131:16, :213:67] wire [3:0][11:0] _GEN_33 = {{siq_3_op_base_offset}, {siq_2_op_base_offset}, {siq_1_op_base_offset}, {siq_0_op_base_offset}}; // @[Mem.scala:131:16, :213:67] wire [11:0] sas_io_op_base_offset = _GEN_33[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67] wire [3:0][19:0] _GEN_34 = {{siq_3_op_page}, {siq_2_op_page}, {siq_1_op_page}, {siq_0_op_page}}; // @[Mem.scala:131:16, :213:67] wire [19:0] sas_io_op_page = _GEN_34[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67] wire [3:0][11:0] _GEN_35 = {{siq_3_op_stride}, {siq_2_op_stride}, {siq_1_op_stride}, {siq_0_op_stride}}; // @[Mem.scala:131:16, :213:67] wire [3:0][2:0] _GEN_36 = {{siq_3_op_segstart}, {siq_2_op_segstart}, {siq_1_op_segstart}, {siq_0_op_segstart}}; // @[Mem.scala:131:16, :213:67] wire [3:0][2:0] _GEN_37 = {{siq_3_op_segend}, {siq_2_op_segend}, {siq_1_op_segend}, {siq_0_op_segend}}; // @[Mem.scala:131:16, :213:67] wire [3:0][6:0] _GEN_38 = {{siq_3_op_vstart}, {siq_2_op_vstart}, {siq_1_op_vstart}, {siq_0_op_vstart}}; // @[Mem.scala:131:16, :213:67] wire [3:0][7:0] _GEN_39 = {{siq_3_op_vl}, {siq_2_op_vl}, {siq_1_op_vl}, {siq_0_op_vl}}; // @[Mem.scala:131:16, :213:67] wire [3:0][1:0] _GEN_40 = {{siq_3_op_mop}, {siq_2_op_mop}, {siq_1_op_mop}, {siq_0_op_mop}}; // @[Mem.scala:131:16, :213:67] wire [1:0] sas_io_op_mop = _GEN_40[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67] wire [3:0] _GEN_41 = {{siq_3_op_vm}, {siq_2_op_vm}, {siq_1_op_vm}, {siq_0_op_vm}}; // @[Mem.scala:131:16, :213:67] wire [3:0][2:0] _GEN_42 = {{siq_3_op_nf}, {siq_2_op_nf}, {siq_1_op_nf}, {siq_0_op_nf}}; // @[Mem.scala:131:16, :213:67] wire [3:0][1:0] _GEN_43 = {{siq_3_op_idx_size}, {siq_2_op_idx_size}, {siq_1_op_idx_size}, {siq_0_op_idx_size}}; // @[Mem.scala:131:16, :213:67] wire [3:0][1:0] _GEN_44 = {{siq_3_op_elem_size}, {siq_2_op_elem_size}, {siq_1_op_elem_size}, {siq_0_op_elem_size}}; // @[Mem.scala:131:16, :213:67] wire [3:0] _GEN_45 = {{siq_3_op_whole_reg}, {siq_2_op_whole_reg}, {siq_1_op_whole_reg}, {siq_0_op_whole_reg}}; // @[Mem.scala:131:16, :213:67] wire [3:0] _GEN_46 = {{siq_3_op_fast_sg}, {siq_2_op_fast_sg}, {siq_1_op_fast_sg}, {siq_0_op_fast_sg}}; // @[Mem.scala:131:16, :213:67] wire _GEN_47 = _GEN_46[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67] wire [3:0][11:0] _GEN_48 = {{siq_3_bound_offset}, {siq_2_bound_offset}, {siq_1_bound_offset}, {siq_0_bound_offset}}; // @[Mem.scala:131:16, :213:67] wire [11:0] _GEN_49 = _GEN_48[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67] wire [3:0] _GEN_50 = {{siq_3_ld_dep_mask_0}, {siq_2_ld_dep_mask_0}, {siq_1_ld_dep_mask_0}, {siq_0_ld_dep_mask_0}}; // @[Mem.scala:131:16, :213:67] wire [3:0] _GEN_51 = {{siq_3_ld_dep_mask_1}, {siq_2_ld_dep_mask_1}, {siq_1_ld_dep_mask_1}, {siq_0_ld_dep_mask_1}}; // @[Mem.scala:131:16, :213:67] wire [3:0] _GEN_52 = {{siq_3_ld_dep_mask_2}, {siq_2_ld_dep_mask_2}, {siq_1_ld_dep_mask_2}, {siq_0_ld_dep_mask_2}}; // @[Mem.scala:131:16, :213:67] wire [3:0] _GEN_53 = {{siq_3_ld_dep_mask_3}, {siq_2_ld_dep_mask_3}, {siq_1_ld_dep_mask_3}, {siq_0_ld_dep_mask_3}}; // @[Mem.scala:131:16, :213:67] wire maskindex_store = siq_sas_valid & ~las_older_than_sas & ~_GEN_47; // @[Mem.scala:147:45, :211:90, :213:{41,44,64,67}] wire liq_las_fire = ~_GEN_20 & _las_io_done; // @[Mem.scala:106:19, :211:46, :268:22] wire [3:0][15:0] _GEN_54 = {{liq_3_op_debug_id}, {liq_2_op_debug_id}, {liq_1_op_debug_id}, {liq_0_op_debug_id}}; // @[Mem.scala:116:16, :308:13] wire siq_sas_fire = ~_GEN_47 & _sas_io_done; // @[Mem.scala:113:19, :213:67, :330:22] wire scu_io_pop_valid = _sas_io_out_valid & _sifq_io_enq_ready; // @[Mem.scala:113:19, :114:20, :345:40] wire sifq_io_deq_ready = _sifq_io_deq_bits_masked | _store_rob_io_deq_valid; // @[Mem.scala:114:20, :338:25, :371:48]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_37( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /** For determining static tile id */ case object NumTiles extends Field[Int](0) /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. */ case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. */ case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. */ case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /** These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. */ trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /** tileHartIdNode is used to collect publishers and subscribers of hartids. */ val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. */ val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */ val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */ val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. */ val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. */ val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. */ trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. */ trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /** Narrow waist through which all tiles are intended to pass while being instantiated. */ def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /** Connect the port where the tile is the master to a TileLink interconnect. */ def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. */ def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } /** Connect the various interrupts sent to and and raised by the tile. */ def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */ def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /** Function to handle all trace crossings when tile is instantiated inside domains */ def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `β†’`: target of arrow is generated by source * * {{{ * (from the other node) * β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€[[InwardNode.uiParams]]─────────────┐ * ↓ β”‚ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ β”‚ * [[InwardNode.accPI]] β”‚ β”‚ β”‚ * β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ ↓ β”‚ * ↓ β”‚ β”‚ β”‚ * (immobilize after elaboration) (inward port from [[OutwardNode]]) β”‚ ↓ β”‚ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] β”‚ * β”‚ β”‚ ↑ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[OutwardNode.doParams]] β”‚ β”‚ * β”‚ β”‚ β”‚ (from the other node) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ └────────┬─────────────── β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ (from the other node) β”‚ ↓ β”‚ * β”‚ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] β”‚ [[MixedNode.edgesIn]]───┐ β”‚ * β”‚ ↑ ↑ β”‚ β”‚ ↓ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ [[MixedNode.in]] β”‚ * β”‚ β”‚ β”‚ β”‚ ↓ ↑ β”‚ * β”‚ (solve star connection) β”‚ β”‚ β”‚ [[MixedNode.bundleIn]]β”€β”€β”˜ β”‚ * β”œβ”€β”€β”€[[MixedNode.resolveStar]]→─┼────────────────────────────── └────────────────────────────────────┐ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.bundleOut]]─┐ β”‚ β”‚ * β”‚ β”‚ β”‚ ↑ ↓ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.out]] β”‚ β”‚ * β”‚ ↓ ↓ β”‚ ↑ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]β”€β”€β”˜ β”‚ β”‚ * β”‚ β”‚ (from the other node) ↑ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.outer.edgeO]] β”‚ β”‚ * β”‚ β”‚ β”‚ (based on protocol) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * (immobilize after elaboration)β”‚ ↓ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.oBindings]]β”€β”˜ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] β”‚ β”‚ * ↑ (inward port from [[OutwardNode]]) β”‚ β”‚ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.accPO]] β”‚ ↓ β”‚ β”‚ β”‚ * (binding node when elaboration) β”‚ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ * β”‚ ↑ β”‚ β”‚ * β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ * β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TilePRCIDomain( // @[ClockDomain.scala:14:9] output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25] input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_18_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_18_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_18_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_18_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_18_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_18_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_18_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_18_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_18_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_18_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_18_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_18_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_18_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_18_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_18_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_18_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_18_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_18_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_18_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_18_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_18_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_17_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_17_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_17_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_17_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_17_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_17_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_17_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_17_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_17_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_17_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_17_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_17_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_17_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_17_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_17_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_17_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_16_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_16_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_16_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_16_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_16_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_16_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_16_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_16_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_16_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_16_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_16_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_16_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_16_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_16_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_16_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_16_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_15_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_15_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_15_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_15_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_15_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_15_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_15_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_15_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_15_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_15_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_15_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_15_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_15_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_15_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_15_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_15_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_14_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_14_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_14_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_14_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_14_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_14_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_14_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_14_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_14_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_14_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_14_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_14_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_14_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_14_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_14_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_14_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_13_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_13_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_13_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_13_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_13_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_13_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_13_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_13_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_13_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_13_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_13_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_13_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_13_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_13_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_13_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_13_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_12_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_12_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_12_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_12_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_12_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_12_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_12_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_12_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_12_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_12_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_12_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_12_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_12_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_12_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_12_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_12_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_11_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_11_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_11_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_11_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_11_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_11_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_11_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_11_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_11_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_11_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_11_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_11_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_11_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_11_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_11_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_11_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_10_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_10_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_10_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_10_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_10_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_10_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_10_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_10_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_10_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_10_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_10_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_10_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_10_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_10_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_10_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_10_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_9_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_9_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_9_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_9_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_9_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_9_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_9_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_9_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_9_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_9_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_9_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_9_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_9_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_9_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_9_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_9_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_8_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_8_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_8_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_8_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_8_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_8_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_8_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_8_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_8_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_8_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_8_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_8_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_8_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_8_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_8_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_8_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_master_clock_xing_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_master_clock_xing_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_master_clock_xing_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_a_ready_0 = auto_tl_master_clock_xing_out_18_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_b_valid_0 = auto_tl_master_clock_xing_out_18_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_18_b_bits_param_0 = auto_tl_master_clock_xing_out_18_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_18_b_bits_address_0 = auto_tl_master_clock_xing_out_18_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_c_ready_0 = auto_tl_master_clock_xing_out_18_c_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_d_valid_0 = auto_tl_master_clock_xing_out_18_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_d_bits_opcode_0 = auto_tl_master_clock_xing_out_18_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_18_d_bits_param_0 = auto_tl_master_clock_xing_out_18_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_18_d_bits_size_0 = auto_tl_master_clock_xing_out_18_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_18_d_bits_source_0 = auto_tl_master_clock_xing_out_18_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_d_bits_sink_0 = auto_tl_master_clock_xing_out_18_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_d_bits_denied_0 = auto_tl_master_clock_xing_out_18_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_18_d_bits_data_0 = auto_tl_master_clock_xing_out_18_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_18_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_a_ready_0 = auto_tl_master_clock_xing_out_17_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_d_valid_0 = auto_tl_master_clock_xing_out_17_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_17_d_bits_opcode_0 = auto_tl_master_clock_xing_out_17_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_17_d_bits_param_0 = auto_tl_master_clock_xing_out_17_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_17_d_bits_size_0 = auto_tl_master_clock_xing_out_17_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_17_d_bits_source_0 = auto_tl_master_clock_xing_out_17_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_17_d_bits_sink_0 = auto_tl_master_clock_xing_out_17_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_d_bits_denied_0 = auto_tl_master_clock_xing_out_17_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_17_d_bits_data_0 = auto_tl_master_clock_xing_out_17_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_17_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_a_ready_0 = auto_tl_master_clock_xing_out_16_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_d_valid_0 = auto_tl_master_clock_xing_out_16_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_16_d_bits_opcode_0 = auto_tl_master_clock_xing_out_16_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_16_d_bits_param_0 = auto_tl_master_clock_xing_out_16_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_16_d_bits_size_0 = auto_tl_master_clock_xing_out_16_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_16_d_bits_source_0 = auto_tl_master_clock_xing_out_16_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_16_d_bits_sink_0 = auto_tl_master_clock_xing_out_16_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_d_bits_denied_0 = auto_tl_master_clock_xing_out_16_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_16_d_bits_data_0 = auto_tl_master_clock_xing_out_16_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_16_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_a_ready_0 = auto_tl_master_clock_xing_out_15_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_d_valid_0 = auto_tl_master_clock_xing_out_15_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_15_d_bits_opcode_0 = auto_tl_master_clock_xing_out_15_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_15_d_bits_param_0 = auto_tl_master_clock_xing_out_15_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_15_d_bits_size_0 = auto_tl_master_clock_xing_out_15_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_15_d_bits_source_0 = auto_tl_master_clock_xing_out_15_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_15_d_bits_sink_0 = auto_tl_master_clock_xing_out_15_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_d_bits_denied_0 = auto_tl_master_clock_xing_out_15_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_15_d_bits_data_0 = auto_tl_master_clock_xing_out_15_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_15_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_a_ready_0 = auto_tl_master_clock_xing_out_14_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_d_valid_0 = auto_tl_master_clock_xing_out_14_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_14_d_bits_opcode_0 = auto_tl_master_clock_xing_out_14_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_14_d_bits_param_0 = auto_tl_master_clock_xing_out_14_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_14_d_bits_size_0 = auto_tl_master_clock_xing_out_14_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_14_d_bits_source_0 = auto_tl_master_clock_xing_out_14_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_14_d_bits_sink_0 = auto_tl_master_clock_xing_out_14_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_d_bits_denied_0 = auto_tl_master_clock_xing_out_14_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_14_d_bits_data_0 = auto_tl_master_clock_xing_out_14_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_14_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_a_ready_0 = auto_tl_master_clock_xing_out_13_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_d_valid_0 = auto_tl_master_clock_xing_out_13_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_13_d_bits_opcode_0 = auto_tl_master_clock_xing_out_13_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_13_d_bits_param_0 = auto_tl_master_clock_xing_out_13_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_13_d_bits_size_0 = auto_tl_master_clock_xing_out_13_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_13_d_bits_source_0 = auto_tl_master_clock_xing_out_13_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_13_d_bits_sink_0 = auto_tl_master_clock_xing_out_13_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_d_bits_denied_0 = auto_tl_master_clock_xing_out_13_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_13_d_bits_data_0 = auto_tl_master_clock_xing_out_13_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_13_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_a_ready_0 = auto_tl_master_clock_xing_out_12_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_d_valid_0 = auto_tl_master_clock_xing_out_12_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_12_d_bits_opcode_0 = auto_tl_master_clock_xing_out_12_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_12_d_bits_param_0 = auto_tl_master_clock_xing_out_12_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_12_d_bits_size_0 = auto_tl_master_clock_xing_out_12_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_12_d_bits_source_0 = auto_tl_master_clock_xing_out_12_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_12_d_bits_sink_0 = auto_tl_master_clock_xing_out_12_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_d_bits_denied_0 = auto_tl_master_clock_xing_out_12_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_12_d_bits_data_0 = auto_tl_master_clock_xing_out_12_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_12_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_a_ready_0 = auto_tl_master_clock_xing_out_11_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_d_valid_0 = auto_tl_master_clock_xing_out_11_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_11_d_bits_opcode_0 = auto_tl_master_clock_xing_out_11_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_11_d_bits_param_0 = auto_tl_master_clock_xing_out_11_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_11_d_bits_size_0 = auto_tl_master_clock_xing_out_11_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_11_d_bits_source_0 = auto_tl_master_clock_xing_out_11_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_11_d_bits_sink_0 = auto_tl_master_clock_xing_out_11_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_d_bits_denied_0 = auto_tl_master_clock_xing_out_11_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_11_d_bits_data_0 = auto_tl_master_clock_xing_out_11_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_11_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_a_ready_0 = auto_tl_master_clock_xing_out_10_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_d_valid_0 = auto_tl_master_clock_xing_out_10_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_10_d_bits_opcode_0 = auto_tl_master_clock_xing_out_10_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_10_d_bits_param_0 = auto_tl_master_clock_xing_out_10_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_10_d_bits_size_0 = auto_tl_master_clock_xing_out_10_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_10_d_bits_source_0 = auto_tl_master_clock_xing_out_10_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_10_d_bits_sink_0 = auto_tl_master_clock_xing_out_10_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_d_bits_denied_0 = auto_tl_master_clock_xing_out_10_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_10_d_bits_data_0 = auto_tl_master_clock_xing_out_10_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_10_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_a_ready_0 = auto_tl_master_clock_xing_out_9_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_d_valid_0 = auto_tl_master_clock_xing_out_9_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_9_d_bits_opcode_0 = auto_tl_master_clock_xing_out_9_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_9_d_bits_param_0 = auto_tl_master_clock_xing_out_9_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_9_d_bits_size_0 = auto_tl_master_clock_xing_out_9_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_9_d_bits_source_0 = auto_tl_master_clock_xing_out_9_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_9_d_bits_sink_0 = auto_tl_master_clock_xing_out_9_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_d_bits_denied_0 = auto_tl_master_clock_xing_out_9_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_9_d_bits_data_0 = auto_tl_master_clock_xing_out_9_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_9_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_a_ready_0 = auto_tl_master_clock_xing_out_8_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_d_valid_0 = auto_tl_master_clock_xing_out_8_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_8_d_bits_opcode_0 = auto_tl_master_clock_xing_out_8_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_8_d_bits_param_0 = auto_tl_master_clock_xing_out_8_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_8_d_bits_size_0 = auto_tl_master_clock_xing_out_8_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_8_d_bits_source_0 = auto_tl_master_clock_xing_out_8_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_8_d_bits_sink_0 = auto_tl_master_clock_xing_out_8_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_d_bits_denied_0 = auto_tl_master_clock_xing_out_8_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_8_d_bits_data_0 = auto_tl_master_clock_xing_out_8_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_8_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_a_ready_0 = auto_tl_master_clock_xing_out_7_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_d_valid_0 = auto_tl_master_clock_xing_out_7_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_7_d_bits_opcode_0 = auto_tl_master_clock_xing_out_7_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_7_d_bits_param_0 = auto_tl_master_clock_xing_out_7_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_7_d_bits_size_0 = auto_tl_master_clock_xing_out_7_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_7_d_bits_source_0 = auto_tl_master_clock_xing_out_7_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_7_d_bits_sink_0 = auto_tl_master_clock_xing_out_7_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_d_bits_denied_0 = auto_tl_master_clock_xing_out_7_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_7_d_bits_data_0 = auto_tl_master_clock_xing_out_7_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_7_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_a_ready_0 = auto_tl_master_clock_xing_out_6_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_d_valid_0 = auto_tl_master_clock_xing_out_6_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_6_d_bits_opcode_0 = auto_tl_master_clock_xing_out_6_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_6_d_bits_param_0 = auto_tl_master_clock_xing_out_6_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_6_d_bits_size_0 = auto_tl_master_clock_xing_out_6_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_6_d_bits_source_0 = auto_tl_master_clock_xing_out_6_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_6_d_bits_sink_0 = auto_tl_master_clock_xing_out_6_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_d_bits_denied_0 = auto_tl_master_clock_xing_out_6_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_6_d_bits_data_0 = auto_tl_master_clock_xing_out_6_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_6_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_a_ready_0 = auto_tl_master_clock_xing_out_5_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_d_valid_0 = auto_tl_master_clock_xing_out_5_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_5_d_bits_opcode_0 = auto_tl_master_clock_xing_out_5_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_5_d_bits_param_0 = auto_tl_master_clock_xing_out_5_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_5_d_bits_size_0 = auto_tl_master_clock_xing_out_5_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_5_d_bits_source_0 = auto_tl_master_clock_xing_out_5_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_5_d_bits_sink_0 = auto_tl_master_clock_xing_out_5_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_d_bits_denied_0 = auto_tl_master_clock_xing_out_5_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_5_d_bits_data_0 = auto_tl_master_clock_xing_out_5_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_5_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_a_ready_0 = auto_tl_master_clock_xing_out_4_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_d_valid_0 = auto_tl_master_clock_xing_out_4_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_4_d_bits_opcode_0 = auto_tl_master_clock_xing_out_4_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_4_d_bits_param_0 = auto_tl_master_clock_xing_out_4_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_4_d_bits_size_0 = auto_tl_master_clock_xing_out_4_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_4_d_bits_source_0 = auto_tl_master_clock_xing_out_4_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_4_d_bits_sink_0 = auto_tl_master_clock_xing_out_4_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_d_bits_denied_0 = auto_tl_master_clock_xing_out_4_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_4_d_bits_data_0 = auto_tl_master_clock_xing_out_4_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_4_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_a_ready_0 = auto_tl_master_clock_xing_out_3_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_d_valid_0 = auto_tl_master_clock_xing_out_3_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_3_d_bits_opcode_0 = auto_tl_master_clock_xing_out_3_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_3_d_bits_param_0 = auto_tl_master_clock_xing_out_3_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_3_d_bits_size_0 = auto_tl_master_clock_xing_out_3_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_3_d_bits_source_0 = auto_tl_master_clock_xing_out_3_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_3_d_bits_sink_0 = auto_tl_master_clock_xing_out_3_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_d_bits_denied_0 = auto_tl_master_clock_xing_out_3_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_3_d_bits_data_0 = auto_tl_master_clock_xing_out_3_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_3_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_a_ready_0 = auto_tl_master_clock_xing_out_2_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_d_valid_0 = auto_tl_master_clock_xing_out_2_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_2_d_bits_opcode_0 = auto_tl_master_clock_xing_out_2_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_2_d_bits_param_0 = auto_tl_master_clock_xing_out_2_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_2_d_bits_size_0 = auto_tl_master_clock_xing_out_2_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_2_d_bits_source_0 = auto_tl_master_clock_xing_out_2_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_2_d_bits_sink_0 = auto_tl_master_clock_xing_out_2_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_d_bits_denied_0 = auto_tl_master_clock_xing_out_2_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_2_d_bits_data_0 = auto_tl_master_clock_xing_out_2_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_2_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_a_ready_0 = auto_tl_master_clock_xing_out_1_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_d_valid_0 = auto_tl_master_clock_xing_out_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_1_d_bits_opcode_0 = auto_tl_master_clock_xing_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_1_d_bits_param_0 = auto_tl_master_clock_xing_out_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_1_d_bits_size_0 = auto_tl_master_clock_xing_out_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_1_d_bits_source_0 = auto_tl_master_clock_xing_out_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_1_d_bits_sink_0 = auto_tl_master_clock_xing_out_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_d_bits_denied_0 = auto_tl_master_clock_xing_out_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_1_d_bits_data_0 = auto_tl_master_clock_xing_out_1_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_a_ready_0 = auto_tl_master_clock_xing_out_0_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_d_valid_0 = auto_tl_master_clock_xing_out_0_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_0_d_bits_opcode_0 = auto_tl_master_clock_xing_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_0_d_bits_param_0 = auto_tl_master_clock_xing_out_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_0_d_bits_size_0 = auto_tl_master_clock_xing_out_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_0_d_bits_source_0 = auto_tl_master_clock_xing_out_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_0_d_bits_sink_0 = auto_tl_master_clock_xing_out_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_d_bits_denied_0 = auto_tl_master_clock_xing_out_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_0_d_bits_data_0 = auto_tl_master_clock_xing_out_0_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_17_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingIn_17_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [3:0] auto_tl_master_clock_xing_out_18_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_17_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingIn_17_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [1:0] auto_tl_master_clock_xing_out_18_b_bits_source = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_17_b_bits_source = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingIn_17_b_bits_source = 2'h0; // @[MixedNode.scala:551:17] wire [7:0] auto_tl_master_clock_xing_out_18_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingOut_17_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingIn_17_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [63:0] auto_tl_master_clock_xing_out_18_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_17_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingIn_17_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire auto_tl_master_clock_xing_out_18_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingIn_17_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire element_reset_domain_auto_rockettile_buffer_out_18_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire x1_tlMasterClockXingOut_17_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingIn_17_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_a_ready = auto_tl_master_clock_xing_out_18_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_17_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_17_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingOut_17_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_17_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_17_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_17_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_b_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_b_valid = auto_tl_master_clock_xing_out_18_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_17_b_bits_param = auto_tl_master_clock_xing_out_18_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingOut_17_b_bits_address = auto_tl_master_clock_xing_out_18_b_bits_address_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_c_ready = auto_tl_master_clock_xing_out_18_c_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_17_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_17_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingOut_17_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_17_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_17_c_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_17_d_valid = auto_tl_master_clock_xing_out_18_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_17_d_bits_opcode = auto_tl_master_clock_xing_out_18_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_17_d_bits_param = auto_tl_master_clock_xing_out_18_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_17_d_bits_size = auto_tl_master_clock_xing_out_18_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_17_d_bits_source = auto_tl_master_clock_xing_out_18_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_17_d_bits_sink = auto_tl_master_clock_xing_out_18_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_d_bits_denied = auto_tl_master_clock_xing_out_18_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_17_d_bits_data = auto_tl_master_clock_xing_out_18_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_d_bits_corrupt = auto_tl_master_clock_xing_out_18_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_17_e_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_17_e_bits_sink; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_16_a_ready = auto_tl_master_clock_xing_out_17_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_16_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_16_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_16_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_16_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_16_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_16_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_16_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_16_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_16_d_valid = auto_tl_master_clock_xing_out_17_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_16_d_bits_opcode = auto_tl_master_clock_xing_out_17_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_16_d_bits_param = auto_tl_master_clock_xing_out_17_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_16_d_bits_size = auto_tl_master_clock_xing_out_17_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_16_d_bits_source = auto_tl_master_clock_xing_out_17_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_16_d_bits_sink = auto_tl_master_clock_xing_out_17_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_16_d_bits_denied = auto_tl_master_clock_xing_out_17_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_16_d_bits_data = auto_tl_master_clock_xing_out_17_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_16_d_bits_corrupt = auto_tl_master_clock_xing_out_17_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_15_a_ready = auto_tl_master_clock_xing_out_16_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_15_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_15_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_15_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_15_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_15_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_15_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_15_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_15_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_15_d_valid = auto_tl_master_clock_xing_out_16_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_15_d_bits_opcode = auto_tl_master_clock_xing_out_16_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_15_d_bits_param = auto_tl_master_clock_xing_out_16_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_15_d_bits_size = auto_tl_master_clock_xing_out_16_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_15_d_bits_source = auto_tl_master_clock_xing_out_16_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_15_d_bits_sink = auto_tl_master_clock_xing_out_16_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_15_d_bits_denied = auto_tl_master_clock_xing_out_16_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_15_d_bits_data = auto_tl_master_clock_xing_out_16_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_15_d_bits_corrupt = auto_tl_master_clock_xing_out_16_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_14_a_ready = auto_tl_master_clock_xing_out_15_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_14_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_14_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_14_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_14_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_14_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_14_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_14_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_14_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_14_d_valid = auto_tl_master_clock_xing_out_15_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_14_d_bits_opcode = auto_tl_master_clock_xing_out_15_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_14_d_bits_param = auto_tl_master_clock_xing_out_15_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_14_d_bits_size = auto_tl_master_clock_xing_out_15_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_14_d_bits_source = auto_tl_master_clock_xing_out_15_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_14_d_bits_sink = auto_tl_master_clock_xing_out_15_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_14_d_bits_denied = auto_tl_master_clock_xing_out_15_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_14_d_bits_data = auto_tl_master_clock_xing_out_15_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_14_d_bits_corrupt = auto_tl_master_clock_xing_out_15_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_13_a_ready = auto_tl_master_clock_xing_out_14_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_13_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_13_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_13_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_13_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_13_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_13_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_13_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_13_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_13_d_valid = auto_tl_master_clock_xing_out_14_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_13_d_bits_opcode = auto_tl_master_clock_xing_out_14_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_13_d_bits_param = auto_tl_master_clock_xing_out_14_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_13_d_bits_size = auto_tl_master_clock_xing_out_14_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_13_d_bits_source = auto_tl_master_clock_xing_out_14_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_13_d_bits_sink = auto_tl_master_clock_xing_out_14_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_13_d_bits_denied = auto_tl_master_clock_xing_out_14_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_13_d_bits_data = auto_tl_master_clock_xing_out_14_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_13_d_bits_corrupt = auto_tl_master_clock_xing_out_14_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_12_a_ready = auto_tl_master_clock_xing_out_13_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_12_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_12_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_12_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_12_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_12_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_12_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_12_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_12_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_12_d_valid = auto_tl_master_clock_xing_out_13_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_12_d_bits_opcode = auto_tl_master_clock_xing_out_13_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_12_d_bits_param = auto_tl_master_clock_xing_out_13_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_12_d_bits_size = auto_tl_master_clock_xing_out_13_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_12_d_bits_source = auto_tl_master_clock_xing_out_13_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_12_d_bits_sink = auto_tl_master_clock_xing_out_13_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_12_d_bits_denied = auto_tl_master_clock_xing_out_13_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_12_d_bits_data = auto_tl_master_clock_xing_out_13_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_12_d_bits_corrupt = auto_tl_master_clock_xing_out_13_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_11_a_ready = auto_tl_master_clock_xing_out_12_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_11_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_11_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_11_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_11_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_11_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_11_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_11_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_11_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_11_d_valid = auto_tl_master_clock_xing_out_12_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_11_d_bits_opcode = auto_tl_master_clock_xing_out_12_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_11_d_bits_param = auto_tl_master_clock_xing_out_12_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_11_d_bits_size = auto_tl_master_clock_xing_out_12_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_11_d_bits_source = auto_tl_master_clock_xing_out_12_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_11_d_bits_sink = auto_tl_master_clock_xing_out_12_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_11_d_bits_denied = auto_tl_master_clock_xing_out_12_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_11_d_bits_data = auto_tl_master_clock_xing_out_12_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_11_d_bits_corrupt = auto_tl_master_clock_xing_out_12_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_10_a_ready = auto_tl_master_clock_xing_out_11_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_10_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_10_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_10_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_10_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_10_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_10_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_10_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_10_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_10_d_valid = auto_tl_master_clock_xing_out_11_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_10_d_bits_opcode = auto_tl_master_clock_xing_out_11_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_10_d_bits_param = auto_tl_master_clock_xing_out_11_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_10_d_bits_size = auto_tl_master_clock_xing_out_11_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_10_d_bits_source = auto_tl_master_clock_xing_out_11_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_10_d_bits_sink = auto_tl_master_clock_xing_out_11_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_10_d_bits_denied = auto_tl_master_clock_xing_out_11_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_10_d_bits_data = auto_tl_master_clock_xing_out_11_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_10_d_bits_corrupt = auto_tl_master_clock_xing_out_11_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_9_a_ready = auto_tl_master_clock_xing_out_10_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_9_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_9_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_9_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_9_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_9_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_9_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_9_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_9_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_9_d_valid = auto_tl_master_clock_xing_out_10_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_9_d_bits_opcode = auto_tl_master_clock_xing_out_10_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_9_d_bits_param = auto_tl_master_clock_xing_out_10_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_9_d_bits_size = auto_tl_master_clock_xing_out_10_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_9_d_bits_source = auto_tl_master_clock_xing_out_10_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_9_d_bits_sink = auto_tl_master_clock_xing_out_10_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_9_d_bits_denied = auto_tl_master_clock_xing_out_10_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_9_d_bits_data = auto_tl_master_clock_xing_out_10_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_9_d_bits_corrupt = auto_tl_master_clock_xing_out_10_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_8_a_ready = auto_tl_master_clock_xing_out_9_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_8_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_8_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_8_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingOut_8_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_8_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_8_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_8_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_8_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_8_d_valid = auto_tl_master_clock_xing_out_9_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_8_d_bits_opcode = auto_tl_master_clock_xing_out_9_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_8_d_bits_param = auto_tl_master_clock_xing_out_9_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_8_d_bits_size = auto_tl_master_clock_xing_out_9_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_8_d_bits_source = auto_tl_master_clock_xing_out_9_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_8_d_bits_sink = auto_tl_master_clock_xing_out_9_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_8_d_bits_denied = auto_tl_master_clock_xing_out_9_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_8_d_bits_data = auto_tl_master_clock_xing_out_9_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_8_d_bits_corrupt = auto_tl_master_clock_xing_out_9_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_7_a_ready = auto_tl_master_clock_xing_out_8_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_7_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_7_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_7_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingOut_7_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_7_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_7_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_7_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_7_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_7_d_valid = auto_tl_master_clock_xing_out_8_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_7_d_bits_opcode = auto_tl_master_clock_xing_out_8_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_7_d_bits_param = auto_tl_master_clock_xing_out_8_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_7_d_bits_size = auto_tl_master_clock_xing_out_8_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_7_d_bits_source = auto_tl_master_clock_xing_out_8_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_7_d_bits_sink = auto_tl_master_clock_xing_out_8_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_7_d_bits_denied = auto_tl_master_clock_xing_out_8_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_7_d_bits_data = auto_tl_master_clock_xing_out_8_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_7_d_bits_corrupt = auto_tl_master_clock_xing_out_8_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_6_a_ready = auto_tl_master_clock_xing_out_7_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_6_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_6_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_6_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_6_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_6_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_6_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_6_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_6_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_6_d_valid = auto_tl_master_clock_xing_out_7_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_6_d_bits_opcode = auto_tl_master_clock_xing_out_7_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_6_d_bits_param = auto_tl_master_clock_xing_out_7_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_6_d_bits_size = auto_tl_master_clock_xing_out_7_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_6_d_bits_source = auto_tl_master_clock_xing_out_7_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_6_d_bits_sink = auto_tl_master_clock_xing_out_7_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_6_d_bits_denied = auto_tl_master_clock_xing_out_7_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_6_d_bits_data = auto_tl_master_clock_xing_out_7_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_6_d_bits_corrupt = auto_tl_master_clock_xing_out_7_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_5_a_ready = auto_tl_master_clock_xing_out_6_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_5_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_5_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_5_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_5_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_5_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_5_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_5_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_5_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_5_d_valid = auto_tl_master_clock_xing_out_6_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_5_d_bits_opcode = auto_tl_master_clock_xing_out_6_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_5_d_bits_param = auto_tl_master_clock_xing_out_6_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_5_d_bits_size = auto_tl_master_clock_xing_out_6_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_5_d_bits_source = auto_tl_master_clock_xing_out_6_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_5_d_bits_sink = auto_tl_master_clock_xing_out_6_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_5_d_bits_denied = auto_tl_master_clock_xing_out_6_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_5_d_bits_data = auto_tl_master_clock_xing_out_6_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_5_d_bits_corrupt = auto_tl_master_clock_xing_out_6_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_4_a_ready = auto_tl_master_clock_xing_out_5_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_4_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_4_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_4_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_4_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_4_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_4_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_4_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_4_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_4_d_valid = auto_tl_master_clock_xing_out_5_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_4_d_bits_opcode = auto_tl_master_clock_xing_out_5_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_4_d_bits_param = auto_tl_master_clock_xing_out_5_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_4_d_bits_size = auto_tl_master_clock_xing_out_5_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_4_d_bits_source = auto_tl_master_clock_xing_out_5_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_4_d_bits_sink = auto_tl_master_clock_xing_out_5_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_4_d_bits_denied = auto_tl_master_clock_xing_out_5_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_4_d_bits_data = auto_tl_master_clock_xing_out_5_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_4_d_bits_corrupt = auto_tl_master_clock_xing_out_5_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_3_a_ready = auto_tl_master_clock_xing_out_4_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_3_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_3_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_3_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_3_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_3_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_3_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_3_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_3_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_3_d_valid = auto_tl_master_clock_xing_out_4_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_3_d_bits_opcode = auto_tl_master_clock_xing_out_4_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_3_d_bits_param = auto_tl_master_clock_xing_out_4_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_3_d_bits_size = auto_tl_master_clock_xing_out_4_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_3_d_bits_source = auto_tl_master_clock_xing_out_4_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_3_d_bits_sink = auto_tl_master_clock_xing_out_4_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_3_d_bits_denied = auto_tl_master_clock_xing_out_4_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_3_d_bits_data = auto_tl_master_clock_xing_out_4_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_3_d_bits_corrupt = auto_tl_master_clock_xing_out_4_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_2_a_ready = auto_tl_master_clock_xing_out_3_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_2_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_2_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_2_d_valid = auto_tl_master_clock_xing_out_3_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_2_d_bits_opcode = auto_tl_master_clock_xing_out_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_2_d_bits_param = auto_tl_master_clock_xing_out_3_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_2_d_bits_size = auto_tl_master_clock_xing_out_3_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_2_d_bits_source = auto_tl_master_clock_xing_out_3_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_2_d_bits_sink = auto_tl_master_clock_xing_out_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_2_d_bits_denied = auto_tl_master_clock_xing_out_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_2_d_bits_data = auto_tl_master_clock_xing_out_3_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_2_d_bits_corrupt = auto_tl_master_clock_xing_out_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_1_a_ready = auto_tl_master_clock_xing_out_2_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_tlMasterClockXingOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_1_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_1_d_valid = auto_tl_master_clock_xing_out_2_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_1_d_bits_opcode = auto_tl_master_clock_xing_out_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_1_d_bits_param = auto_tl_master_clock_xing_out_2_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_1_d_bits_size = auto_tl_master_clock_xing_out_2_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingOut_1_d_bits_source = auto_tl_master_clock_xing_out_2_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_1_d_bits_sink = auto_tl_master_clock_xing_out_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_1_d_bits_denied = auto_tl_master_clock_xing_out_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_1_d_bits_data = auto_tl_master_clock_xing_out_2_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_1_d_bits_corrupt = auto_tl_master_clock_xing_out_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_1_a_ready_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire x1_tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_1_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_1_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_1_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_1_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_1_d_bits_data_0; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_0_a_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_0_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_0_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_0_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_0_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_0_d_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_18_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_18_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_18_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_18_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_18_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_18_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_18_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_18_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_18_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_18_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_18_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_17_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_17_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_17_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_17_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_17_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_17_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_17_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_17_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_16_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_16_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_16_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_16_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_16_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_16_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_16_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_16_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_15_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_15_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_15_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_15_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_15_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_15_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_15_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_15_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_14_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_14_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_14_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_14_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_14_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_14_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_14_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_14_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_13_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_13_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_13_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_13_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_13_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_13_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_13_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_13_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_12_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_12_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_12_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_12_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_12_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_12_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_12_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_12_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_11_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_11_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_11_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_11_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_11_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_11_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_11_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_11_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_10_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_10_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_10_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_10_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_10_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_10_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_10_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_10_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_9_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_9_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_9_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_9_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_9_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_9_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_9_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_9_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_8_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_8_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_8_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_8_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_8_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_8_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_8_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_8_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_7_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_7_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_7_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_7_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_7_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_7_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_7_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_7_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_6_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_6_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_6_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_6_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_6_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_6_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_6_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_6_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_5_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_5_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_5_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_5_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_5_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_5_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_5_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_5_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_4_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_4_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_4_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_4_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_4_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_4_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_4_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_4_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_3_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_3_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_3_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_3_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_3_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_3_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_2_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_2_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_tl_master_clock_xing_out_2_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_2_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_2_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_2_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_1_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_0_d_ready_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_18_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_18_b_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_b_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_18_c_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_c_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_18_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_18_e_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_e_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_18_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_17_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_17_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_17_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_16_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_16_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_16_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_15_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_15_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_15_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_14_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_14_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_14_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_13_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_13_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_13_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_12_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_12_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_12_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_11_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_11_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_11_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_10_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_10_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_10_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_9_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_9_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_9_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_8_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_8_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_8_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_7_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_7_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_7_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_6_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_6_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_6_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_5_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_5_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_5_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_4_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_4_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_4_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_3_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_3_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_3_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_2_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_2_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_2_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_1_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_buffer_out_0_d_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31] wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31] assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17] wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9] assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17] assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17] assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17] assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_0_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_a_ready = x1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_valid_0 = x1_tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_opcode_0 = x1_tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_param_0 = x1_tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_size_0 = x1_tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_source_0 = x1_tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_address_0 = x1_tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_mask_0 = x1_tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_data_0 = x1_tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_a_bits_corrupt_0 = x1_tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_1_d_ready_0 = x1_tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_d_valid = x1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_d_bits_opcode = x1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_d_bits_param = x1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_d_bits_size = x1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_d_bits_source = x1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_d_bits_sink = x1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_d_bits_denied = x1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_d_bits_data = x1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_d_bits_corrupt = x1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_1_a_ready = x1_tlMasterClockXingOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_1_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_valid_0 = x1_tlMasterClockXingOut_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_1_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_opcode_0 = x1_tlMasterClockXingOut_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_1_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_param_0 = x1_tlMasterClockXingOut_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_1_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_size_0 = x1_tlMasterClockXingOut_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_1_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_source_0 = x1_tlMasterClockXingOut_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_1_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_address_0 = x1_tlMasterClockXingOut_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_1_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_mask_0 = x1_tlMasterClockXingOut_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_1_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_data_0 = x1_tlMasterClockXingOut_1_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_1_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_a_bits_corrupt_0 = x1_tlMasterClockXingOut_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_1_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_2_d_ready_0 = x1_tlMasterClockXingOut_1_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_1_d_valid = x1_tlMasterClockXingOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_1_d_bits_opcode = x1_tlMasterClockXingOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_1_d_bits_param = x1_tlMasterClockXingOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_1_d_bits_size = x1_tlMasterClockXingOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_1_d_bits_source = x1_tlMasterClockXingOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_1_d_bits_sink = x1_tlMasterClockXingOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_1_d_bits_denied = x1_tlMasterClockXingOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_1_d_bits_data = x1_tlMasterClockXingOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_1_d_bits_corrupt = x1_tlMasterClockXingOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_2_a_ready = x1_tlMasterClockXingOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_2_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_valid_0 = x1_tlMasterClockXingOut_2_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_2_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_opcode_0 = x1_tlMasterClockXingOut_2_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_2_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_param_0 = x1_tlMasterClockXingOut_2_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_2_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_size_0 = x1_tlMasterClockXingOut_2_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_2_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_source_0 = x1_tlMasterClockXingOut_2_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_2_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_address_0 = x1_tlMasterClockXingOut_2_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_2_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_mask_0 = x1_tlMasterClockXingOut_2_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_2_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_data_0 = x1_tlMasterClockXingOut_2_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_2_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_a_bits_corrupt_0 = x1_tlMasterClockXingOut_2_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_2_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_3_d_ready_0 = x1_tlMasterClockXingOut_2_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_2_d_valid = x1_tlMasterClockXingOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_2_d_bits_opcode = x1_tlMasterClockXingOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_2_d_bits_param = x1_tlMasterClockXingOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_2_d_bits_size = x1_tlMasterClockXingOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_2_d_bits_source = x1_tlMasterClockXingOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_2_d_bits_sink = x1_tlMasterClockXingOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_2_d_bits_denied = x1_tlMasterClockXingOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_2_d_bits_data = x1_tlMasterClockXingOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_2_d_bits_corrupt = x1_tlMasterClockXingOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_3_a_ready = x1_tlMasterClockXingOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_3_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_valid_0 = x1_tlMasterClockXingOut_3_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_3_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_opcode_0 = x1_tlMasterClockXingOut_3_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_3_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_param_0 = x1_tlMasterClockXingOut_3_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_3_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_size_0 = x1_tlMasterClockXingOut_3_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_3_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_source_0 = x1_tlMasterClockXingOut_3_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_3_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_address_0 = x1_tlMasterClockXingOut_3_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_3_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_mask_0 = x1_tlMasterClockXingOut_3_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_3_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_data_0 = x1_tlMasterClockXingOut_3_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_3_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_a_bits_corrupt_0 = x1_tlMasterClockXingOut_3_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_3_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_4_d_ready_0 = x1_tlMasterClockXingOut_3_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_3_d_valid = x1_tlMasterClockXingOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_3_d_bits_opcode = x1_tlMasterClockXingOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_3_d_bits_param = x1_tlMasterClockXingOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_3_d_bits_size = x1_tlMasterClockXingOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_3_d_bits_source = x1_tlMasterClockXingOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_3_d_bits_sink = x1_tlMasterClockXingOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_3_d_bits_denied = x1_tlMasterClockXingOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_3_d_bits_data = x1_tlMasterClockXingOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_3_d_bits_corrupt = x1_tlMasterClockXingOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_4_a_ready = x1_tlMasterClockXingOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_4_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_valid_0 = x1_tlMasterClockXingOut_4_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_4_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_opcode_0 = x1_tlMasterClockXingOut_4_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_4_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_param_0 = x1_tlMasterClockXingOut_4_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_4_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_size_0 = x1_tlMasterClockXingOut_4_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_4_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_source_0 = x1_tlMasterClockXingOut_4_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_4_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_address_0 = x1_tlMasterClockXingOut_4_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_4_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_mask_0 = x1_tlMasterClockXingOut_4_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_4_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_data_0 = x1_tlMasterClockXingOut_4_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_4_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_a_bits_corrupt_0 = x1_tlMasterClockXingOut_4_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_4_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_5_d_ready_0 = x1_tlMasterClockXingOut_4_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_4_d_valid = x1_tlMasterClockXingOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_4_d_bits_opcode = x1_tlMasterClockXingOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_4_d_bits_param = x1_tlMasterClockXingOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_4_d_bits_size = x1_tlMasterClockXingOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_4_d_bits_source = x1_tlMasterClockXingOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_4_d_bits_sink = x1_tlMasterClockXingOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_4_d_bits_denied = x1_tlMasterClockXingOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_4_d_bits_data = x1_tlMasterClockXingOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_4_d_bits_corrupt = x1_tlMasterClockXingOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_5_a_ready = x1_tlMasterClockXingOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_5_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_valid_0 = x1_tlMasterClockXingOut_5_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_5_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_opcode_0 = x1_tlMasterClockXingOut_5_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_5_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_param_0 = x1_tlMasterClockXingOut_5_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_5_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_size_0 = x1_tlMasterClockXingOut_5_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_5_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_source_0 = x1_tlMasterClockXingOut_5_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_5_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_address_0 = x1_tlMasterClockXingOut_5_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_5_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_mask_0 = x1_tlMasterClockXingOut_5_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_5_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_data_0 = x1_tlMasterClockXingOut_5_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_5_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_a_bits_corrupt_0 = x1_tlMasterClockXingOut_5_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_5_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_6_d_ready_0 = x1_tlMasterClockXingOut_5_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_5_d_valid = x1_tlMasterClockXingOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_5_d_bits_opcode = x1_tlMasterClockXingOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_5_d_bits_param = x1_tlMasterClockXingOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_5_d_bits_size = x1_tlMasterClockXingOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_5_d_bits_source = x1_tlMasterClockXingOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_5_d_bits_sink = x1_tlMasterClockXingOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_5_d_bits_denied = x1_tlMasterClockXingOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_5_d_bits_data = x1_tlMasterClockXingOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_5_d_bits_corrupt = x1_tlMasterClockXingOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_6_a_ready = x1_tlMasterClockXingOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_6_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_valid_0 = x1_tlMasterClockXingOut_6_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_6_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_opcode_0 = x1_tlMasterClockXingOut_6_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_6_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_param_0 = x1_tlMasterClockXingOut_6_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_6_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_size_0 = x1_tlMasterClockXingOut_6_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_6_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_source_0 = x1_tlMasterClockXingOut_6_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_6_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_address_0 = x1_tlMasterClockXingOut_6_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_6_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_mask_0 = x1_tlMasterClockXingOut_6_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_6_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_data_0 = x1_tlMasterClockXingOut_6_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_6_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_a_bits_corrupt_0 = x1_tlMasterClockXingOut_6_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_6_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_7_d_ready_0 = x1_tlMasterClockXingOut_6_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_6_d_valid = x1_tlMasterClockXingOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_6_d_bits_opcode = x1_tlMasterClockXingOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_6_d_bits_param = x1_tlMasterClockXingOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_6_d_bits_size = x1_tlMasterClockXingOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_6_d_bits_source = x1_tlMasterClockXingOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_6_d_bits_sink = x1_tlMasterClockXingOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_6_d_bits_denied = x1_tlMasterClockXingOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_6_d_bits_data = x1_tlMasterClockXingOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_6_d_bits_corrupt = x1_tlMasterClockXingOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_7_a_ready = x1_tlMasterClockXingOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_7_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_valid_0 = x1_tlMasterClockXingOut_7_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_7_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_opcode_0 = x1_tlMasterClockXingOut_7_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_7_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_param_0 = x1_tlMasterClockXingOut_7_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_7_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_size_0 = x1_tlMasterClockXingOut_7_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingIn_7_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_source_0 = x1_tlMasterClockXingOut_7_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_7_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_address_0 = x1_tlMasterClockXingOut_7_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_7_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_mask_0 = x1_tlMasterClockXingOut_7_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_7_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_data_0 = x1_tlMasterClockXingOut_7_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_7_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_a_bits_corrupt_0 = x1_tlMasterClockXingOut_7_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_7_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_8_d_ready_0 = x1_tlMasterClockXingOut_7_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_7_d_valid = x1_tlMasterClockXingOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_7_d_bits_opcode = x1_tlMasterClockXingOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_7_d_bits_param = x1_tlMasterClockXingOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_7_d_bits_size = x1_tlMasterClockXingOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_7_d_bits_source = x1_tlMasterClockXingOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_7_d_bits_sink = x1_tlMasterClockXingOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_7_d_bits_denied = x1_tlMasterClockXingOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_7_d_bits_data = x1_tlMasterClockXingOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_7_d_bits_corrupt = x1_tlMasterClockXingOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_8_a_ready = x1_tlMasterClockXingOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_8_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_valid_0 = x1_tlMasterClockXingOut_8_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_8_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_opcode_0 = x1_tlMasterClockXingOut_8_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_8_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_param_0 = x1_tlMasterClockXingOut_8_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_8_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_size_0 = x1_tlMasterClockXingOut_8_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingIn_8_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_source_0 = x1_tlMasterClockXingOut_8_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_8_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_address_0 = x1_tlMasterClockXingOut_8_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_8_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_mask_0 = x1_tlMasterClockXingOut_8_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_8_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_data_0 = x1_tlMasterClockXingOut_8_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_8_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_a_bits_corrupt_0 = x1_tlMasterClockXingOut_8_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_8_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_9_d_ready_0 = x1_tlMasterClockXingOut_8_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_8_d_valid = x1_tlMasterClockXingOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_8_d_bits_opcode = x1_tlMasterClockXingOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_8_d_bits_param = x1_tlMasterClockXingOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_8_d_bits_size = x1_tlMasterClockXingOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_8_d_bits_source = x1_tlMasterClockXingOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_8_d_bits_sink = x1_tlMasterClockXingOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_8_d_bits_denied = x1_tlMasterClockXingOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_8_d_bits_data = x1_tlMasterClockXingOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_8_d_bits_corrupt = x1_tlMasterClockXingOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_9_a_ready = x1_tlMasterClockXingOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_9_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_valid_0 = x1_tlMasterClockXingOut_9_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_9_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_opcode_0 = x1_tlMasterClockXingOut_9_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_9_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_param_0 = x1_tlMasterClockXingOut_9_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_9_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_size_0 = x1_tlMasterClockXingOut_9_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_9_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_source_0 = x1_tlMasterClockXingOut_9_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_9_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_address_0 = x1_tlMasterClockXingOut_9_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_9_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_mask_0 = x1_tlMasterClockXingOut_9_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_9_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_data_0 = x1_tlMasterClockXingOut_9_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_9_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_a_bits_corrupt_0 = x1_tlMasterClockXingOut_9_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_9_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_10_d_ready_0 = x1_tlMasterClockXingOut_9_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_9_d_valid = x1_tlMasterClockXingOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_9_d_bits_opcode = x1_tlMasterClockXingOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_9_d_bits_param = x1_tlMasterClockXingOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_9_d_bits_size = x1_tlMasterClockXingOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_9_d_bits_source = x1_tlMasterClockXingOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_9_d_bits_sink = x1_tlMasterClockXingOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_9_d_bits_denied = x1_tlMasterClockXingOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_9_d_bits_data = x1_tlMasterClockXingOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_9_d_bits_corrupt = x1_tlMasterClockXingOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_10_a_ready = x1_tlMasterClockXingOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_10_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_valid_0 = x1_tlMasterClockXingOut_10_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_10_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_opcode_0 = x1_tlMasterClockXingOut_10_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_10_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_param_0 = x1_tlMasterClockXingOut_10_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_10_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_size_0 = x1_tlMasterClockXingOut_10_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_10_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_source_0 = x1_tlMasterClockXingOut_10_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_10_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_address_0 = x1_tlMasterClockXingOut_10_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_10_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_mask_0 = x1_tlMasterClockXingOut_10_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_10_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_data_0 = x1_tlMasterClockXingOut_10_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_10_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_a_bits_corrupt_0 = x1_tlMasterClockXingOut_10_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_10_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_11_d_ready_0 = x1_tlMasterClockXingOut_10_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_10_d_valid = x1_tlMasterClockXingOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_10_d_bits_opcode = x1_tlMasterClockXingOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_10_d_bits_param = x1_tlMasterClockXingOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_10_d_bits_size = x1_tlMasterClockXingOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_10_d_bits_source = x1_tlMasterClockXingOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_10_d_bits_sink = x1_tlMasterClockXingOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_10_d_bits_denied = x1_tlMasterClockXingOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_10_d_bits_data = x1_tlMasterClockXingOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_10_d_bits_corrupt = x1_tlMasterClockXingOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_11_a_ready = x1_tlMasterClockXingOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_11_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_valid_0 = x1_tlMasterClockXingOut_11_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_11_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_opcode_0 = x1_tlMasterClockXingOut_11_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_11_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_param_0 = x1_tlMasterClockXingOut_11_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_11_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_size_0 = x1_tlMasterClockXingOut_11_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_11_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_source_0 = x1_tlMasterClockXingOut_11_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_11_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_address_0 = x1_tlMasterClockXingOut_11_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_11_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_mask_0 = x1_tlMasterClockXingOut_11_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_11_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_data_0 = x1_tlMasterClockXingOut_11_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_11_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_a_bits_corrupt_0 = x1_tlMasterClockXingOut_11_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_11_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_12_d_ready_0 = x1_tlMasterClockXingOut_11_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_11_d_valid = x1_tlMasterClockXingOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_11_d_bits_opcode = x1_tlMasterClockXingOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_11_d_bits_param = x1_tlMasterClockXingOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_11_d_bits_size = x1_tlMasterClockXingOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_11_d_bits_source = x1_tlMasterClockXingOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_11_d_bits_sink = x1_tlMasterClockXingOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_11_d_bits_denied = x1_tlMasterClockXingOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_11_d_bits_data = x1_tlMasterClockXingOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_11_d_bits_corrupt = x1_tlMasterClockXingOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_12_a_ready = x1_tlMasterClockXingOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_12_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_valid_0 = x1_tlMasterClockXingOut_12_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_12_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_opcode_0 = x1_tlMasterClockXingOut_12_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_12_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_param_0 = x1_tlMasterClockXingOut_12_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_12_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_size_0 = x1_tlMasterClockXingOut_12_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_12_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_source_0 = x1_tlMasterClockXingOut_12_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_12_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_address_0 = x1_tlMasterClockXingOut_12_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_12_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_mask_0 = x1_tlMasterClockXingOut_12_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_12_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_data_0 = x1_tlMasterClockXingOut_12_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_12_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_a_bits_corrupt_0 = x1_tlMasterClockXingOut_12_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_12_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_13_d_ready_0 = x1_tlMasterClockXingOut_12_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_12_d_valid = x1_tlMasterClockXingOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_12_d_bits_opcode = x1_tlMasterClockXingOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_12_d_bits_param = x1_tlMasterClockXingOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_12_d_bits_size = x1_tlMasterClockXingOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_12_d_bits_source = x1_tlMasterClockXingOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_12_d_bits_sink = x1_tlMasterClockXingOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_12_d_bits_denied = x1_tlMasterClockXingOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_12_d_bits_data = x1_tlMasterClockXingOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_12_d_bits_corrupt = x1_tlMasterClockXingOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_13_a_ready = x1_tlMasterClockXingOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_13_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_valid_0 = x1_tlMasterClockXingOut_13_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_13_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_opcode_0 = x1_tlMasterClockXingOut_13_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_13_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_param_0 = x1_tlMasterClockXingOut_13_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_13_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_size_0 = x1_tlMasterClockXingOut_13_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_13_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_source_0 = x1_tlMasterClockXingOut_13_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_13_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_address_0 = x1_tlMasterClockXingOut_13_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_13_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_mask_0 = x1_tlMasterClockXingOut_13_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_13_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_data_0 = x1_tlMasterClockXingOut_13_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_13_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_a_bits_corrupt_0 = x1_tlMasterClockXingOut_13_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_13_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_14_d_ready_0 = x1_tlMasterClockXingOut_13_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_13_d_valid = x1_tlMasterClockXingOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_13_d_bits_opcode = x1_tlMasterClockXingOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_13_d_bits_param = x1_tlMasterClockXingOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_13_d_bits_size = x1_tlMasterClockXingOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_13_d_bits_source = x1_tlMasterClockXingOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_13_d_bits_sink = x1_tlMasterClockXingOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_13_d_bits_denied = x1_tlMasterClockXingOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_13_d_bits_data = x1_tlMasterClockXingOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_13_d_bits_corrupt = x1_tlMasterClockXingOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_14_a_ready = x1_tlMasterClockXingOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_14_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_valid_0 = x1_tlMasterClockXingOut_14_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_14_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_opcode_0 = x1_tlMasterClockXingOut_14_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_14_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_param_0 = x1_tlMasterClockXingOut_14_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_14_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_size_0 = x1_tlMasterClockXingOut_14_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_14_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_source_0 = x1_tlMasterClockXingOut_14_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_14_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_address_0 = x1_tlMasterClockXingOut_14_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_14_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_mask_0 = x1_tlMasterClockXingOut_14_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_14_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_data_0 = x1_tlMasterClockXingOut_14_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_14_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_a_bits_corrupt_0 = x1_tlMasterClockXingOut_14_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_14_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_15_d_ready_0 = x1_tlMasterClockXingOut_14_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_14_d_valid = x1_tlMasterClockXingOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_14_d_bits_opcode = x1_tlMasterClockXingOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_14_d_bits_param = x1_tlMasterClockXingOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_14_d_bits_size = x1_tlMasterClockXingOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_14_d_bits_source = x1_tlMasterClockXingOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_14_d_bits_sink = x1_tlMasterClockXingOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_14_d_bits_denied = x1_tlMasterClockXingOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_14_d_bits_data = x1_tlMasterClockXingOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_14_d_bits_corrupt = x1_tlMasterClockXingOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_15_a_ready = x1_tlMasterClockXingOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_15_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_valid_0 = x1_tlMasterClockXingOut_15_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_15_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_opcode_0 = x1_tlMasterClockXingOut_15_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_15_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_param_0 = x1_tlMasterClockXingOut_15_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_15_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_size_0 = x1_tlMasterClockXingOut_15_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_15_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_source_0 = x1_tlMasterClockXingOut_15_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_15_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_address_0 = x1_tlMasterClockXingOut_15_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_15_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_mask_0 = x1_tlMasterClockXingOut_15_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_15_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_data_0 = x1_tlMasterClockXingOut_15_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_15_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_a_bits_corrupt_0 = x1_tlMasterClockXingOut_15_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_15_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_16_d_ready_0 = x1_tlMasterClockXingOut_15_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_15_d_valid = x1_tlMasterClockXingOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_15_d_bits_opcode = x1_tlMasterClockXingOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_15_d_bits_param = x1_tlMasterClockXingOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_15_d_bits_size = x1_tlMasterClockXingOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_15_d_bits_source = x1_tlMasterClockXingOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_15_d_bits_sink = x1_tlMasterClockXingOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_15_d_bits_denied = x1_tlMasterClockXingOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_15_d_bits_data = x1_tlMasterClockXingOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_15_d_bits_corrupt = x1_tlMasterClockXingOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_16_a_ready = x1_tlMasterClockXingOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_16_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_valid_0 = x1_tlMasterClockXingOut_16_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_16_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_opcode_0 = x1_tlMasterClockXingOut_16_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_16_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_param_0 = x1_tlMasterClockXingOut_16_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_16_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_size_0 = x1_tlMasterClockXingOut_16_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] x1_tlMasterClockXingIn_16_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_source_0 = x1_tlMasterClockXingOut_16_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_16_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_address_0 = x1_tlMasterClockXingOut_16_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_16_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_mask_0 = x1_tlMasterClockXingOut_16_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_16_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_data_0 = x1_tlMasterClockXingOut_16_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_16_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_a_bits_corrupt_0 = x1_tlMasterClockXingOut_16_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_16_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_17_d_ready_0 = x1_tlMasterClockXingOut_16_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_16_d_valid = x1_tlMasterClockXingOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_16_d_bits_opcode = x1_tlMasterClockXingOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_16_d_bits_param = x1_tlMasterClockXingOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_16_d_bits_size = x1_tlMasterClockXingOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlMasterClockXingIn_16_d_bits_source = x1_tlMasterClockXingOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_16_d_bits_sink = x1_tlMasterClockXingOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_16_d_bits_denied = x1_tlMasterClockXingOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_16_d_bits_data = x1_tlMasterClockXingOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_16_d_bits_corrupt = x1_tlMasterClockXingOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_a_ready = x1_tlMasterClockXingOut_17_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_valid_0 = x1_tlMasterClockXingOut_17_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_17_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_opcode_0 = x1_tlMasterClockXingOut_17_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_17_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_param_0 = x1_tlMasterClockXingOut_17_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_17_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_size_0 = x1_tlMasterClockXingOut_17_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingIn_17_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_source_0 = x1_tlMasterClockXingOut_17_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_17_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_address_0 = x1_tlMasterClockXingOut_17_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] x1_tlMasterClockXingIn_17_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_mask_0 = x1_tlMasterClockXingOut_17_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_17_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_data_0 = x1_tlMasterClockXingOut_17_a_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_a_bits_corrupt_0 = x1_tlMasterClockXingOut_17_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_b_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_b_ready_0 = x1_tlMasterClockXingOut_17_b_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_b_valid = x1_tlMasterClockXingOut_17_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_17_b_bits_param = x1_tlMasterClockXingOut_17_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [31:0] x1_tlMasterClockXingIn_17_b_bits_address = x1_tlMasterClockXingOut_17_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_c_ready = x1_tlMasterClockXingOut_17_c_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_c_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_valid_0 = x1_tlMasterClockXingOut_17_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_17_c_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_opcode_0 = x1_tlMasterClockXingOut_17_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_17_c_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_param_0 = x1_tlMasterClockXingOut_17_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] x1_tlMasterClockXingIn_17_c_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_size_0 = x1_tlMasterClockXingOut_17_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] x1_tlMasterClockXingIn_17_c_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_source_0 = x1_tlMasterClockXingOut_17_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] x1_tlMasterClockXingIn_17_c_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_address_0 = x1_tlMasterClockXingOut_17_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] x1_tlMasterClockXingIn_17_c_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_data_0 = x1_tlMasterClockXingOut_17_c_bits_data; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_c_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_c_bits_corrupt_0 = x1_tlMasterClockXingOut_17_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_d_ready_0 = x1_tlMasterClockXingOut_17_d_ready; // @[ClockDomain.scala:14:9] wire x1_tlMasterClockXingIn_17_d_valid = x1_tlMasterClockXingOut_17_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_17_d_bits_opcode = x1_tlMasterClockXingOut_17_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_17_d_bits_param = x1_tlMasterClockXingOut_17_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlMasterClockXingIn_17_d_bits_size = x1_tlMasterClockXingOut_17_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlMasterClockXingIn_17_d_bits_source = x1_tlMasterClockXingOut_17_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlMasterClockXingIn_17_d_bits_sink = x1_tlMasterClockXingOut_17_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_d_bits_denied = x1_tlMasterClockXingOut_17_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlMasterClockXingIn_17_d_bits_data = x1_tlMasterClockXingOut_17_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_d_bits_corrupt = x1_tlMasterClockXingOut_17_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlMasterClockXingIn_17_e_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_e_valid_0 = x1_tlMasterClockXingOut_17_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] x1_tlMasterClockXingIn_17_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_18_e_bits_sink_0 = x1_tlMasterClockXingOut_17_e_bits_sink; // @[ClockDomain.scala:14:9] assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_valid = x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_opcode = x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_param = x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_size = x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_source = x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_address = x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_mask = x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_data = x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_a_bits_corrupt = x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_d_ready = x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_valid = x1_tlMasterClockXingIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_opcode = x1_tlMasterClockXingIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_param = x1_tlMasterClockXingIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_size = x1_tlMasterClockXingIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_source = x1_tlMasterClockXingIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_address = x1_tlMasterClockXingIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_mask = x1_tlMasterClockXingIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_data = x1_tlMasterClockXingIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_a_bits_corrupt = x1_tlMasterClockXingIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_1_d_ready = x1_tlMasterClockXingIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_valid = x1_tlMasterClockXingIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_opcode = x1_tlMasterClockXingIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_param = x1_tlMasterClockXingIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_size = x1_tlMasterClockXingIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_source = x1_tlMasterClockXingIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_address = x1_tlMasterClockXingIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_mask = x1_tlMasterClockXingIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_data = x1_tlMasterClockXingIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_a_bits_corrupt = x1_tlMasterClockXingIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_2_d_ready = x1_tlMasterClockXingIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_valid = x1_tlMasterClockXingIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_opcode = x1_tlMasterClockXingIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_param = x1_tlMasterClockXingIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_size = x1_tlMasterClockXingIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_source = x1_tlMasterClockXingIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_address = x1_tlMasterClockXingIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_mask = x1_tlMasterClockXingIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_data = x1_tlMasterClockXingIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_a_bits_corrupt = x1_tlMasterClockXingIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_3_d_ready = x1_tlMasterClockXingIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_valid = x1_tlMasterClockXingIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_opcode = x1_tlMasterClockXingIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_param = x1_tlMasterClockXingIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_size = x1_tlMasterClockXingIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_source = x1_tlMasterClockXingIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_address = x1_tlMasterClockXingIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_mask = x1_tlMasterClockXingIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_data = x1_tlMasterClockXingIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_a_bits_corrupt = x1_tlMasterClockXingIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_4_d_ready = x1_tlMasterClockXingIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_valid = x1_tlMasterClockXingIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_opcode = x1_tlMasterClockXingIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_param = x1_tlMasterClockXingIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_size = x1_tlMasterClockXingIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_source = x1_tlMasterClockXingIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_address = x1_tlMasterClockXingIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_mask = x1_tlMasterClockXingIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_data = x1_tlMasterClockXingIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_a_bits_corrupt = x1_tlMasterClockXingIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_5_d_ready = x1_tlMasterClockXingIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_valid = x1_tlMasterClockXingIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_opcode = x1_tlMasterClockXingIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_param = x1_tlMasterClockXingIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_size = x1_tlMasterClockXingIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_source = x1_tlMasterClockXingIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_address = x1_tlMasterClockXingIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_mask = x1_tlMasterClockXingIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_data = x1_tlMasterClockXingIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_a_bits_corrupt = x1_tlMasterClockXingIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_6_d_ready = x1_tlMasterClockXingIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_valid = x1_tlMasterClockXingIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_opcode = x1_tlMasterClockXingIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_param = x1_tlMasterClockXingIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_size = x1_tlMasterClockXingIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_source = x1_tlMasterClockXingIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_address = x1_tlMasterClockXingIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_mask = x1_tlMasterClockXingIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_data = x1_tlMasterClockXingIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_a_bits_corrupt = x1_tlMasterClockXingIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_7_d_ready = x1_tlMasterClockXingIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_valid = x1_tlMasterClockXingIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_opcode = x1_tlMasterClockXingIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_param = x1_tlMasterClockXingIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_size = x1_tlMasterClockXingIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_source = x1_tlMasterClockXingIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_address = x1_tlMasterClockXingIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_mask = x1_tlMasterClockXingIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_data = x1_tlMasterClockXingIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_a_bits_corrupt = x1_tlMasterClockXingIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_8_d_ready = x1_tlMasterClockXingIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_valid = x1_tlMasterClockXingIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_opcode = x1_tlMasterClockXingIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_param = x1_tlMasterClockXingIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_size = x1_tlMasterClockXingIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_source = x1_tlMasterClockXingIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_address = x1_tlMasterClockXingIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_mask = x1_tlMasterClockXingIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_data = x1_tlMasterClockXingIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_a_bits_corrupt = x1_tlMasterClockXingIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_9_d_ready = x1_tlMasterClockXingIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_valid = x1_tlMasterClockXingIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_opcode = x1_tlMasterClockXingIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_param = x1_tlMasterClockXingIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_size = x1_tlMasterClockXingIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_source = x1_tlMasterClockXingIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_address = x1_tlMasterClockXingIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_mask = x1_tlMasterClockXingIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_data = x1_tlMasterClockXingIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_a_bits_corrupt = x1_tlMasterClockXingIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_10_d_ready = x1_tlMasterClockXingIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_valid = x1_tlMasterClockXingIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_opcode = x1_tlMasterClockXingIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_param = x1_tlMasterClockXingIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_size = x1_tlMasterClockXingIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_source = x1_tlMasterClockXingIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_address = x1_tlMasterClockXingIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_mask = x1_tlMasterClockXingIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_data = x1_tlMasterClockXingIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_a_bits_corrupt = x1_tlMasterClockXingIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_11_d_ready = x1_tlMasterClockXingIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_valid = x1_tlMasterClockXingIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_opcode = x1_tlMasterClockXingIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_param = x1_tlMasterClockXingIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_size = x1_tlMasterClockXingIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_source = x1_tlMasterClockXingIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_address = x1_tlMasterClockXingIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_mask = x1_tlMasterClockXingIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_data = x1_tlMasterClockXingIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_a_bits_corrupt = x1_tlMasterClockXingIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_12_d_ready = x1_tlMasterClockXingIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_valid = x1_tlMasterClockXingIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_opcode = x1_tlMasterClockXingIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_param = x1_tlMasterClockXingIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_size = x1_tlMasterClockXingIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_source = x1_tlMasterClockXingIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_address = x1_tlMasterClockXingIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_mask = x1_tlMasterClockXingIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_data = x1_tlMasterClockXingIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_a_bits_corrupt = x1_tlMasterClockXingIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_13_d_ready = x1_tlMasterClockXingIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_valid = x1_tlMasterClockXingIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_opcode = x1_tlMasterClockXingIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_param = x1_tlMasterClockXingIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_size = x1_tlMasterClockXingIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_source = x1_tlMasterClockXingIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_address = x1_tlMasterClockXingIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_mask = x1_tlMasterClockXingIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_data = x1_tlMasterClockXingIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_a_bits_corrupt = x1_tlMasterClockXingIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_14_d_ready = x1_tlMasterClockXingIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_valid = x1_tlMasterClockXingIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_opcode = x1_tlMasterClockXingIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_param = x1_tlMasterClockXingIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_size = x1_tlMasterClockXingIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_source = x1_tlMasterClockXingIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_address = x1_tlMasterClockXingIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_mask = x1_tlMasterClockXingIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_data = x1_tlMasterClockXingIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_a_bits_corrupt = x1_tlMasterClockXingIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_15_d_ready = x1_tlMasterClockXingIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_valid = x1_tlMasterClockXingIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_opcode = x1_tlMasterClockXingIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_param = x1_tlMasterClockXingIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_size = x1_tlMasterClockXingIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_source = x1_tlMasterClockXingIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_address = x1_tlMasterClockXingIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_mask = x1_tlMasterClockXingIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_data = x1_tlMasterClockXingIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_a_bits_corrupt = x1_tlMasterClockXingIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_16_d_ready = x1_tlMasterClockXingIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_valid = x1_tlMasterClockXingIn_17_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_opcode = x1_tlMasterClockXingIn_17_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_param = x1_tlMasterClockXingIn_17_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_size = x1_tlMasterClockXingIn_17_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_source = x1_tlMasterClockXingIn_17_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_address = x1_tlMasterClockXingIn_17_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_mask = x1_tlMasterClockXingIn_17_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_data = x1_tlMasterClockXingIn_17_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_a_bits_corrupt = x1_tlMasterClockXingIn_17_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_b_ready = x1_tlMasterClockXingIn_17_b_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_valid = x1_tlMasterClockXingIn_17_c_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_opcode = x1_tlMasterClockXingIn_17_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_param = x1_tlMasterClockXingIn_17_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_size = x1_tlMasterClockXingIn_17_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_source = x1_tlMasterClockXingIn_17_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_address = x1_tlMasterClockXingIn_17_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_data = x1_tlMasterClockXingIn_17_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_c_bits_corrupt = x1_tlMasterClockXingIn_17_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_d_ready = x1_tlMasterClockXingIn_17_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_e_valid = x1_tlMasterClockXingIn_17_e_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlMasterClockXingOut_17_e_bits_sink = x1_tlMasterClockXingIn_17_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17] RocketTile element_reset_domain_rockettile ( // @[HasTiles.scala:164:59] .clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31] .reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_18_a_ready (element_reset_domain_auto_rockettile_buffer_out_18_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_a_valid (element_reset_domain_auto_rockettile_buffer_out_18_a_valid), .auto_buffer_out_18_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_opcode), .auto_buffer_out_18_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_param), .auto_buffer_out_18_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_size), .auto_buffer_out_18_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_source), .auto_buffer_out_18_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_address), .auto_buffer_out_18_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_mask), .auto_buffer_out_18_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_data), .auto_buffer_out_18_b_ready (element_reset_domain_auto_rockettile_buffer_out_18_b_ready), .auto_buffer_out_18_b_valid (element_reset_domain_auto_rockettile_buffer_out_18_b_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_address), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_mask), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_c_ready (element_reset_domain_auto_rockettile_buffer_out_18_c_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_c_valid (element_reset_domain_auto_rockettile_buffer_out_18_c_valid), .auto_buffer_out_18_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_opcode), .auto_buffer_out_18_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_param), .auto_buffer_out_18_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_size), .auto_buffer_out_18_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_source), .auto_buffer_out_18_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_address), .auto_buffer_out_18_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_data), .auto_buffer_out_18_d_ready (element_reset_domain_auto_rockettile_buffer_out_18_d_ready), .auto_buffer_out_18_d_valid (element_reset_domain_auto_rockettile_buffer_out_18_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_e_ready (element_reset_domain_auto_rockettile_buffer_out_18_e_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_18_e_valid (element_reset_domain_auto_rockettile_buffer_out_18_e_valid), .auto_buffer_out_18_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_18_e_bits_sink), .auto_buffer_out_17_a_ready (element_reset_domain_auto_rockettile_buffer_out_17_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_a_valid (element_reset_domain_auto_rockettile_buffer_out_17_a_valid), .auto_buffer_out_17_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_opcode), .auto_buffer_out_17_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_param), .auto_buffer_out_17_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_size), .auto_buffer_out_17_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_source), .auto_buffer_out_17_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_address), .auto_buffer_out_17_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_mask), .auto_buffer_out_17_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_data), .auto_buffer_out_17_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_corrupt), .auto_buffer_out_17_d_ready (element_reset_domain_auto_rockettile_buffer_out_17_d_ready), .auto_buffer_out_17_d_valid (element_reset_domain_auto_rockettile_buffer_out_17_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_17_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_a_ready (element_reset_domain_auto_rockettile_buffer_out_16_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_a_valid (element_reset_domain_auto_rockettile_buffer_out_16_a_valid), .auto_buffer_out_16_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_opcode), .auto_buffer_out_16_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_param), .auto_buffer_out_16_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_size), .auto_buffer_out_16_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_source), .auto_buffer_out_16_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_address), .auto_buffer_out_16_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_mask), .auto_buffer_out_16_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_data), .auto_buffer_out_16_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_corrupt), .auto_buffer_out_16_d_ready (element_reset_domain_auto_rockettile_buffer_out_16_d_ready), .auto_buffer_out_16_d_valid (element_reset_domain_auto_rockettile_buffer_out_16_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_16_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_a_ready (element_reset_domain_auto_rockettile_buffer_out_15_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_a_valid (element_reset_domain_auto_rockettile_buffer_out_15_a_valid), .auto_buffer_out_15_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_opcode), .auto_buffer_out_15_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_param), .auto_buffer_out_15_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_size), .auto_buffer_out_15_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_source), .auto_buffer_out_15_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_address), .auto_buffer_out_15_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_mask), .auto_buffer_out_15_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_data), .auto_buffer_out_15_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_corrupt), .auto_buffer_out_15_d_ready (element_reset_domain_auto_rockettile_buffer_out_15_d_ready), .auto_buffer_out_15_d_valid (element_reset_domain_auto_rockettile_buffer_out_15_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_15_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_a_ready (element_reset_domain_auto_rockettile_buffer_out_14_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_a_valid (element_reset_domain_auto_rockettile_buffer_out_14_a_valid), .auto_buffer_out_14_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_opcode), .auto_buffer_out_14_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_param), .auto_buffer_out_14_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_size), .auto_buffer_out_14_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_source), .auto_buffer_out_14_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_address), .auto_buffer_out_14_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_mask), .auto_buffer_out_14_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_data), .auto_buffer_out_14_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_corrupt), .auto_buffer_out_14_d_ready (element_reset_domain_auto_rockettile_buffer_out_14_d_ready), .auto_buffer_out_14_d_valid (element_reset_domain_auto_rockettile_buffer_out_14_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_14_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_a_ready (element_reset_domain_auto_rockettile_buffer_out_13_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_a_valid (element_reset_domain_auto_rockettile_buffer_out_13_a_valid), .auto_buffer_out_13_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_opcode), .auto_buffer_out_13_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_param), .auto_buffer_out_13_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_size), .auto_buffer_out_13_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_source), .auto_buffer_out_13_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_address), .auto_buffer_out_13_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_mask), .auto_buffer_out_13_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_data), .auto_buffer_out_13_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_corrupt), .auto_buffer_out_13_d_ready (element_reset_domain_auto_rockettile_buffer_out_13_d_ready), .auto_buffer_out_13_d_valid (element_reset_domain_auto_rockettile_buffer_out_13_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_13_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_a_ready (element_reset_domain_auto_rockettile_buffer_out_12_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_a_valid (element_reset_domain_auto_rockettile_buffer_out_12_a_valid), .auto_buffer_out_12_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_opcode), .auto_buffer_out_12_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_param), .auto_buffer_out_12_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_size), .auto_buffer_out_12_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_source), .auto_buffer_out_12_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_address), .auto_buffer_out_12_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_mask), .auto_buffer_out_12_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_data), .auto_buffer_out_12_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_corrupt), .auto_buffer_out_12_d_ready (element_reset_domain_auto_rockettile_buffer_out_12_d_ready), .auto_buffer_out_12_d_valid (element_reset_domain_auto_rockettile_buffer_out_12_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_12_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_a_ready (element_reset_domain_auto_rockettile_buffer_out_11_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_a_valid (element_reset_domain_auto_rockettile_buffer_out_11_a_valid), .auto_buffer_out_11_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_opcode), .auto_buffer_out_11_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_param), .auto_buffer_out_11_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_size), .auto_buffer_out_11_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_source), .auto_buffer_out_11_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_address), .auto_buffer_out_11_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_mask), .auto_buffer_out_11_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_data), .auto_buffer_out_11_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_corrupt), .auto_buffer_out_11_d_ready (element_reset_domain_auto_rockettile_buffer_out_11_d_ready), .auto_buffer_out_11_d_valid (element_reset_domain_auto_rockettile_buffer_out_11_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_11_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_a_ready (element_reset_domain_auto_rockettile_buffer_out_10_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_a_valid (element_reset_domain_auto_rockettile_buffer_out_10_a_valid), .auto_buffer_out_10_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_opcode), .auto_buffer_out_10_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_param), .auto_buffer_out_10_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_size), .auto_buffer_out_10_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_source), .auto_buffer_out_10_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_address), .auto_buffer_out_10_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_mask), .auto_buffer_out_10_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_data), .auto_buffer_out_10_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_corrupt), .auto_buffer_out_10_d_ready (element_reset_domain_auto_rockettile_buffer_out_10_d_ready), .auto_buffer_out_10_d_valid (element_reset_domain_auto_rockettile_buffer_out_10_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_10_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_a_ready (element_reset_domain_auto_rockettile_buffer_out_9_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_a_valid (element_reset_domain_auto_rockettile_buffer_out_9_a_valid), .auto_buffer_out_9_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_opcode), .auto_buffer_out_9_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_param), .auto_buffer_out_9_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_size), .auto_buffer_out_9_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_source), .auto_buffer_out_9_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_address), .auto_buffer_out_9_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_mask), .auto_buffer_out_9_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_data), .auto_buffer_out_9_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_corrupt), .auto_buffer_out_9_d_ready (element_reset_domain_auto_rockettile_buffer_out_9_d_ready), .auto_buffer_out_9_d_valid (element_reset_domain_auto_rockettile_buffer_out_9_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_9_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_a_ready (element_reset_domain_auto_rockettile_buffer_out_8_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_a_valid (element_reset_domain_auto_rockettile_buffer_out_8_a_valid), .auto_buffer_out_8_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_opcode), .auto_buffer_out_8_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_param), .auto_buffer_out_8_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_size), .auto_buffer_out_8_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_source), .auto_buffer_out_8_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_address), .auto_buffer_out_8_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_mask), .auto_buffer_out_8_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_data), .auto_buffer_out_8_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_corrupt), .auto_buffer_out_8_d_ready (element_reset_domain_auto_rockettile_buffer_out_8_d_ready), .auto_buffer_out_8_d_valid (element_reset_domain_auto_rockettile_buffer_out_8_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_8_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_a_ready (element_reset_domain_auto_rockettile_buffer_out_7_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_a_valid (element_reset_domain_auto_rockettile_buffer_out_7_a_valid), .auto_buffer_out_7_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_opcode), .auto_buffer_out_7_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_param), .auto_buffer_out_7_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_size), .auto_buffer_out_7_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_source), .auto_buffer_out_7_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_address), .auto_buffer_out_7_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_mask), .auto_buffer_out_7_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_data), .auto_buffer_out_7_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_corrupt), .auto_buffer_out_7_d_ready (element_reset_domain_auto_rockettile_buffer_out_7_d_ready), .auto_buffer_out_7_d_valid (element_reset_domain_auto_rockettile_buffer_out_7_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_7_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_a_ready (element_reset_domain_auto_rockettile_buffer_out_6_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_a_valid (element_reset_domain_auto_rockettile_buffer_out_6_a_valid), .auto_buffer_out_6_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_opcode), .auto_buffer_out_6_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_param), .auto_buffer_out_6_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_size), .auto_buffer_out_6_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_source), .auto_buffer_out_6_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_address), .auto_buffer_out_6_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_mask), .auto_buffer_out_6_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_data), .auto_buffer_out_6_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_corrupt), .auto_buffer_out_6_d_ready (element_reset_domain_auto_rockettile_buffer_out_6_d_ready), .auto_buffer_out_6_d_valid (element_reset_domain_auto_rockettile_buffer_out_6_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_6_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_a_ready (element_reset_domain_auto_rockettile_buffer_out_5_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_a_valid (element_reset_domain_auto_rockettile_buffer_out_5_a_valid), .auto_buffer_out_5_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_opcode), .auto_buffer_out_5_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_param), .auto_buffer_out_5_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_size), .auto_buffer_out_5_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_source), .auto_buffer_out_5_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_address), .auto_buffer_out_5_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_mask), .auto_buffer_out_5_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_data), .auto_buffer_out_5_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_corrupt), .auto_buffer_out_5_d_ready (element_reset_domain_auto_rockettile_buffer_out_5_d_ready), .auto_buffer_out_5_d_valid (element_reset_domain_auto_rockettile_buffer_out_5_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_5_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_a_ready (element_reset_domain_auto_rockettile_buffer_out_4_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_a_valid (element_reset_domain_auto_rockettile_buffer_out_4_a_valid), .auto_buffer_out_4_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_opcode), .auto_buffer_out_4_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_param), .auto_buffer_out_4_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_size), .auto_buffer_out_4_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_source), .auto_buffer_out_4_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_address), .auto_buffer_out_4_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_mask), .auto_buffer_out_4_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_data), .auto_buffer_out_4_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_corrupt), .auto_buffer_out_4_d_ready (element_reset_domain_auto_rockettile_buffer_out_4_d_ready), .auto_buffer_out_4_d_valid (element_reset_domain_auto_rockettile_buffer_out_4_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_4_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_a_ready (element_reset_domain_auto_rockettile_buffer_out_3_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_a_valid (element_reset_domain_auto_rockettile_buffer_out_3_a_valid), .auto_buffer_out_3_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_opcode), .auto_buffer_out_3_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_param), .auto_buffer_out_3_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_size), .auto_buffer_out_3_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_source), .auto_buffer_out_3_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_address), .auto_buffer_out_3_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_mask), .auto_buffer_out_3_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_data), .auto_buffer_out_3_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_corrupt), .auto_buffer_out_3_d_ready (element_reset_domain_auto_rockettile_buffer_out_3_d_ready), .auto_buffer_out_3_d_valid (element_reset_domain_auto_rockettile_buffer_out_3_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_3_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_a_ready (element_reset_domain_auto_rockettile_buffer_out_2_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_a_valid (element_reset_domain_auto_rockettile_buffer_out_2_a_valid), .auto_buffer_out_2_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_opcode), .auto_buffer_out_2_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_param), .auto_buffer_out_2_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_size), .auto_buffer_out_2_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_source), .auto_buffer_out_2_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_address), .auto_buffer_out_2_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_mask), .auto_buffer_out_2_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_data), .auto_buffer_out_2_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_corrupt), .auto_buffer_out_2_d_ready (element_reset_domain_auto_rockettile_buffer_out_2_d_ready), .auto_buffer_out_2_d_valid (element_reset_domain_auto_rockettile_buffer_out_2_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_2_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_a_ready (element_reset_domain_auto_rockettile_buffer_out_1_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_a_valid (element_reset_domain_auto_rockettile_buffer_out_1_a_valid), .auto_buffer_out_1_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode), .auto_buffer_out_1_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param), .auto_buffer_out_1_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size), .auto_buffer_out_1_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source), .auto_buffer_out_1_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address), .auto_buffer_out_1_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask), .auto_buffer_out_1_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data), .auto_buffer_out_1_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_corrupt), .auto_buffer_out_1_d_ready (element_reset_domain_auto_rockettile_buffer_out_1_d_ready), .auto_buffer_out_1_d_valid (element_reset_domain_auto_rockettile_buffer_out_1_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_1_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_a_ready (element_reset_domain_auto_rockettile_buffer_out_0_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_a_valid (element_reset_domain_auto_rockettile_buffer_out_0_a_valid), .auto_buffer_out_0_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode), .auto_buffer_out_0_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param), .auto_buffer_out_0_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size), .auto_buffer_out_0_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source), .auto_buffer_out_0_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address), .auto_buffer_out_0_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask), .auto_buffer_out_0_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data), .auto_buffer_out_0_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt), .auto_buffer_out_0_d_ready (element_reset_domain_auto_rockettile_buffer_out_0_d_ready), .auto_buffer_out_0_d_valid (element_reset_domain_auto_rockettile_buffer_out_0_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_0_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0), .auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9] .auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9] .auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9] .auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid), .auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr), .auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn), .auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv), .auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception), .auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt), .auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause), .auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval), .auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time), .auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9] ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s2k3z4u_1 buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_18_a_ready (element_reset_domain_auto_rockettile_buffer_out_18_a_ready), .auto_in_18_a_valid (element_reset_domain_auto_rockettile_buffer_out_18_a_valid), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_18_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_18_b_ready (element_reset_domain_auto_rockettile_buffer_out_18_b_ready), // @[ClockDomain.scala:14:9] .auto_in_18_b_valid (element_reset_domain_auto_rockettile_buffer_out_18_b_valid), .auto_in_18_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_opcode), .auto_in_18_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_param), .auto_in_18_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_size), .auto_in_18_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_source), .auto_in_18_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_address), .auto_in_18_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_mask), .auto_in_18_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_data), .auto_in_18_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_18_b_bits_corrupt), .auto_in_18_c_ready (element_reset_domain_auto_rockettile_buffer_out_18_c_ready), .auto_in_18_c_valid (element_reset_domain_auto_rockettile_buffer_out_18_c_valid), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_param), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_size), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_source), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_address), // @[ClockDomain.scala:14:9] .auto_in_18_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_c_bits_data), // @[ClockDomain.scala:14:9] .auto_in_18_d_ready (element_reset_domain_auto_rockettile_buffer_out_18_d_ready), // @[ClockDomain.scala:14:9] .auto_in_18_d_valid (element_reset_domain_auto_rockettile_buffer_out_18_d_valid), .auto_in_18_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_opcode), .auto_in_18_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_param), .auto_in_18_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_size), .auto_in_18_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_source), .auto_in_18_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_sink), .auto_in_18_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_denied), .auto_in_18_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_data), .auto_in_18_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_18_d_bits_corrupt), .auto_in_18_e_ready (element_reset_domain_auto_rockettile_buffer_out_18_e_ready), .auto_in_18_e_valid (element_reset_domain_auto_rockettile_buffer_out_18_e_valid), // @[ClockDomain.scala:14:9] .auto_in_18_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_18_e_bits_sink), // @[ClockDomain.scala:14:9] .auto_in_17_a_ready (element_reset_domain_auto_rockettile_buffer_out_17_a_ready), .auto_in_17_a_valid (element_reset_domain_auto_rockettile_buffer_out_17_a_valid), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_17_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_17_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_17_d_ready (element_reset_domain_auto_rockettile_buffer_out_17_d_ready), // @[ClockDomain.scala:14:9] .auto_in_17_d_valid (element_reset_domain_auto_rockettile_buffer_out_17_d_valid), .auto_in_17_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_opcode), .auto_in_17_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_param), .auto_in_17_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_size), .auto_in_17_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_source), .auto_in_17_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_sink), .auto_in_17_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_denied), .auto_in_17_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_data), .auto_in_17_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_17_d_bits_corrupt), .auto_in_16_a_ready (element_reset_domain_auto_rockettile_buffer_out_16_a_ready), .auto_in_16_a_valid (element_reset_domain_auto_rockettile_buffer_out_16_a_valid), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_16_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_16_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_16_d_ready (element_reset_domain_auto_rockettile_buffer_out_16_d_ready), // @[ClockDomain.scala:14:9] .auto_in_16_d_valid (element_reset_domain_auto_rockettile_buffer_out_16_d_valid), .auto_in_16_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_opcode), .auto_in_16_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_param), .auto_in_16_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_size), .auto_in_16_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_source), .auto_in_16_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_sink), .auto_in_16_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_denied), .auto_in_16_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_data), .auto_in_16_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_16_d_bits_corrupt), .auto_in_15_a_ready (element_reset_domain_auto_rockettile_buffer_out_15_a_ready), .auto_in_15_a_valid (element_reset_domain_auto_rockettile_buffer_out_15_a_valid), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_15_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_15_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_15_d_ready (element_reset_domain_auto_rockettile_buffer_out_15_d_ready), // @[ClockDomain.scala:14:9] .auto_in_15_d_valid (element_reset_domain_auto_rockettile_buffer_out_15_d_valid), .auto_in_15_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_opcode), .auto_in_15_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_param), .auto_in_15_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_size), .auto_in_15_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_source), .auto_in_15_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_sink), .auto_in_15_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_denied), .auto_in_15_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_data), .auto_in_15_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_15_d_bits_corrupt), .auto_in_14_a_ready (element_reset_domain_auto_rockettile_buffer_out_14_a_ready), .auto_in_14_a_valid (element_reset_domain_auto_rockettile_buffer_out_14_a_valid), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_14_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_14_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_14_d_ready (element_reset_domain_auto_rockettile_buffer_out_14_d_ready), // @[ClockDomain.scala:14:9] .auto_in_14_d_valid (element_reset_domain_auto_rockettile_buffer_out_14_d_valid), .auto_in_14_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_opcode), .auto_in_14_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_param), .auto_in_14_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_size), .auto_in_14_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_source), .auto_in_14_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_sink), .auto_in_14_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_denied), .auto_in_14_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_data), .auto_in_14_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_14_d_bits_corrupt), .auto_in_13_a_ready (element_reset_domain_auto_rockettile_buffer_out_13_a_ready), .auto_in_13_a_valid (element_reset_domain_auto_rockettile_buffer_out_13_a_valid), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_13_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_13_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_13_d_ready (element_reset_domain_auto_rockettile_buffer_out_13_d_ready), // @[ClockDomain.scala:14:9] .auto_in_13_d_valid (element_reset_domain_auto_rockettile_buffer_out_13_d_valid), .auto_in_13_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_opcode), .auto_in_13_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_param), .auto_in_13_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_size), .auto_in_13_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_source), .auto_in_13_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_sink), .auto_in_13_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_denied), .auto_in_13_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_data), .auto_in_13_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_13_d_bits_corrupt), .auto_in_12_a_ready (element_reset_domain_auto_rockettile_buffer_out_12_a_ready), .auto_in_12_a_valid (element_reset_domain_auto_rockettile_buffer_out_12_a_valid), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_12_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_12_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_12_d_ready (element_reset_domain_auto_rockettile_buffer_out_12_d_ready), // @[ClockDomain.scala:14:9] .auto_in_12_d_valid (element_reset_domain_auto_rockettile_buffer_out_12_d_valid), .auto_in_12_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_opcode), .auto_in_12_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_param), .auto_in_12_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_size), .auto_in_12_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_source), .auto_in_12_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_sink), .auto_in_12_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_denied), .auto_in_12_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_data), .auto_in_12_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_12_d_bits_corrupt), .auto_in_11_a_ready (element_reset_domain_auto_rockettile_buffer_out_11_a_ready), .auto_in_11_a_valid (element_reset_domain_auto_rockettile_buffer_out_11_a_valid), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_11_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_11_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_11_d_ready (element_reset_domain_auto_rockettile_buffer_out_11_d_ready), // @[ClockDomain.scala:14:9] .auto_in_11_d_valid (element_reset_domain_auto_rockettile_buffer_out_11_d_valid), .auto_in_11_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_opcode), .auto_in_11_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_param), .auto_in_11_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_size), .auto_in_11_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_source), .auto_in_11_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_sink), .auto_in_11_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_denied), .auto_in_11_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_data), .auto_in_11_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_11_d_bits_corrupt), .auto_in_10_a_ready (element_reset_domain_auto_rockettile_buffer_out_10_a_ready), .auto_in_10_a_valid (element_reset_domain_auto_rockettile_buffer_out_10_a_valid), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_10_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_10_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_10_d_ready (element_reset_domain_auto_rockettile_buffer_out_10_d_ready), // @[ClockDomain.scala:14:9] .auto_in_10_d_valid (element_reset_domain_auto_rockettile_buffer_out_10_d_valid), .auto_in_10_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_opcode), .auto_in_10_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_param), .auto_in_10_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_size), .auto_in_10_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_source), .auto_in_10_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_sink), .auto_in_10_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_denied), .auto_in_10_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_data), .auto_in_10_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_10_d_bits_corrupt), .auto_in_9_a_ready (element_reset_domain_auto_rockettile_buffer_out_9_a_ready), .auto_in_9_a_valid (element_reset_domain_auto_rockettile_buffer_out_9_a_valid), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_9_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_9_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_9_d_ready (element_reset_domain_auto_rockettile_buffer_out_9_d_ready), // @[ClockDomain.scala:14:9] .auto_in_9_d_valid (element_reset_domain_auto_rockettile_buffer_out_9_d_valid), .auto_in_9_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_opcode), .auto_in_9_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_param), .auto_in_9_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_size), .auto_in_9_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_source), .auto_in_9_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_sink), .auto_in_9_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_denied), .auto_in_9_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_data), .auto_in_9_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_9_d_bits_corrupt), .auto_in_8_a_ready (element_reset_domain_auto_rockettile_buffer_out_8_a_ready), .auto_in_8_a_valid (element_reset_domain_auto_rockettile_buffer_out_8_a_valid), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_8_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_8_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_8_d_ready (element_reset_domain_auto_rockettile_buffer_out_8_d_ready), // @[ClockDomain.scala:14:9] .auto_in_8_d_valid (element_reset_domain_auto_rockettile_buffer_out_8_d_valid), .auto_in_8_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_opcode), .auto_in_8_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_param), .auto_in_8_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_size), .auto_in_8_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_source), .auto_in_8_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_sink), .auto_in_8_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_denied), .auto_in_8_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_data), .auto_in_8_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_8_d_bits_corrupt), .auto_in_7_a_ready (element_reset_domain_auto_rockettile_buffer_out_7_a_ready), .auto_in_7_a_valid (element_reset_domain_auto_rockettile_buffer_out_7_a_valid), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_7_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_7_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_7_d_ready (element_reset_domain_auto_rockettile_buffer_out_7_d_ready), // @[ClockDomain.scala:14:9] .auto_in_7_d_valid (element_reset_domain_auto_rockettile_buffer_out_7_d_valid), .auto_in_7_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_opcode), .auto_in_7_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_param), .auto_in_7_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_size), .auto_in_7_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_source), .auto_in_7_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_sink), .auto_in_7_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_denied), .auto_in_7_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_data), .auto_in_7_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_7_d_bits_corrupt), .auto_in_6_a_ready (element_reset_domain_auto_rockettile_buffer_out_6_a_ready), .auto_in_6_a_valid (element_reset_domain_auto_rockettile_buffer_out_6_a_valid), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_6_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_6_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_6_d_ready (element_reset_domain_auto_rockettile_buffer_out_6_d_ready), // @[ClockDomain.scala:14:9] .auto_in_6_d_valid (element_reset_domain_auto_rockettile_buffer_out_6_d_valid), .auto_in_6_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_opcode), .auto_in_6_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_param), .auto_in_6_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_size), .auto_in_6_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_source), .auto_in_6_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_sink), .auto_in_6_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_denied), .auto_in_6_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_data), .auto_in_6_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_6_d_bits_corrupt), .auto_in_5_a_ready (element_reset_domain_auto_rockettile_buffer_out_5_a_ready), .auto_in_5_a_valid (element_reset_domain_auto_rockettile_buffer_out_5_a_valid), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_5_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_5_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_5_d_ready (element_reset_domain_auto_rockettile_buffer_out_5_d_ready), // @[ClockDomain.scala:14:9] .auto_in_5_d_valid (element_reset_domain_auto_rockettile_buffer_out_5_d_valid), .auto_in_5_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_opcode), .auto_in_5_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_param), .auto_in_5_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_size), .auto_in_5_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_source), .auto_in_5_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_sink), .auto_in_5_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_denied), .auto_in_5_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_data), .auto_in_5_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_5_d_bits_corrupt), .auto_in_4_a_ready (element_reset_domain_auto_rockettile_buffer_out_4_a_ready), .auto_in_4_a_valid (element_reset_domain_auto_rockettile_buffer_out_4_a_valid), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_4_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_4_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_4_d_ready (element_reset_domain_auto_rockettile_buffer_out_4_d_ready), // @[ClockDomain.scala:14:9] .auto_in_4_d_valid (element_reset_domain_auto_rockettile_buffer_out_4_d_valid), .auto_in_4_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_opcode), .auto_in_4_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_param), .auto_in_4_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_size), .auto_in_4_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_source), .auto_in_4_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_sink), .auto_in_4_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_denied), .auto_in_4_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_data), .auto_in_4_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_4_d_bits_corrupt), .auto_in_3_a_ready (element_reset_domain_auto_rockettile_buffer_out_3_a_ready), .auto_in_3_a_valid (element_reset_domain_auto_rockettile_buffer_out_3_a_valid), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_3_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_3_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_3_d_ready (element_reset_domain_auto_rockettile_buffer_out_3_d_ready), // @[ClockDomain.scala:14:9] .auto_in_3_d_valid (element_reset_domain_auto_rockettile_buffer_out_3_d_valid), .auto_in_3_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_opcode), .auto_in_3_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_param), .auto_in_3_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_size), .auto_in_3_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_source), .auto_in_3_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_sink), .auto_in_3_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_denied), .auto_in_3_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_data), .auto_in_3_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_3_d_bits_corrupt), .auto_in_2_a_ready (element_reset_domain_auto_rockettile_buffer_out_2_a_ready), .auto_in_2_a_valid (element_reset_domain_auto_rockettile_buffer_out_2_a_valid), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_2_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_2_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_2_d_ready (element_reset_domain_auto_rockettile_buffer_out_2_d_ready), // @[ClockDomain.scala:14:9] .auto_in_2_d_valid (element_reset_domain_auto_rockettile_buffer_out_2_d_valid), .auto_in_2_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_opcode), .auto_in_2_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_param), .auto_in_2_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_size), .auto_in_2_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_source), .auto_in_2_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_sink), .auto_in_2_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_denied), .auto_in_2_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_data), .auto_in_2_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_2_d_bits_corrupt), .auto_in_1_a_ready (element_reset_domain_auto_rockettile_buffer_out_1_a_ready), .auto_in_1_a_valid (element_reset_domain_auto_rockettile_buffer_out_1_a_valid), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_1_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_1_d_ready (element_reset_domain_auto_rockettile_buffer_out_1_d_ready), // @[ClockDomain.scala:14:9] .auto_in_1_d_valid (element_reset_domain_auto_rockettile_buffer_out_1_d_valid), .auto_in_1_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode), .auto_in_1_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param), .auto_in_1_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size), .auto_in_1_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source), .auto_in_1_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink), .auto_in_1_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied), .auto_in_1_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data), .auto_in_1_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt), .auto_in_0_a_ready (element_reset_domain_auto_rockettile_buffer_out_0_a_ready), .auto_in_0_a_valid (element_reset_domain_auto_rockettile_buffer_out_0_a_valid), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_0_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_in_0_d_ready (element_reset_domain_auto_rockettile_buffer_out_0_d_ready), // @[ClockDomain.scala:14:9] .auto_in_0_d_valid (element_reset_domain_auto_rockettile_buffer_out_0_d_valid), .auto_in_0_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode), .auto_in_0_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param), .auto_in_0_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size), .auto_in_0_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source), .auto_in_0_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink), .auto_in_0_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied), .auto_in_0_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data), .auto_in_0_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt), .auto_out_18_a_ready (x1_tlMasterClockXingIn_17_a_ready), // @[MixedNode.scala:551:17] .auto_out_18_a_valid (x1_tlMasterClockXingIn_17_a_valid), .auto_out_18_a_bits_opcode (x1_tlMasterClockXingIn_17_a_bits_opcode), .auto_out_18_a_bits_param (x1_tlMasterClockXingIn_17_a_bits_param), .auto_out_18_a_bits_size (x1_tlMasterClockXingIn_17_a_bits_size), .auto_out_18_a_bits_source (x1_tlMasterClockXingIn_17_a_bits_source), .auto_out_18_a_bits_address (x1_tlMasterClockXingIn_17_a_bits_address), .auto_out_18_a_bits_mask (x1_tlMasterClockXingIn_17_a_bits_mask), .auto_out_18_a_bits_data (x1_tlMasterClockXingIn_17_a_bits_data), .auto_out_18_a_bits_corrupt (x1_tlMasterClockXingIn_17_a_bits_corrupt), .auto_out_18_b_ready (x1_tlMasterClockXingIn_17_b_ready), .auto_out_18_b_valid (x1_tlMasterClockXingIn_17_b_valid), // @[MixedNode.scala:551:17] .auto_out_18_b_bits_param (x1_tlMasterClockXingIn_17_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_18_b_bits_address (x1_tlMasterClockXingIn_17_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_18_c_ready (x1_tlMasterClockXingIn_17_c_ready), // @[MixedNode.scala:551:17] .auto_out_18_c_valid (x1_tlMasterClockXingIn_17_c_valid), .auto_out_18_c_bits_opcode (x1_tlMasterClockXingIn_17_c_bits_opcode), .auto_out_18_c_bits_param (x1_tlMasterClockXingIn_17_c_bits_param), .auto_out_18_c_bits_size (x1_tlMasterClockXingIn_17_c_bits_size), .auto_out_18_c_bits_source (x1_tlMasterClockXingIn_17_c_bits_source), .auto_out_18_c_bits_address (x1_tlMasterClockXingIn_17_c_bits_address), .auto_out_18_c_bits_data (x1_tlMasterClockXingIn_17_c_bits_data), .auto_out_18_c_bits_corrupt (x1_tlMasterClockXingIn_17_c_bits_corrupt), .auto_out_18_d_ready (x1_tlMasterClockXingIn_17_d_ready), .auto_out_18_d_valid (x1_tlMasterClockXingIn_17_d_valid), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_opcode (x1_tlMasterClockXingIn_17_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_param (x1_tlMasterClockXingIn_17_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_size (x1_tlMasterClockXingIn_17_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_source (x1_tlMasterClockXingIn_17_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_sink (x1_tlMasterClockXingIn_17_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_denied (x1_tlMasterClockXingIn_17_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_data (x1_tlMasterClockXingIn_17_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_18_d_bits_corrupt (x1_tlMasterClockXingIn_17_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_18_e_valid (x1_tlMasterClockXingIn_17_e_valid), .auto_out_18_e_bits_sink (x1_tlMasterClockXingIn_17_e_bits_sink), .auto_out_17_a_ready (x1_tlMasterClockXingIn_16_a_ready), // @[MixedNode.scala:551:17] .auto_out_17_a_valid (x1_tlMasterClockXingIn_16_a_valid), .auto_out_17_a_bits_opcode (x1_tlMasterClockXingIn_16_a_bits_opcode), .auto_out_17_a_bits_param (x1_tlMasterClockXingIn_16_a_bits_param), .auto_out_17_a_bits_size (x1_tlMasterClockXingIn_16_a_bits_size), .auto_out_17_a_bits_source (x1_tlMasterClockXingIn_16_a_bits_source), .auto_out_17_a_bits_address (x1_tlMasterClockXingIn_16_a_bits_address), .auto_out_17_a_bits_mask (x1_tlMasterClockXingIn_16_a_bits_mask), .auto_out_17_a_bits_data (x1_tlMasterClockXingIn_16_a_bits_data), .auto_out_17_a_bits_corrupt (x1_tlMasterClockXingIn_16_a_bits_corrupt), .auto_out_17_d_ready (x1_tlMasterClockXingIn_16_d_ready), .auto_out_17_d_valid (x1_tlMasterClockXingIn_16_d_valid), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_opcode (x1_tlMasterClockXingIn_16_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_param (x1_tlMasterClockXingIn_16_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_size (x1_tlMasterClockXingIn_16_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_source (x1_tlMasterClockXingIn_16_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_sink (x1_tlMasterClockXingIn_16_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_denied (x1_tlMasterClockXingIn_16_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_data (x1_tlMasterClockXingIn_16_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_17_d_bits_corrupt (x1_tlMasterClockXingIn_16_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_16_a_ready (x1_tlMasterClockXingIn_15_a_ready), // @[MixedNode.scala:551:17] .auto_out_16_a_valid (x1_tlMasterClockXingIn_15_a_valid), .auto_out_16_a_bits_opcode (x1_tlMasterClockXingIn_15_a_bits_opcode), .auto_out_16_a_bits_param (x1_tlMasterClockXingIn_15_a_bits_param), .auto_out_16_a_bits_size (x1_tlMasterClockXingIn_15_a_bits_size), .auto_out_16_a_bits_source (x1_tlMasterClockXingIn_15_a_bits_source), .auto_out_16_a_bits_address (x1_tlMasterClockXingIn_15_a_bits_address), .auto_out_16_a_bits_mask (x1_tlMasterClockXingIn_15_a_bits_mask), .auto_out_16_a_bits_data (x1_tlMasterClockXingIn_15_a_bits_data), .auto_out_16_a_bits_corrupt (x1_tlMasterClockXingIn_15_a_bits_corrupt), .auto_out_16_d_ready (x1_tlMasterClockXingIn_15_d_ready), .auto_out_16_d_valid (x1_tlMasterClockXingIn_15_d_valid), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_opcode (x1_tlMasterClockXingIn_15_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_param (x1_tlMasterClockXingIn_15_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_size (x1_tlMasterClockXingIn_15_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_source (x1_tlMasterClockXingIn_15_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_sink (x1_tlMasterClockXingIn_15_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_denied (x1_tlMasterClockXingIn_15_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_data (x1_tlMasterClockXingIn_15_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_16_d_bits_corrupt (x1_tlMasterClockXingIn_15_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_15_a_ready (x1_tlMasterClockXingIn_14_a_ready), // @[MixedNode.scala:551:17] .auto_out_15_a_valid (x1_tlMasterClockXingIn_14_a_valid), .auto_out_15_a_bits_opcode (x1_tlMasterClockXingIn_14_a_bits_opcode), .auto_out_15_a_bits_param (x1_tlMasterClockXingIn_14_a_bits_param), .auto_out_15_a_bits_size (x1_tlMasterClockXingIn_14_a_bits_size), .auto_out_15_a_bits_source (x1_tlMasterClockXingIn_14_a_bits_source), .auto_out_15_a_bits_address (x1_tlMasterClockXingIn_14_a_bits_address), .auto_out_15_a_bits_mask (x1_tlMasterClockXingIn_14_a_bits_mask), .auto_out_15_a_bits_data (x1_tlMasterClockXingIn_14_a_bits_data), .auto_out_15_a_bits_corrupt (x1_tlMasterClockXingIn_14_a_bits_corrupt), .auto_out_15_d_ready (x1_tlMasterClockXingIn_14_d_ready), .auto_out_15_d_valid (x1_tlMasterClockXingIn_14_d_valid), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_opcode (x1_tlMasterClockXingIn_14_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_param (x1_tlMasterClockXingIn_14_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_size (x1_tlMasterClockXingIn_14_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_source (x1_tlMasterClockXingIn_14_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_sink (x1_tlMasterClockXingIn_14_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_denied (x1_tlMasterClockXingIn_14_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_data (x1_tlMasterClockXingIn_14_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_15_d_bits_corrupt (x1_tlMasterClockXingIn_14_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_14_a_ready (x1_tlMasterClockXingIn_13_a_ready), // @[MixedNode.scala:551:17] .auto_out_14_a_valid (x1_tlMasterClockXingIn_13_a_valid), .auto_out_14_a_bits_opcode (x1_tlMasterClockXingIn_13_a_bits_opcode), .auto_out_14_a_bits_param (x1_tlMasterClockXingIn_13_a_bits_param), .auto_out_14_a_bits_size (x1_tlMasterClockXingIn_13_a_bits_size), .auto_out_14_a_bits_source (x1_tlMasterClockXingIn_13_a_bits_source), .auto_out_14_a_bits_address (x1_tlMasterClockXingIn_13_a_bits_address), .auto_out_14_a_bits_mask (x1_tlMasterClockXingIn_13_a_bits_mask), .auto_out_14_a_bits_data (x1_tlMasterClockXingIn_13_a_bits_data), .auto_out_14_a_bits_corrupt (x1_tlMasterClockXingIn_13_a_bits_corrupt), .auto_out_14_d_ready (x1_tlMasterClockXingIn_13_d_ready), .auto_out_14_d_valid (x1_tlMasterClockXingIn_13_d_valid), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_opcode (x1_tlMasterClockXingIn_13_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_param (x1_tlMasterClockXingIn_13_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_size (x1_tlMasterClockXingIn_13_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_source (x1_tlMasterClockXingIn_13_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_sink (x1_tlMasterClockXingIn_13_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_denied (x1_tlMasterClockXingIn_13_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_data (x1_tlMasterClockXingIn_13_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_14_d_bits_corrupt (x1_tlMasterClockXingIn_13_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_13_a_ready (x1_tlMasterClockXingIn_12_a_ready), // @[MixedNode.scala:551:17] .auto_out_13_a_valid (x1_tlMasterClockXingIn_12_a_valid), .auto_out_13_a_bits_opcode (x1_tlMasterClockXingIn_12_a_bits_opcode), .auto_out_13_a_bits_param (x1_tlMasterClockXingIn_12_a_bits_param), .auto_out_13_a_bits_size (x1_tlMasterClockXingIn_12_a_bits_size), .auto_out_13_a_bits_source (x1_tlMasterClockXingIn_12_a_bits_source), .auto_out_13_a_bits_address (x1_tlMasterClockXingIn_12_a_bits_address), .auto_out_13_a_bits_mask (x1_tlMasterClockXingIn_12_a_bits_mask), .auto_out_13_a_bits_data (x1_tlMasterClockXingIn_12_a_bits_data), .auto_out_13_a_bits_corrupt (x1_tlMasterClockXingIn_12_a_bits_corrupt), .auto_out_13_d_ready (x1_tlMasterClockXingIn_12_d_ready), .auto_out_13_d_valid (x1_tlMasterClockXingIn_12_d_valid), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_opcode (x1_tlMasterClockXingIn_12_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_param (x1_tlMasterClockXingIn_12_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_size (x1_tlMasterClockXingIn_12_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_source (x1_tlMasterClockXingIn_12_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_sink (x1_tlMasterClockXingIn_12_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_denied (x1_tlMasterClockXingIn_12_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_data (x1_tlMasterClockXingIn_12_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_13_d_bits_corrupt (x1_tlMasterClockXingIn_12_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_12_a_ready (x1_tlMasterClockXingIn_11_a_ready), // @[MixedNode.scala:551:17] .auto_out_12_a_valid (x1_tlMasterClockXingIn_11_a_valid), .auto_out_12_a_bits_opcode (x1_tlMasterClockXingIn_11_a_bits_opcode), .auto_out_12_a_bits_param (x1_tlMasterClockXingIn_11_a_bits_param), .auto_out_12_a_bits_size (x1_tlMasterClockXingIn_11_a_bits_size), .auto_out_12_a_bits_source (x1_tlMasterClockXingIn_11_a_bits_source), .auto_out_12_a_bits_address (x1_tlMasterClockXingIn_11_a_bits_address), .auto_out_12_a_bits_mask (x1_tlMasterClockXingIn_11_a_bits_mask), .auto_out_12_a_bits_data (x1_tlMasterClockXingIn_11_a_bits_data), .auto_out_12_a_bits_corrupt (x1_tlMasterClockXingIn_11_a_bits_corrupt), .auto_out_12_d_ready (x1_tlMasterClockXingIn_11_d_ready), .auto_out_12_d_valid (x1_tlMasterClockXingIn_11_d_valid), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_opcode (x1_tlMasterClockXingIn_11_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_param (x1_tlMasterClockXingIn_11_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_size (x1_tlMasterClockXingIn_11_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_source (x1_tlMasterClockXingIn_11_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_sink (x1_tlMasterClockXingIn_11_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_denied (x1_tlMasterClockXingIn_11_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_data (x1_tlMasterClockXingIn_11_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_12_d_bits_corrupt (x1_tlMasterClockXingIn_11_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_11_a_ready (x1_tlMasterClockXingIn_10_a_ready), // @[MixedNode.scala:551:17] .auto_out_11_a_valid (x1_tlMasterClockXingIn_10_a_valid), .auto_out_11_a_bits_opcode (x1_tlMasterClockXingIn_10_a_bits_opcode), .auto_out_11_a_bits_param (x1_tlMasterClockXingIn_10_a_bits_param), .auto_out_11_a_bits_size (x1_tlMasterClockXingIn_10_a_bits_size), .auto_out_11_a_bits_source (x1_tlMasterClockXingIn_10_a_bits_source), .auto_out_11_a_bits_address (x1_tlMasterClockXingIn_10_a_bits_address), .auto_out_11_a_bits_mask (x1_tlMasterClockXingIn_10_a_bits_mask), .auto_out_11_a_bits_data (x1_tlMasterClockXingIn_10_a_bits_data), .auto_out_11_a_bits_corrupt (x1_tlMasterClockXingIn_10_a_bits_corrupt), .auto_out_11_d_ready (x1_tlMasterClockXingIn_10_d_ready), .auto_out_11_d_valid (x1_tlMasterClockXingIn_10_d_valid), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_opcode (x1_tlMasterClockXingIn_10_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_param (x1_tlMasterClockXingIn_10_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_size (x1_tlMasterClockXingIn_10_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_source (x1_tlMasterClockXingIn_10_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_sink (x1_tlMasterClockXingIn_10_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_denied (x1_tlMasterClockXingIn_10_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_data (x1_tlMasterClockXingIn_10_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_11_d_bits_corrupt (x1_tlMasterClockXingIn_10_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_10_a_ready (x1_tlMasterClockXingIn_9_a_ready), // @[MixedNode.scala:551:17] .auto_out_10_a_valid (x1_tlMasterClockXingIn_9_a_valid), .auto_out_10_a_bits_opcode (x1_tlMasterClockXingIn_9_a_bits_opcode), .auto_out_10_a_bits_param (x1_tlMasterClockXingIn_9_a_bits_param), .auto_out_10_a_bits_size (x1_tlMasterClockXingIn_9_a_bits_size), .auto_out_10_a_bits_source (x1_tlMasterClockXingIn_9_a_bits_source), .auto_out_10_a_bits_address (x1_tlMasterClockXingIn_9_a_bits_address), .auto_out_10_a_bits_mask (x1_tlMasterClockXingIn_9_a_bits_mask), .auto_out_10_a_bits_data (x1_tlMasterClockXingIn_9_a_bits_data), .auto_out_10_a_bits_corrupt (x1_tlMasterClockXingIn_9_a_bits_corrupt), .auto_out_10_d_ready (x1_tlMasterClockXingIn_9_d_ready), .auto_out_10_d_valid (x1_tlMasterClockXingIn_9_d_valid), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_opcode (x1_tlMasterClockXingIn_9_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_param (x1_tlMasterClockXingIn_9_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_size (x1_tlMasterClockXingIn_9_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_source (x1_tlMasterClockXingIn_9_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_sink (x1_tlMasterClockXingIn_9_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_denied (x1_tlMasterClockXingIn_9_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_data (x1_tlMasterClockXingIn_9_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_10_d_bits_corrupt (x1_tlMasterClockXingIn_9_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_9_a_ready (x1_tlMasterClockXingIn_8_a_ready), // @[MixedNode.scala:551:17] .auto_out_9_a_valid (x1_tlMasterClockXingIn_8_a_valid), .auto_out_9_a_bits_opcode (x1_tlMasterClockXingIn_8_a_bits_opcode), .auto_out_9_a_bits_param (x1_tlMasterClockXingIn_8_a_bits_param), .auto_out_9_a_bits_size (x1_tlMasterClockXingIn_8_a_bits_size), .auto_out_9_a_bits_source (x1_tlMasterClockXingIn_8_a_bits_source), .auto_out_9_a_bits_address (x1_tlMasterClockXingIn_8_a_bits_address), .auto_out_9_a_bits_mask (x1_tlMasterClockXingIn_8_a_bits_mask), .auto_out_9_a_bits_data (x1_tlMasterClockXingIn_8_a_bits_data), .auto_out_9_a_bits_corrupt (x1_tlMasterClockXingIn_8_a_bits_corrupt), .auto_out_9_d_ready (x1_tlMasterClockXingIn_8_d_ready), .auto_out_9_d_valid (x1_tlMasterClockXingIn_8_d_valid), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_opcode (x1_tlMasterClockXingIn_8_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_param (x1_tlMasterClockXingIn_8_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_size (x1_tlMasterClockXingIn_8_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_source (x1_tlMasterClockXingIn_8_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_sink (x1_tlMasterClockXingIn_8_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_denied (x1_tlMasterClockXingIn_8_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_data (x1_tlMasterClockXingIn_8_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_9_d_bits_corrupt (x1_tlMasterClockXingIn_8_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_8_a_ready (x1_tlMasterClockXingIn_7_a_ready), // @[MixedNode.scala:551:17] .auto_out_8_a_valid (x1_tlMasterClockXingIn_7_a_valid), .auto_out_8_a_bits_opcode (x1_tlMasterClockXingIn_7_a_bits_opcode), .auto_out_8_a_bits_param (x1_tlMasterClockXingIn_7_a_bits_param), .auto_out_8_a_bits_size (x1_tlMasterClockXingIn_7_a_bits_size), .auto_out_8_a_bits_source (x1_tlMasterClockXingIn_7_a_bits_source), .auto_out_8_a_bits_address (x1_tlMasterClockXingIn_7_a_bits_address), .auto_out_8_a_bits_mask (x1_tlMasterClockXingIn_7_a_bits_mask), .auto_out_8_a_bits_data (x1_tlMasterClockXingIn_7_a_bits_data), .auto_out_8_a_bits_corrupt (x1_tlMasterClockXingIn_7_a_bits_corrupt), .auto_out_8_d_ready (x1_tlMasterClockXingIn_7_d_ready), .auto_out_8_d_valid (x1_tlMasterClockXingIn_7_d_valid), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_opcode (x1_tlMasterClockXingIn_7_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_param (x1_tlMasterClockXingIn_7_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_size (x1_tlMasterClockXingIn_7_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_source (x1_tlMasterClockXingIn_7_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_sink (x1_tlMasterClockXingIn_7_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_denied (x1_tlMasterClockXingIn_7_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_data (x1_tlMasterClockXingIn_7_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_8_d_bits_corrupt (x1_tlMasterClockXingIn_7_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_7_a_ready (x1_tlMasterClockXingIn_6_a_ready), // @[MixedNode.scala:551:17] .auto_out_7_a_valid (x1_tlMasterClockXingIn_6_a_valid), .auto_out_7_a_bits_opcode (x1_tlMasterClockXingIn_6_a_bits_opcode), .auto_out_7_a_bits_param (x1_tlMasterClockXingIn_6_a_bits_param), .auto_out_7_a_bits_size (x1_tlMasterClockXingIn_6_a_bits_size), .auto_out_7_a_bits_source (x1_tlMasterClockXingIn_6_a_bits_source), .auto_out_7_a_bits_address (x1_tlMasterClockXingIn_6_a_bits_address), .auto_out_7_a_bits_mask (x1_tlMasterClockXingIn_6_a_bits_mask), .auto_out_7_a_bits_data (x1_tlMasterClockXingIn_6_a_bits_data), .auto_out_7_a_bits_corrupt (x1_tlMasterClockXingIn_6_a_bits_corrupt), .auto_out_7_d_ready (x1_tlMasterClockXingIn_6_d_ready), .auto_out_7_d_valid (x1_tlMasterClockXingIn_6_d_valid), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_opcode (x1_tlMasterClockXingIn_6_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_param (x1_tlMasterClockXingIn_6_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_size (x1_tlMasterClockXingIn_6_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_source (x1_tlMasterClockXingIn_6_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_sink (x1_tlMasterClockXingIn_6_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_denied (x1_tlMasterClockXingIn_6_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_data (x1_tlMasterClockXingIn_6_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_7_d_bits_corrupt (x1_tlMasterClockXingIn_6_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_6_a_ready (x1_tlMasterClockXingIn_5_a_ready), // @[MixedNode.scala:551:17] .auto_out_6_a_valid (x1_tlMasterClockXingIn_5_a_valid), .auto_out_6_a_bits_opcode (x1_tlMasterClockXingIn_5_a_bits_opcode), .auto_out_6_a_bits_param (x1_tlMasterClockXingIn_5_a_bits_param), .auto_out_6_a_bits_size (x1_tlMasterClockXingIn_5_a_bits_size), .auto_out_6_a_bits_source (x1_tlMasterClockXingIn_5_a_bits_source), .auto_out_6_a_bits_address (x1_tlMasterClockXingIn_5_a_bits_address), .auto_out_6_a_bits_mask (x1_tlMasterClockXingIn_5_a_bits_mask), .auto_out_6_a_bits_data (x1_tlMasterClockXingIn_5_a_bits_data), .auto_out_6_a_bits_corrupt (x1_tlMasterClockXingIn_5_a_bits_corrupt), .auto_out_6_d_ready (x1_tlMasterClockXingIn_5_d_ready), .auto_out_6_d_valid (x1_tlMasterClockXingIn_5_d_valid), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_opcode (x1_tlMasterClockXingIn_5_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_param (x1_tlMasterClockXingIn_5_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_size (x1_tlMasterClockXingIn_5_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_source (x1_tlMasterClockXingIn_5_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_sink (x1_tlMasterClockXingIn_5_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_denied (x1_tlMasterClockXingIn_5_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_data (x1_tlMasterClockXingIn_5_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_6_d_bits_corrupt (x1_tlMasterClockXingIn_5_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_5_a_ready (x1_tlMasterClockXingIn_4_a_ready), // @[MixedNode.scala:551:17] .auto_out_5_a_valid (x1_tlMasterClockXingIn_4_a_valid), .auto_out_5_a_bits_opcode (x1_tlMasterClockXingIn_4_a_bits_opcode), .auto_out_5_a_bits_param (x1_tlMasterClockXingIn_4_a_bits_param), .auto_out_5_a_bits_size (x1_tlMasterClockXingIn_4_a_bits_size), .auto_out_5_a_bits_source (x1_tlMasterClockXingIn_4_a_bits_source), .auto_out_5_a_bits_address (x1_tlMasterClockXingIn_4_a_bits_address), .auto_out_5_a_bits_mask (x1_tlMasterClockXingIn_4_a_bits_mask), .auto_out_5_a_bits_data (x1_tlMasterClockXingIn_4_a_bits_data), .auto_out_5_a_bits_corrupt (x1_tlMasterClockXingIn_4_a_bits_corrupt), .auto_out_5_d_ready (x1_tlMasterClockXingIn_4_d_ready), .auto_out_5_d_valid (x1_tlMasterClockXingIn_4_d_valid), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_opcode (x1_tlMasterClockXingIn_4_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_param (x1_tlMasterClockXingIn_4_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_size (x1_tlMasterClockXingIn_4_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_source (x1_tlMasterClockXingIn_4_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_sink (x1_tlMasterClockXingIn_4_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_denied (x1_tlMasterClockXingIn_4_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_data (x1_tlMasterClockXingIn_4_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_5_d_bits_corrupt (x1_tlMasterClockXingIn_4_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_4_a_ready (x1_tlMasterClockXingIn_3_a_ready), // @[MixedNode.scala:551:17] .auto_out_4_a_valid (x1_tlMasterClockXingIn_3_a_valid), .auto_out_4_a_bits_opcode (x1_tlMasterClockXingIn_3_a_bits_opcode), .auto_out_4_a_bits_param (x1_tlMasterClockXingIn_3_a_bits_param), .auto_out_4_a_bits_size (x1_tlMasterClockXingIn_3_a_bits_size), .auto_out_4_a_bits_source (x1_tlMasterClockXingIn_3_a_bits_source), .auto_out_4_a_bits_address (x1_tlMasterClockXingIn_3_a_bits_address), .auto_out_4_a_bits_mask (x1_tlMasterClockXingIn_3_a_bits_mask), .auto_out_4_a_bits_data (x1_tlMasterClockXingIn_3_a_bits_data), .auto_out_4_a_bits_corrupt (x1_tlMasterClockXingIn_3_a_bits_corrupt), .auto_out_4_d_ready (x1_tlMasterClockXingIn_3_d_ready), .auto_out_4_d_valid (x1_tlMasterClockXingIn_3_d_valid), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_opcode (x1_tlMasterClockXingIn_3_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_param (x1_tlMasterClockXingIn_3_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_size (x1_tlMasterClockXingIn_3_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_source (x1_tlMasterClockXingIn_3_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_sink (x1_tlMasterClockXingIn_3_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_denied (x1_tlMasterClockXingIn_3_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_data (x1_tlMasterClockXingIn_3_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_4_d_bits_corrupt (x1_tlMasterClockXingIn_3_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_3_a_ready (x1_tlMasterClockXingIn_2_a_ready), // @[MixedNode.scala:551:17] .auto_out_3_a_valid (x1_tlMasterClockXingIn_2_a_valid), .auto_out_3_a_bits_opcode (x1_tlMasterClockXingIn_2_a_bits_opcode), .auto_out_3_a_bits_param (x1_tlMasterClockXingIn_2_a_bits_param), .auto_out_3_a_bits_size (x1_tlMasterClockXingIn_2_a_bits_size), .auto_out_3_a_bits_source (x1_tlMasterClockXingIn_2_a_bits_source), .auto_out_3_a_bits_address (x1_tlMasterClockXingIn_2_a_bits_address), .auto_out_3_a_bits_mask (x1_tlMasterClockXingIn_2_a_bits_mask), .auto_out_3_a_bits_data (x1_tlMasterClockXingIn_2_a_bits_data), .auto_out_3_a_bits_corrupt (x1_tlMasterClockXingIn_2_a_bits_corrupt), .auto_out_3_d_ready (x1_tlMasterClockXingIn_2_d_ready), .auto_out_3_d_valid (x1_tlMasterClockXingIn_2_d_valid), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_opcode (x1_tlMasterClockXingIn_2_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_param (x1_tlMasterClockXingIn_2_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_size (x1_tlMasterClockXingIn_2_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_source (x1_tlMasterClockXingIn_2_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_sink (x1_tlMasterClockXingIn_2_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_denied (x1_tlMasterClockXingIn_2_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_data (x1_tlMasterClockXingIn_2_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_3_d_bits_corrupt (x1_tlMasterClockXingIn_2_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_2_a_ready (x1_tlMasterClockXingIn_1_a_ready), // @[MixedNode.scala:551:17] .auto_out_2_a_valid (x1_tlMasterClockXingIn_1_a_valid), .auto_out_2_a_bits_opcode (x1_tlMasterClockXingIn_1_a_bits_opcode), .auto_out_2_a_bits_param (x1_tlMasterClockXingIn_1_a_bits_param), .auto_out_2_a_bits_size (x1_tlMasterClockXingIn_1_a_bits_size), .auto_out_2_a_bits_source (x1_tlMasterClockXingIn_1_a_bits_source), .auto_out_2_a_bits_address (x1_tlMasterClockXingIn_1_a_bits_address), .auto_out_2_a_bits_mask (x1_tlMasterClockXingIn_1_a_bits_mask), .auto_out_2_a_bits_data (x1_tlMasterClockXingIn_1_a_bits_data), .auto_out_2_a_bits_corrupt (x1_tlMasterClockXingIn_1_a_bits_corrupt), .auto_out_2_d_ready (x1_tlMasterClockXingIn_1_d_ready), .auto_out_2_d_valid (x1_tlMasterClockXingIn_1_d_valid), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_opcode (x1_tlMasterClockXingIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_param (x1_tlMasterClockXingIn_1_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_size (x1_tlMasterClockXingIn_1_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_source (x1_tlMasterClockXingIn_1_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_sink (x1_tlMasterClockXingIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_denied (x1_tlMasterClockXingIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_data (x1_tlMasterClockXingIn_1_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_2_d_bits_corrupt (x1_tlMasterClockXingIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_1_a_ready (x1_tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_1_a_valid (x1_tlMasterClockXingIn_a_valid), .auto_out_1_a_bits_opcode (x1_tlMasterClockXingIn_a_bits_opcode), .auto_out_1_a_bits_param (x1_tlMasterClockXingIn_a_bits_param), .auto_out_1_a_bits_size (x1_tlMasterClockXingIn_a_bits_size), .auto_out_1_a_bits_source (x1_tlMasterClockXingIn_a_bits_source), .auto_out_1_a_bits_address (x1_tlMasterClockXingIn_a_bits_address), .auto_out_1_a_bits_mask (x1_tlMasterClockXingIn_a_bits_mask), .auto_out_1_a_bits_data (x1_tlMasterClockXingIn_a_bits_data), .auto_out_1_a_bits_corrupt (x1_tlMasterClockXingIn_a_bits_corrupt), .auto_out_1_d_ready (x1_tlMasterClockXingIn_d_ready), .auto_out_1_d_valid (x1_tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_opcode (x1_tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_param (x1_tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_size (x1_tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_source (x1_tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_sink (x1_tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_denied (x1_tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_data (x1_tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_1_d_bits_corrupt (x1_tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_0_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_0_a_valid (tlMasterClockXingIn_a_valid), .auto_out_0_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode), .auto_out_0_a_bits_param (tlMasterClockXingIn_a_bits_param), .auto_out_0_a_bits_size (tlMasterClockXingIn_a_bits_size), .auto_out_0_a_bits_source (tlMasterClockXingIn_a_bits_source), .auto_out_0_a_bits_address (tlMasterClockXingIn_a_bits_address), .auto_out_0_a_bits_mask (tlMasterClockXingIn_a_bits_mask), .auto_out_0_a_bits_data (tlMasterClockXingIn_a_bits_data), .auto_out_0_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt), .auto_out_0_d_ready (tlMasterClockXingIn_d_ready), .auto_out_0_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_0_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Buffer.scala:75:28] TLBuffer_2 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), .auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_1 intsink_3 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0) ); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_2 intsink_4 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_3 intsink_5 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_1_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_1 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_3_sync_0) ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_4 intsink_6 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_2 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_valid = auto_tl_master_clock_xing_out_18_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_opcode = auto_tl_master_clock_xing_out_18_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_param = auto_tl_master_clock_xing_out_18_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_size = auto_tl_master_clock_xing_out_18_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_source = auto_tl_master_clock_xing_out_18_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_address = auto_tl_master_clock_xing_out_18_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_mask = auto_tl_master_clock_xing_out_18_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_data = auto_tl_master_clock_xing_out_18_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_a_bits_corrupt = auto_tl_master_clock_xing_out_18_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_b_ready = auto_tl_master_clock_xing_out_18_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_valid = auto_tl_master_clock_xing_out_18_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_opcode = auto_tl_master_clock_xing_out_18_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_param = auto_tl_master_clock_xing_out_18_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_size = auto_tl_master_clock_xing_out_18_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_source = auto_tl_master_clock_xing_out_18_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_address = auto_tl_master_clock_xing_out_18_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_data = auto_tl_master_clock_xing_out_18_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_c_bits_corrupt = auto_tl_master_clock_xing_out_18_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_d_ready = auto_tl_master_clock_xing_out_18_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_e_valid = auto_tl_master_clock_xing_out_18_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_18_e_bits_sink = auto_tl_master_clock_xing_out_18_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_valid = auto_tl_master_clock_xing_out_17_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_opcode = auto_tl_master_clock_xing_out_17_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_param = auto_tl_master_clock_xing_out_17_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_size = auto_tl_master_clock_xing_out_17_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_source = auto_tl_master_clock_xing_out_17_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_address = auto_tl_master_clock_xing_out_17_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_mask = auto_tl_master_clock_xing_out_17_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_data = auto_tl_master_clock_xing_out_17_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_a_bits_corrupt = auto_tl_master_clock_xing_out_17_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_17_d_ready = auto_tl_master_clock_xing_out_17_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_valid = auto_tl_master_clock_xing_out_16_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_opcode = auto_tl_master_clock_xing_out_16_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_param = auto_tl_master_clock_xing_out_16_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_size = auto_tl_master_clock_xing_out_16_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_source = auto_tl_master_clock_xing_out_16_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_address = auto_tl_master_clock_xing_out_16_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_mask = auto_tl_master_clock_xing_out_16_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_data = auto_tl_master_clock_xing_out_16_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_a_bits_corrupt = auto_tl_master_clock_xing_out_16_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_16_d_ready = auto_tl_master_clock_xing_out_16_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_valid = auto_tl_master_clock_xing_out_15_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_opcode = auto_tl_master_clock_xing_out_15_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_param = auto_tl_master_clock_xing_out_15_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_size = auto_tl_master_clock_xing_out_15_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_source = auto_tl_master_clock_xing_out_15_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_address = auto_tl_master_clock_xing_out_15_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_mask = auto_tl_master_clock_xing_out_15_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_data = auto_tl_master_clock_xing_out_15_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_a_bits_corrupt = auto_tl_master_clock_xing_out_15_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_15_d_ready = auto_tl_master_clock_xing_out_15_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_valid = auto_tl_master_clock_xing_out_14_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_opcode = auto_tl_master_clock_xing_out_14_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_param = auto_tl_master_clock_xing_out_14_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_size = auto_tl_master_clock_xing_out_14_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_source = auto_tl_master_clock_xing_out_14_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_address = auto_tl_master_clock_xing_out_14_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_mask = auto_tl_master_clock_xing_out_14_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_data = auto_tl_master_clock_xing_out_14_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_a_bits_corrupt = auto_tl_master_clock_xing_out_14_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_14_d_ready = auto_tl_master_clock_xing_out_14_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_valid = auto_tl_master_clock_xing_out_13_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_opcode = auto_tl_master_clock_xing_out_13_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_param = auto_tl_master_clock_xing_out_13_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_size = auto_tl_master_clock_xing_out_13_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_source = auto_tl_master_clock_xing_out_13_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_address = auto_tl_master_clock_xing_out_13_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_mask = auto_tl_master_clock_xing_out_13_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_data = auto_tl_master_clock_xing_out_13_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_a_bits_corrupt = auto_tl_master_clock_xing_out_13_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_13_d_ready = auto_tl_master_clock_xing_out_13_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_valid = auto_tl_master_clock_xing_out_12_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_opcode = auto_tl_master_clock_xing_out_12_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_param = auto_tl_master_clock_xing_out_12_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_size = auto_tl_master_clock_xing_out_12_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_source = auto_tl_master_clock_xing_out_12_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_address = auto_tl_master_clock_xing_out_12_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_mask = auto_tl_master_clock_xing_out_12_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_data = auto_tl_master_clock_xing_out_12_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_a_bits_corrupt = auto_tl_master_clock_xing_out_12_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_12_d_ready = auto_tl_master_clock_xing_out_12_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_valid = auto_tl_master_clock_xing_out_11_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_opcode = auto_tl_master_clock_xing_out_11_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_param = auto_tl_master_clock_xing_out_11_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_size = auto_tl_master_clock_xing_out_11_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_source = auto_tl_master_clock_xing_out_11_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_address = auto_tl_master_clock_xing_out_11_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_mask = auto_tl_master_clock_xing_out_11_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_data = auto_tl_master_clock_xing_out_11_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_a_bits_corrupt = auto_tl_master_clock_xing_out_11_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_11_d_ready = auto_tl_master_clock_xing_out_11_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_valid = auto_tl_master_clock_xing_out_10_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_opcode = auto_tl_master_clock_xing_out_10_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_param = auto_tl_master_clock_xing_out_10_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_size = auto_tl_master_clock_xing_out_10_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_source = auto_tl_master_clock_xing_out_10_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_address = auto_tl_master_clock_xing_out_10_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_mask = auto_tl_master_clock_xing_out_10_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_data = auto_tl_master_clock_xing_out_10_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_a_bits_corrupt = auto_tl_master_clock_xing_out_10_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_10_d_ready = auto_tl_master_clock_xing_out_10_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_valid = auto_tl_master_clock_xing_out_9_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_opcode = auto_tl_master_clock_xing_out_9_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_param = auto_tl_master_clock_xing_out_9_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_size = auto_tl_master_clock_xing_out_9_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_source = auto_tl_master_clock_xing_out_9_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_address = auto_tl_master_clock_xing_out_9_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_mask = auto_tl_master_clock_xing_out_9_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_data = auto_tl_master_clock_xing_out_9_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_a_bits_corrupt = auto_tl_master_clock_xing_out_9_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_9_d_ready = auto_tl_master_clock_xing_out_9_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_valid = auto_tl_master_clock_xing_out_8_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_opcode = auto_tl_master_clock_xing_out_8_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_param = auto_tl_master_clock_xing_out_8_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_size = auto_tl_master_clock_xing_out_8_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_source = auto_tl_master_clock_xing_out_8_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_address = auto_tl_master_clock_xing_out_8_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_mask = auto_tl_master_clock_xing_out_8_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_data = auto_tl_master_clock_xing_out_8_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_a_bits_corrupt = auto_tl_master_clock_xing_out_8_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_8_d_ready = auto_tl_master_clock_xing_out_8_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_valid = auto_tl_master_clock_xing_out_7_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_opcode = auto_tl_master_clock_xing_out_7_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_param = auto_tl_master_clock_xing_out_7_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_size = auto_tl_master_clock_xing_out_7_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_source = auto_tl_master_clock_xing_out_7_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_address = auto_tl_master_clock_xing_out_7_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_mask = auto_tl_master_clock_xing_out_7_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_data = auto_tl_master_clock_xing_out_7_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_a_bits_corrupt = auto_tl_master_clock_xing_out_7_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_7_d_ready = auto_tl_master_clock_xing_out_7_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_valid = auto_tl_master_clock_xing_out_6_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_opcode = auto_tl_master_clock_xing_out_6_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_param = auto_tl_master_clock_xing_out_6_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_size = auto_tl_master_clock_xing_out_6_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_source = auto_tl_master_clock_xing_out_6_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_address = auto_tl_master_clock_xing_out_6_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_mask = auto_tl_master_clock_xing_out_6_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_data = auto_tl_master_clock_xing_out_6_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_a_bits_corrupt = auto_tl_master_clock_xing_out_6_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_6_d_ready = auto_tl_master_clock_xing_out_6_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_valid = auto_tl_master_clock_xing_out_5_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_opcode = auto_tl_master_clock_xing_out_5_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_param = auto_tl_master_clock_xing_out_5_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_size = auto_tl_master_clock_xing_out_5_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_source = auto_tl_master_clock_xing_out_5_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_address = auto_tl_master_clock_xing_out_5_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_mask = auto_tl_master_clock_xing_out_5_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_data = auto_tl_master_clock_xing_out_5_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_a_bits_corrupt = auto_tl_master_clock_xing_out_5_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_5_d_ready = auto_tl_master_clock_xing_out_5_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_valid = auto_tl_master_clock_xing_out_4_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_opcode = auto_tl_master_clock_xing_out_4_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_param = auto_tl_master_clock_xing_out_4_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_size = auto_tl_master_clock_xing_out_4_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_source = auto_tl_master_clock_xing_out_4_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_address = auto_tl_master_clock_xing_out_4_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_mask = auto_tl_master_clock_xing_out_4_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_data = auto_tl_master_clock_xing_out_4_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_a_bits_corrupt = auto_tl_master_clock_xing_out_4_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_4_d_ready = auto_tl_master_clock_xing_out_4_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_valid = auto_tl_master_clock_xing_out_3_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_opcode = auto_tl_master_clock_xing_out_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_param = auto_tl_master_clock_xing_out_3_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_size = auto_tl_master_clock_xing_out_3_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_source = auto_tl_master_clock_xing_out_3_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_address = auto_tl_master_clock_xing_out_3_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_mask = auto_tl_master_clock_xing_out_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_data = auto_tl_master_clock_xing_out_3_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_a_bits_corrupt = auto_tl_master_clock_xing_out_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_3_d_ready = auto_tl_master_clock_xing_out_3_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_valid = auto_tl_master_clock_xing_out_2_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_opcode = auto_tl_master_clock_xing_out_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_param = auto_tl_master_clock_xing_out_2_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_size = auto_tl_master_clock_xing_out_2_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_source = auto_tl_master_clock_xing_out_2_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_address = auto_tl_master_clock_xing_out_2_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_mask = auto_tl_master_clock_xing_out_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_data = auto_tl_master_clock_xing_out_2_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_a_bits_corrupt = auto_tl_master_clock_xing_out_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_2_d_ready = auto_tl_master_clock_xing_out_2_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_valid = auto_tl_master_clock_xing_out_1_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_opcode = auto_tl_master_clock_xing_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_param = auto_tl_master_clock_xing_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_size = auto_tl_master_clock_xing_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_source = auto_tl_master_clock_xing_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_address = auto_tl_master_clock_xing_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_mask = auto_tl_master_clock_xing_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_data = auto_tl_master_clock_xing_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_a_bits_corrupt = auto_tl_master_clock_xing_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_1_d_ready = auto_tl_master_clock_xing_out_1_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_valid = auto_tl_master_clock_xing_out_0_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_opcode = auto_tl_master_clock_xing_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_param = auto_tl_master_clock_xing_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_size = auto_tl_master_clock_xing_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_source = auto_tl_master_clock_xing_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_address = auto_tl_master_clock_xing_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_mask = auto_tl_master_clock_xing_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_data = auto_tl_master_clock_xing_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_a_bits_corrupt = auto_tl_master_clock_xing_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_0_d_ready = auto_tl_master_clock_xing_out_0_d_ready_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module cc_banks_1( // @[DescribedSRAM.scala:17:26] input [12:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [63:0] RW0_wdata, output [63:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_377( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_106( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e5_s11( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ListBuffer.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean) { val queueBits = log2Up(queues) val entryBits = log2Up(entries) } class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle { val index = UInt(params.queueBits.W) val data = Output(params.gen) } class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module { override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}" val io = IO(new Bundle { // push is visible on the same cycle; flow queues val push = Flipped(Decoupled(new ListBufferPush(params))) val valid = UInt(params.queues.W) val pop = Flipped(Valid(UInt(params.queueBits.W))) val data = Output(params.gen) }) val valid = RegInit(0.U(params.queues.W)) val head = Mem(params.queues, UInt(params.entryBits.W)) val tail = Mem(params.queues, UInt(params.entryBits.W)) val used = RegInit(0.U(params.entries.W)) val next = Mem(params.entries, UInt(params.entryBits.W)) val data = Mem(params.entries, params.gen) val freeOH = ~(leftOR(~used) << 1) & ~used val freeIdx = OHToUInt(freeOH) val valid_set = WireDefault(0.U(params.queues.W)) val valid_clr = WireDefault(0.U(params.queues.W)) val used_set = WireDefault(0.U(params.entries.W)) val used_clr = WireDefault(0.U(params.entries.W)) val push_tail = tail.read(io.push.bits.index) val push_valid = valid(io.push.bits.index) io.push.ready := !used.andR when (io.push.fire) { valid_set := UIntToOH(io.push.bits.index, params.queues) used_set := freeOH data.write(freeIdx, io.push.bits.data) when (push_valid) { next.write(push_tail, freeIdx) } .otherwise { head.write(io.push.bits.index, freeIdx) } tail.write(io.push.bits.index, freeIdx) } val pop_head = head.read(io.pop.bits) val pop_valid = valid(io.pop.bits) // Bypass push data to the peek port io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head))) io.valid := (if (!params.bypass) valid else (valid | valid_set)) // It is an error to pop something that is not valid assert (!io.pop.fire || (io.valid)(io.pop.bits)) when (io.pop.fire) { used_clr := UIntToOH(pop_head, params.entries) when (pop_head === tail.read(io.pop.bits)) { valid_clr := UIntToOH(io.pop.bits, params.queues) } head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head))) } // Empty bypass changes no state when ((!params.bypass).B || !io.pop.valid || pop_valid) { used := (used & ~used_clr) | used_set valid := (valid & ~valid_clr) | valid_set } }
module ListBuffer_PutBufferAEntry_q40_e40_2( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input [127:0] io_push_bits_data_data, // @[ListBuffer.scala:39:14] input [15:0] io_push_bits_data_mask, // @[ListBuffer.scala:39:14] input io_push_bits_data_corrupt, // @[ListBuffer.scala:39:14] output [39:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output [127:0] io_data_data, // @[ListBuffer.scala:39:14] output [15:0] io_data_mask, // @[ListBuffer.scala:39:14] output io_data_corrupt // @[ListBuffer.scala:39:14] ); wire [144:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire [127:0] io_push_bits_data_data_0 = io_push_bits_data_data; // @[ListBuffer.scala:36:7] wire [15:0] io_push_bits_data_mask_0 = io_push_bits_data_mask; // @[ListBuffer.scala:36:7] wire io_push_bits_data_corrupt_0 = io_push_bits_data_corrupt; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire [127:0] io_data_data_0; // @[ListBuffer.scala:36:7] wire [15:0] io_data_mask_0; // @[ListBuffer.scala:36:7] wire io_data_corrupt_0; // @[ListBuffer.scala:36:7] wire [39:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [39:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [39:0] used; // @[ListBuffer.scala:50:22] assign io_data_data_0 = _data_ext_R0_data[127:0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_mask_0 = _data_ext_R0_data[143:128]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_corrupt_0 = _data_ext_R0_data[144]; // @[ListBuffer.scala:36:7, :52:18] wire [39:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}] wire [39:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire [39:0] valid_set; // @[ListBuffer.scala:57:30] wire [39:0] valid_clr; // @[ListBuffer.scala:58:30] wire [39:0] used_set; // @[ListBuffer.scala:59:30] wire [39:0] used_clr; // @[ListBuffer.scala:60:30] wire [39:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _valid_set_T_1 = _valid_set_T[39:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 40'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[39:0] : 40'h0; // @[Decoupled.scala:51:35] wire [39:0] _GEN = {34'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [39:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_659; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire [2:0] _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] wire _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] TLMonitor_58 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_in_d_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), // @[AsyncQueue.scala:211:22] .io_in_d_bits_param (_nodeIn_d_sink_io_deq_bits_param), // @[AsyncQueue.scala:211:22] .io_in_d_bits_size (_nodeIn_d_sink_io_deq_bits_size), // @[AsyncQueue.scala:211:22] .io_in_d_bits_source (_nodeIn_d_sink_io_deq_bits_source), // @[AsyncQueue.scala:211:22] .io_in_d_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), // @[AsyncQueue.scala:211:22] .io_in_d_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), // @[AsyncQueue.scala:211:22] .io_in_d_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt) // @[AsyncQueue.scala:211:22] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_source_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_data (auto_in_a_bits_data), .io_async_mem_0_opcode (auto_out_a_mem_0_opcode), .io_async_mem_0_address (auto_out_a_mem_0_address), .io_async_mem_0_data (auto_out_a_mem_0_data), .io_async_ridx (auto_out_a_ridx), .io_async_widx (auto_out_a_widx), .io_async_safe_ridx_valid (auto_out_a_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_a_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_a_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_a_safe_sink_reset_n) ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_sink_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_sink_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_sink_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_sink_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt), .io_async_mem_0_opcode (auto_out_d_mem_0_opcode), .io_async_mem_0_size (auto_out_d_mem_0_size), .io_async_mem_0_source (auto_out_d_mem_0_source), .io_async_mem_0_data (auto_out_d_mem_0_data), .io_async_ridx (auto_out_d_ridx), .io_async_widx (auto_out_d_widx), .io_async_safe_ridx_valid (auto_out_d_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_d_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_d_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] assign auto_in_d_valid = _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_opcode = _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_param = _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_size = _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_source = _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_sink = _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_denied = _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_corrupt = _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_55( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_79 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PMA.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters} class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val paddr = Input(UInt()) val resp = Output(new Bundle { val cacheable = Bool() val r = Bool() val w = Bool() val pp = Bool() val al = Bool() val aa = Bool() val x = Bool() val eff = Bool() }) }) // PMA // check exist a slave can consume this address. val legal_address = manager.findSafe(io.paddr).reduce(_||_) // check utility to help check SoC property. def fastCheck(member: TLManagerParameters => Boolean) = legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B) io.resp.cacheable := fastCheck(_.supportsAcquireB) io.resp.r := fastCheck(_.supportsGet) io.resp.w := fastCheck(_.supportsPutFull) io.resp.pp := fastCheck(_.supportsPutPartial) io.resp.al := fastCheck(_.supportsLogical) io.resp.aa := fastCheck(_.supportsArithmetic) io.resp.x := fastCheck(_.executable) io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module PMAChecker_3( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_22 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_25; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_43; // @[PMA.scala:39:19] wire _io_resp_pp_T_43; // @[PMA.scala:39:19] wire _io_resp_al_T_43; // @[PMA.scala:39:19] wire _io_resp_aa_T_43; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31] assign _io_resp_w_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31] assign _io_resp_pp_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31] assign _io_resp_al_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31] assign _io_resp_aa_T_35 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_11; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_11 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_45 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000040}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000080}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_55 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h80000C0}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_60 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000100}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46] wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_65 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000140}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46] wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_70 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000180}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46] wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_75 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h80001C0}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFF01C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46] wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31] assign _legal_address_T_80 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46] wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_85; // @[Parameters.scala:137:31] assign _legal_address_T_85 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_86 = {1'h0, _legal_address_T_85}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_87 = _legal_address_T_86 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_88 = _legal_address_T_87; // @[Parameters.scala:137:46] wire _legal_address_T_89 = _legal_address_T_88 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_17 = _legal_address_T_89; // @[Parameters.scala:612:40] wire [39:0] _GEN_8 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_90; // @[Parameters.scala:137:31] assign _legal_address_T_90 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_16; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_16 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_91 = {1'h0, _legal_address_T_90}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_92 = _legal_address_T_91 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_93 = _legal_address_T_92; // @[Parameters.scala:137:46] wire _legal_address_T_94 = _legal_address_T_93 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_18 = _legal_address_T_94; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_95 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000040}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_96 = {1'h0, _legal_address_T_95}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_97 = _legal_address_T_96 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_98 = _legal_address_T_97; // @[Parameters.scala:137:46] wire _legal_address_T_99 = _legal_address_T_98 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_19 = _legal_address_T_99; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_100 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000080}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_101 = {1'h0, _legal_address_T_100}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_102 = _legal_address_T_101 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_103 = _legal_address_T_102; // @[Parameters.scala:137:46] wire _legal_address_T_104 = _legal_address_T_103 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_20 = _legal_address_T_104; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_105 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h800000C0}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_106 = {1'h0, _legal_address_T_105}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_107 = _legal_address_T_106 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_108 = _legal_address_T_107; // @[Parameters.scala:137:46] wire _legal_address_T_109 = _legal_address_T_108 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_21 = _legal_address_T_109; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_110 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000100}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_111 = {1'h0, _legal_address_T_110}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_112 = _legal_address_T_111 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_113 = _legal_address_T_112; // @[Parameters.scala:137:46] wire _legal_address_T_114 = _legal_address_T_113 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_22 = _legal_address_T_114; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_115 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000140}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_116 = {1'h0, _legal_address_T_115}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_117 = _legal_address_T_116 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_118 = _legal_address_T_117; // @[Parameters.scala:137:46] wire _legal_address_T_119 = _legal_address_T_118 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_23 = _legal_address_T_119; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_120 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000180}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_121 = {1'h0, _legal_address_T_120}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_122 = _legal_address_T_121 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_123 = _legal_address_T_122; // @[Parameters.scala:137:46] wire _legal_address_T_124 = _legal_address_T_123 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_24 = _legal_address_T_124; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_125 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h800001C0}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_126 = {1'h0, _legal_address_T_125}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_127 = _legal_address_T_126 & 41'h1FFF00001C0; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_128 = _legal_address_T_127; // @[Parameters.scala:137:46] wire _legal_address_T_129 = _legal_address_T_128 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_25 = _legal_address_T_129; // @[Parameters.scala:612:40] wire _legal_address_T_130 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_131 = _legal_address_T_130 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_132 = _legal_address_T_131 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_133 = _legal_address_T_132 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_134 = _legal_address_T_133 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_135 = _legal_address_T_134 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_136 = _legal_address_T_135 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_137 = _legal_address_T_136 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_138 = _legal_address_T_137 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_139 = _legal_address_T_138 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire _legal_address_T_140 = _legal_address_T_139 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] wire _legal_address_T_141 = _legal_address_T_140 | _legal_address_WIRE_12; // @[Parameters.scala:612:40] wire _legal_address_T_142 = _legal_address_T_141 | _legal_address_WIRE_13; // @[Parameters.scala:612:40] wire _legal_address_T_143 = _legal_address_T_142 | _legal_address_WIRE_14; // @[Parameters.scala:612:40] wire _legal_address_T_144 = _legal_address_T_143 | _legal_address_WIRE_15; // @[Parameters.scala:612:40] wire _legal_address_T_145 = _legal_address_T_144 | _legal_address_WIRE_16; // @[Parameters.scala:612:40] wire _legal_address_T_146 = _legal_address_T_145 | _legal_address_WIRE_17; // @[Parameters.scala:612:40] wire _legal_address_T_147 = _legal_address_T_146 | _legal_address_WIRE_18; // @[Parameters.scala:612:40] wire _legal_address_T_148 = _legal_address_T_147 | _legal_address_WIRE_19; // @[Parameters.scala:612:40] wire _legal_address_T_149 = _legal_address_T_148 | _legal_address_WIRE_20; // @[Parameters.scala:612:40] wire _legal_address_T_150 = _legal_address_T_149 | _legal_address_WIRE_21; // @[Parameters.scala:612:40] wire _legal_address_T_151 = _legal_address_T_150 | _legal_address_WIRE_22; // @[Parameters.scala:612:40] wire _legal_address_T_152 = _legal_address_T_151 | _legal_address_WIRE_23; // @[Parameters.scala:612:40] wire _legal_address_T_153 = _legal_address_T_152 | _legal_address_WIRE_24; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_153 | _legal_address_WIRE_25; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_10 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_12 = {1'h0, _io_resp_cacheable_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_17 = {1'h0, _io_resp_cacheable_T_16}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_20; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_23 = _io_resp_cacheable_T_21; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_24; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_25 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_25; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_30 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_31 = _io_resp_w_T_30 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_32 = _io_resp_w_T_31 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_33 = _io_resp_w_T_32 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_34 = _io_resp_w_T_33 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46] wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_42 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_42; // @[Mux.scala:30:73] assign _io_resp_w_T_43 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_43; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_30 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_31 = _io_resp_pp_T_30 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_32 = _io_resp_pp_T_31 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_33 = _io_resp_pp_T_32 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_42 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_42; // @[Mux.scala:30:73] assign _io_resp_pp_T_43 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_43; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_30 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_31 = _io_resp_al_T_30 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_32 = _io_resp_al_T_31 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_33 = _io_resp_al_T_32 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_34 = _io_resp_al_T_33 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46] wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_42 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_42; // @[Mux.scala:30:73] assign _io_resp_al_T_43 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_43; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hF7FF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFE0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_30 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_31 = _io_resp_aa_T_30 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_32 = _io_resp_aa_T_31 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_33 = _io_resp_aa_T_32 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_42 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_42; // @[Mux.scala:30:73] assign _io_resp_aa_T_43 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_43; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFEE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [39:0] _io_resp_eff_T_35 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h2000}; // @[PMA.scala:18:7] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'hFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'hF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_275( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_511 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [5:0] _io_schedule_bits_b_bits_clients_T = 6'h3F; // @[MSHR.scala:289:53] wire [5:0] _last_probe_T_1 = 6'h3F; // @[MSHR.scala:459:66] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [5:0] excluded_client = 6'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [5:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_3( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File annotations.scala: // See LICENSE for license details. package midas.targetutils import chisel3.{ dontTouch, fromBooleanToLiteral, when, Bits, Bool, Clock, Data, MemBase, Module, Printable, RegNext, Reset, UInt, Wire, WireDefault, } import chisel3.printf.Printf import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation} import firrtl.RenameMap import firrtl.annotations.{ Annotation, ComponentName, HasSerializationHints, InstanceTarget, ModuleTarget, ReferenceTarget, SingleTargetAnnotation, } /** These are consumed by [[midas.passes.AutoILATransform]] to directly instantiate an ILA at the top of simulator's * design hierarchy (the PlatformShim level). */ case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation { def toFirrtl = FirrtlFpgaDebugAnnotation(target.toNamed) } case class FirrtlFpgaDebugAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] { def duplicate(n: ComponentName) = this.copy(target = n) } object FpgaDebug { def apply(targets: Data*): Unit = { targets.foreach { requireIsHardware(_, "Target passed to FpgaDebug:") } targets.map({ t => annotate(FpgaDebugAnnotation(t)) }) } } private[midas] class ReferenceTargetRenamer(renames: RenameMap) { // TODO: determine order for multiple renames, or just check of == 1 rename? def exactRename(rt: ReferenceTarget): ReferenceTarget = { val renameMatches = renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) assert( renameMatches.length <= 1, s"${rt} should be renamed exactly once (or not at all). Suggested renames: ${renameMatches}", ) renameMatches.headOption.getOrElse(rt) } def apply(rt: ReferenceTarget): Seq[ReferenceTarget] = { renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) } } private[midas] case class SynthPrintfAnnotation( target: ReferenceTarget ) extends firrtl.annotations.SingleTargetAnnotation[ReferenceTarget] { def duplicate(newTarget: ReferenceTarget) = this.copy(newTarget) } object SynthesizePrintf { /** Annotates a chisel printf as a candidate for synthesis. The printf is only synthesized if Printf synthesis is * enabled in Golden Gate. * * See: https://docs.fires.im/en/stable/search.html?q=Printf+Synthesis&check_keywords=yes&area=default * * @param printf * The printf statement to be synthesized. * * @return * The original input, so that this annotator may be applied inline if desired. */ def apply(printf: Printf): Printf = { annotate(new ChiselAnnotation { def toFirrtl = SynthPrintfAnnotation(printf.toTarget) }) printf } private def generateAnnotations(format: String, args: Seq[Bits], name: Option[String]): Printable = { Module.currentModule.getOrElse(throw new RuntimeException("Cannot annotate a printf outside of a Module")) // To preserve the behavior of the printf parameter annotator, generate a // secondary printf and annotate that, instead of the user's printf, which // will be given an empty string. This will be removed with the apply methods in 1.15. val printf = SynthesizePrintf(chisel3.printf(Printable.pack(format, args: _*))) name.foreach { n => printf.suggestName(n) } Printable.pack("") } /** Annotates* a printf by intercepting the parameters to a chisel printf, and returning a printable. As a side * effect, this function generates a ChiselSynthPrintfAnnotation with the format string and references to each of the * args. * * *Note: this isn't actually annotating the statement but instead the arguments. This is a vestige from earlier * versions of chisel / firrtl in which print statements were unnamed, and thus not referenceable from annotations. * * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(format: String, args: Bits*): Printable = generateAnnotations(format, args, None) /** Like the other apply method, but provides an optional name which can be used by synthesized hardware / bridge. * Generally, users deploy the nameless form. * * @param name * A descriptive name for this printf instance. * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(name: String, format: String, args: Bits*): Printable = generateAnnotations(format, args, Some(name)) } /** A mixed-in ancestor trait for all FAME annotations, useful for type-casing. */ trait FAMEAnnotation { this: Annotation => } /** This labels an instance so that it is extracted as a separate FAME model. */ case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlFAMEModelAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlFAMEModelAnnotation(parent.instOf(target.instanceName, target.name)) } } case class FirrtlFAMEModelAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This specifies that the module should be automatically multi-threaded (Chisel annotator). */ case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name)) } } /** This specifies that the module should be automatically multi-threaded (FIRRTL annotation). */ case class FirrtlEnableModelMultiThreadingAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This labels a target Mem so that it is extracted and replaced with a separate model. */ case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation { def toFirrtl = FirrtlMemModelAnnotation(target.toNamed.toTarget) } case class FirrtlMemModelAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] { def duplicate(rt: ReferenceTarget) = this.copy(target = rt) } case class ExcludeInstanceAssertsAnnotation(target: (String, String)) extends firrtl.annotations.NoTargetAnnotation { def duplicate(n: (String, String)) = this.copy(target = n) } // TODO: Actually use a real target and not strings. object ExcludeInstanceAsserts { def apply(target: (String, String)): ChiselAnnotation = new ChiselAnnotation { def toFirrtl = ExcludeInstanceAssertsAnnotation(target) } } sealed trait PerfCounterOpType object PerfCounterOps { /** Takes the annotated UInt and adds it to an accumulation register generated in the bridge */ case object Accumulate extends PerfCounterOpType /** Takes the annotated UInt and exposes it directly to the driver NB: Fields longer than 64b are not supported, and * must be divided into smaller segments that are sepearate annotated */ case object Identity extends PerfCounterOpType } /** AutoCounter annotations. Do not emit the FIRRTL annotations unless you are writing a target transformation, use the * Chisel-side [[PerfCounter]] object instead. */ case class AutoCounterFirrtlAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: ReferenceTarget, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, coverGenerated: Boolean = false, ) extends firrtl.annotations.Annotation with HasSerializationHints { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = renamer.exactRename(reset) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } // The AutoCounter tranform will reject this annotation if it's not enclosed def shouldBeIncluded(modList: Seq[String]): Boolean = !coverGenerated || modList.contains(target.module) def enclosingModule(): String = target.module def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, enclosingModule()) def typeHints: Seq[Class[_]] = Seq(opType.getClass) } case class AutoCounterCoverModuleFirrtlAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation { def duplicate(n: ModuleTarget) = this.copy(target = n) } case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation { def toFirrtl = AutoCounterCoverModuleFirrtlAnnotation(target) } object PerfCounter { private def emitAnnotation( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType, ): Unit = { requireIsHardware(target, "Target passed to PerfCounter:") requireIsHardware(clock, "Clock passed to PerfCounter:") requireIsHardware(reset, "Reset passed to PerfCounter:") annotate(new ChiselAnnotation { def toFirrtl = AutoCounterFirrtlAnnotation(target.toTarget, clock.toTarget, reset.toTarget, label, description, opType) }) } /** Labels a signal as an event for which an host-side counter (an "AutoCounter") should be generated). Events can be * multi-bit to encode multiple occurances in a cycle (e.g., the number of instructions retired in a superscalar * processor). NB: Golden Gate will not generate the coutner unless AutoCounter is enabled in your the platform * config. See the docs.fires.im for end-to-end usage information. * * @param target * The number of occurances of the event (in the current cycle) * * @param clock * The clock to which this event is sychronized. * * @param reset * If the event is asserted while under the provide reset, it is not counted. TODO: This should be made optional. * * @param label * A verilog-friendly identifier for the event signal * * @param description * A human-friendly description of the event. * * @param opType * Defines how the bridge should be aggregated into a performance counter. */ def apply( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, ): Unit = emitAnnotation(target, clock, reset, label, description, opType) /** A simplified variation of the full apply method above that uses the implicit clock and reset. */ def apply(target: UInt, label: String, description: String): Unit = emitAnnotation(target, Module.clock, Module.reset, label, description, PerfCounterOps.Accumulate) /** Passes the annotated UInt through to the driver without accumulation. Use cases: * - Custom accumulation / counting logic not supported by the driver * - Providing runtime metadata along side standard accumulation registers * * Note: Under reset, the passthrough value is set to 0. This keeps event handling uniform in the transform. */ def identity(target: UInt, label: String, description: String): Unit = { require( target.getWidth <= 64, s"""|PerfCounter.identity can only accept fields <= 64b wide. Provided target for label: | $label |was ${target.getWidth}b.""".stripMargin, ) emitAnnotation(target, Module.clock, Module.reset, label, description, opType = PerfCounterOps.Identity) } } case class PlusArgFirrtlAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } object PlusArg { private def emitAnnotation( target: BaseModule ): Unit = { annotate(new ChiselAnnotation { def toFirrtl = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) PlusArgFirrtlAnnotation(parent.instOf(target.instanceName, target.name)) } }) } /** Labels a Rocket Chip 'plusarg_reader' module to synthesize. Must be of the type found in * https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/PlusArg.scala * * @param target * The 'plusarg_reader' module to synthesize */ def apply(target: BaseModule): Unit = { emitAnnotation(target) } } // Need serialization utils to be upstreamed to FIRRTL before i can use these. //sealed trait TriggerSourceType //case object Credit extends TriggerSourceType //case object Debit extends TriggerSourceType case class TriggerSourceAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: Option[ReferenceTarget], sourceType: Boolean, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = reset.map(renamer.exactRename) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } case class TriggerSinkAnnotation( target: ReferenceTarget, clock: ReferenceTarget, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) Seq(this.copy(target = renamedTarget, clock = renamedClock)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) } object TriggerSource { private def annotateTrigger(tpe: Boolean)(target: Bool, reset: Option[Bool]): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val clock = WireDefault(Module.clock) reset.map(dontTouch.apply) requireIsHardware(target, "Target passed to TriggerSource:") reset.foreach { requireIsHardware(_, "Reset passed to TriggerSource:") } annotate(new ChiselAnnotation { def toFirrtl = TriggerSourceAnnotation(target.toNamed.toTarget, clock.toNamed.toTarget, reset.map(_.toTarget), tpe) }) } def annotateCredit = annotateTrigger(true) _ def annotateDebit = annotateTrigger(false) _ /** Methods to annotate a Boolean as a trigger credit or debit. Credits and debits issued while the module's implicit * reset is asserted are not counted. */ def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool)) def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool)) def apply(creditSig: Bool, debitSig: Bool): Unit = { credit(creditSig) debit(debitSig) } /** Variations of the above methods that count credits and debits provided while the implicit reset is asserted. */ def creditEvenUnderReset(credit: Bool): Unit = annotateCredit(credit, None) def debitEvenUnderReset(debit: Bool): Unit = annotateDebit(debit, None) def evenUnderReset(creditSig: Bool, debitSig: Bool): Unit = { creditEvenUnderReset(creditSig) debitEvenUnderReset(debitSig) } /** Level sensitive trigger sources. Implemented using [[credit]] and [[debit]]. Note: This generated hardware in your * target design. * * @param src * Enables the trigger when asserted. If no other credits have been issued since (e.g., a second level-sensitive * enable was asserted), the trigger is disabled when src is desasserted. */ def levelSensitiveEnable(src: Bool): Unit = { val srcLast = RegNext(src) credit(src && !srcLast) debit(!src && srcLast) } } object TriggerSink { /** Marks a bool as receiving the global trigger signal. * * @param target * A Bool node that will be driven with the trigger * * @param noSourceDefault * The value that the trigger signal should take on if no trigger soruces are found in the target. This is a * temporary parameter required while this apply method generates a wire. Otherwise this can be punted to the * target's RTL. */ def apply(target: Bool, noSourceDefault: => Bool = true.B): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val targetWire = WireDefault(noSourceDefault) val clock = Module.clock target := targetWire // Both the provided node and the generated one need to be dontTouched to stop // constProp from optimizing the down stream logic(?) dontTouch(target) annotate(new ChiselAnnotation { def toFirrtl = TriggerSinkAnnotation(targetWire.toTarget, clock.toTarget) }) } /** Syntatic sugar for a when context that is predicated by a trigger sink. Example usage: * {{{ * TriggerSink.whenEnabled { * printf(<...>) * } * }}} * * @param noSourceDefault * See [[TriggerSink.apply]]. */ def whenEnabled(noSourceDefault: => Bool = true.B)(elaborator: => Unit): Unit = { val sinkEnable = Wire(Bool()) apply(sinkEnable, noSourceDefault) when(sinkEnable) { elaborator } } } case class RoCCBusyFirrtlAnnotation( target: ReferenceTarget, ready: ReferenceTarget, valid: ReferenceTarget, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedReady = renamer.exactRename(ready) val renamedValid = renamer.exactRename(valid) val renamedTarget = renamer.exactRename(target) Seq(this.copy(target = renamedTarget, ready = renamedReady, valid = renamedValid)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } object MakeRoCCBusyLatencyInsensitive { def apply( target: Bool, ready: Bool, valid: Bool, ): Unit = { requireIsHardware(target, "Target passed to ..:") requireIsHardware(ready, "Ready passed to ..:") requireIsHardware(valid, "Valid passed to ..:") annotate(new ChiselAnnotation { def toFirrtl = RoCCBusyFirrtlAnnotation(target.toNamed.toTarget, ready.toNamed.toTarget, valid.toNamed.toTarget) }) } } case class FirrtlPartWrapperParentAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } case class FirrtlPortToNeighborRouterIdxAnno( target: ReferenceTarget, extractNeighborIdx: Int, removeNeighborIdx: Int, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } case class FirrtlCombLogicInsideModuleAnno( target: ReferenceTarget ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } File XactTracker.scala: package gemmini import chisel3._ import chisel3.util._ import gemmini.Util.UDValid import midas.targetutils.SynthesizePrintf class XactTrackerEntry[U <: Data](maxShift: Int, spadWidth: Int, accWidth: Int, spadRows: Int, accRows: Int, maxReqBytes: Int, mvin_scale_t_bits: Int, nCmds: Int) extends Bundle { val shift = UInt(log2Up(maxShift).W) val addr = UInt(log2Up(spadRows max accRows).W) val is_acc = Bool() val accumulate = Bool() val has_acc_bitwidth = Bool() val scale = UInt(mvin_scale_t_bits.W) val repeats = UInt(16.W) // TODO magic number val pixel_repeats = UInt(8.W) // TODO magic number val len = UInt(16.W) // TODO magic number val block_stride = UInt(16.W) // TODO magic number val spad_row_offset = UInt(log2Up(spadWidth max accWidth).W) val lg_len_req = UInt(log2Up(log2Up(maxReqBytes+1)+1).W) val bytes_to_read = UInt(log2Up(maxReqBytes+1).W) val cmd_id = UInt(log2Up(nCmds).W) } class XactTrackerAllocIO[U <: Data](nXacts: Int, maxShift: Int, spadWidth: Int, accWidth :Int, spadRows: Int, accRows: Int, maxReqBytes: Int, mvin_scale_t_bits: Int, nCmds: Int) extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val xactid = Input(UInt(log2Up(nXacts).W)) val entry = Output(new XactTrackerEntry(maxShift, spadWidth, accWidth, spadRows, accRows, maxReqBytes, mvin_scale_t_bits, nCmds)) def fire(dummy: Int = 0) = valid && ready } class XactTrackerPeekIO[U <: Data](val nXacts: Int, val maxShift: Int, val spadWidth: Int, val accWidth: Int, val spadRows: Int, val accRows: Int, val maxReqBytes: Int, mvin_scale_t_bits: Int, nCmds: Int) extends Bundle { val xactid = Input(UInt(log2Up(nXacts).W)) val pop = Input(Bool()) val entry = Output(new XactTrackerEntry(maxShift, spadWidth, accWidth, spadRows, accRows, maxReqBytes, mvin_scale_t_bits, nCmds)) } /* maxShift: the maximum number of bytes in the beginning of a TileLink response which may be discarded spadWidth: the width of an spad row in bytes spadRows: the total number of rows in the spad maxReqBytes: Removed: maxMatrices: the maximum number of rows from different matrices which can be packed into one request */ class XactTracker[U <: Data](nXacts: Int, maxShift: Int, spadWidth: Int, accWidth: Int, spadRows: Int, accRows: Int, maxReqBytes: Int, mvin_scale_t_bits: Int, nCmds: Int, use_firesim_simulation_counters: Boolean) extends Module { val io = IO(new Bundle { val alloc = Flipped(new XactTrackerAllocIO(nXacts, maxShift, spadWidth, accWidth, spadRows, accRows, maxReqBytes, mvin_scale_t_bits, nCmds)) val peek = new XactTrackerPeekIO(nXacts, maxShift, spadWidth, accWidth, spadRows, accRows, maxReqBytes, mvin_scale_t_bits, nCmds) val busy = Output(Bool()) val counter = new CounterEventIO() }) val entries = Reg(Vec(nXacts, UDValid(new XactTrackerEntry(maxShift, spadWidth, accWidth, spadRows, accRows, maxReqBytes, mvin_scale_t_bits, nCmds)))) val free_entry = MuxCase((nXacts-1).U, entries.zipWithIndex.map { case (e, i) => !e.valid -> i.U }) io.alloc.ready := !entries.map(_.valid).reduce(_ && _) io.alloc.xactid := free_entry io.peek.entry := entries(io.peek.xactid).bits io.busy := entries.map(_.valid).reduce(_ || _) when (io.alloc.fire()) { entries(free_entry).valid := true.B entries(free_entry).bits := io.alloc.entry } when (io.peek.pop) { entries(io.peek.xactid).valid := false.B assert(entries(io.peek.xactid).valid) } when (reset.asBool) { entries.foreach(_.valid := false.B) } // Performance counters CounterEventIO.init(io.counter) val total_latency = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W)) when (io.counter.external_reset) { total_latency := 0.U }.otherwise { total_latency := total_latency + PopCount(entries.map(_.valid)) } io.counter.connectExternalCounter(CounterExternal.RDMA_TOTAL_LATENCY, total_latency) if (use_firesim_simulation_counters) { val cntr = Counter(500000) when(cntr.inc()) { printf(SynthesizePrintf("RDMA total latency: %d\n", total_latency)) } } }
module XactTracker( // @[XactTracker.scala:56:7] input clock, // @[XactTracker.scala:56:7] input reset, // @[XactTracker.scala:56:7] input io_alloc_valid, // @[XactTracker.scala:59:14] output io_alloc_ready, // @[XactTracker.scala:59:14] output [5:0] io_alloc_xactid, // @[XactTracker.scala:59:14] input [5:0] io_alloc_entry_shift, // @[XactTracker.scala:59:14] input [13:0] io_alloc_entry_addr, // @[XactTracker.scala:59:14] input io_alloc_entry_is_acc, // @[XactTracker.scala:59:14] input io_alloc_entry_accumulate, // @[XactTracker.scala:59:14] input io_alloc_entry_has_acc_bitwidth, // @[XactTracker.scala:59:14] input [31:0] io_alloc_entry_scale, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_repeats, // @[XactTracker.scala:59:14] input [7:0] io_alloc_entry_pixel_repeats, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_len, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_block_stride, // @[XactTracker.scala:59:14] input [8:0] io_alloc_entry_spad_row_offset, // @[XactTracker.scala:59:14] input [6:0] io_alloc_entry_bytes_to_read, // @[XactTracker.scala:59:14] input [2:0] io_alloc_entry_cmd_id, // @[XactTracker.scala:59:14] input [5:0] io_peek_xactid, // @[XactTracker.scala:59:14] input io_peek_pop, // @[XactTracker.scala:59:14] output [5:0] io_peek_entry_shift, // @[XactTracker.scala:59:14] output [13:0] io_peek_entry_addr, // @[XactTracker.scala:59:14] output io_peek_entry_is_acc, // @[XactTracker.scala:59:14] output io_peek_entry_accumulate, // @[XactTracker.scala:59:14] output io_peek_entry_has_acc_bitwidth, // @[XactTracker.scala:59:14] output [31:0] io_peek_entry_scale, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_repeats, // @[XactTracker.scala:59:14] output [7:0] io_peek_entry_pixel_repeats, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_len, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_block_stride, // @[XactTracker.scala:59:14] output [8:0] io_peek_entry_spad_row_offset, // @[XactTracker.scala:59:14] output [6:0] io_peek_entry_bytes_to_read, // @[XactTracker.scala:59:14] output [2:0] io_peek_entry_cmd_id, // @[XactTracker.scala:59:14] output io_busy, // @[XactTracker.scala:59:14] output [31:0] io_counter_external_values_6, // @[XactTracker.scala:59:14] input io_counter_external_reset // @[XactTracker.scala:59:14] ); wire io_alloc_valid_0 = io_alloc_valid; // @[XactTracker.scala:56:7] wire [5:0] io_alloc_entry_shift_0 = io_alloc_entry_shift; // @[XactTracker.scala:56:7] wire [13:0] io_alloc_entry_addr_0 = io_alloc_entry_addr; // @[XactTracker.scala:56:7] wire io_alloc_entry_is_acc_0 = io_alloc_entry_is_acc; // @[XactTracker.scala:56:7] wire io_alloc_entry_accumulate_0 = io_alloc_entry_accumulate; // @[XactTracker.scala:56:7] wire io_alloc_entry_has_acc_bitwidth_0 = io_alloc_entry_has_acc_bitwidth; // @[XactTracker.scala:56:7] wire [31:0] io_alloc_entry_scale_0 = io_alloc_entry_scale; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_repeats_0 = io_alloc_entry_repeats; // @[XactTracker.scala:56:7] wire [7:0] io_alloc_entry_pixel_repeats_0 = io_alloc_entry_pixel_repeats; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_len_0 = io_alloc_entry_len; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_block_stride_0 = io_alloc_entry_block_stride; // @[XactTracker.scala:56:7] wire [8:0] io_alloc_entry_spad_row_offset_0 = io_alloc_entry_spad_row_offset; // @[XactTracker.scala:56:7] wire [6:0] io_alloc_entry_bytes_to_read_0 = io_alloc_entry_bytes_to_read; // @[XactTracker.scala:56:7] wire [2:0] io_alloc_entry_cmd_id_0 = io_alloc_entry_cmd_id; // @[XactTracker.scala:56:7] wire [5:0] io_peek_xactid_0 = io_peek_xactid; // @[XactTracker.scala:56:7] wire io_peek_pop_0 = io_peek_pop; // @[XactTracker.scala:56:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[XactTracker.scala:56:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire [2:0] io_alloc_entry_lg_len_req = 3'h0; // @[XactTracker.scala:56:7] wire [2:0] io_peek_entry_lg_len_req = 3'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_0 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_1 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_2 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_3 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_4 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_5 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_6 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_7 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_8 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_9 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_10 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_11 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_12 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_13 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_14 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_15 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_16 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_17 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_18 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_19 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_20 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_21 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_22 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_23 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_24 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_25 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_26 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_27 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_28 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_29 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_30 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_31 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_32 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_33 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_34 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_35 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_36 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_37 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_38 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_39 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_40 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_41 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_42 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_43 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_44 = 1'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_0 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[XactTracker.scala:56:7] wire [5:0] _free_entry_T_64 = 6'h3F; // @[Mux.scala:126:16] wire _io_alloc_ready_T_63; // @[XactTracker.scala:70:21] wire [5:0] free_entry; // @[Mux.scala:126:16] wire _io_busy_T_62; // @[XactTracker.scala:75:44] wire io_alloc_ready_0; // @[XactTracker.scala:56:7] wire [5:0] io_alloc_xactid_0; // @[XactTracker.scala:56:7] wire [5:0] io_peek_entry_shift_0; // @[XactTracker.scala:56:7] wire [13:0] io_peek_entry_addr_0; // @[XactTracker.scala:56:7] wire io_peek_entry_is_acc_0; // @[XactTracker.scala:56:7] wire io_peek_entry_accumulate_0; // @[XactTracker.scala:56:7] wire io_peek_entry_has_acc_bitwidth_0; // @[XactTracker.scala:56:7] wire [31:0] io_peek_entry_scale_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_repeats_0; // @[XactTracker.scala:56:7] wire [7:0] io_peek_entry_pixel_repeats_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_len_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_block_stride_0; // @[XactTracker.scala:56:7] wire [8:0] io_peek_entry_spad_row_offset_0; // @[XactTracker.scala:56:7] wire [6:0] io_peek_entry_bytes_to_read_0; // @[XactTracker.scala:56:7] wire [2:0] io_peek_entry_cmd_id_0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_6_0; // @[XactTracker.scala:56:7] wire io_busy_0; // @[XactTracker.scala:56:7] reg entries_0_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_0_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_0_bits_addr; // @[XactTracker.scala:67:20] reg entries_0_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_0_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_0_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_0_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_0_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_0_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_0_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_0_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_1_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_1_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_1_bits_addr; // @[XactTracker.scala:67:20] reg entries_1_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_1_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_1_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_1_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_1_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_1_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_1_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_1_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_2_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_2_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_2_bits_addr; // @[XactTracker.scala:67:20] reg entries_2_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_2_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_2_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_2_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_2_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_2_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_2_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_2_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_3_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_3_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_3_bits_addr; // @[XactTracker.scala:67:20] reg entries_3_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_3_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_3_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_3_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_3_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_3_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_3_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_3_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_4_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_4_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_4_bits_addr; // @[XactTracker.scala:67:20] reg entries_4_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_4_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_4_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_4_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_4_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_4_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_4_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_4_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_5_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_5_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_5_bits_addr; // @[XactTracker.scala:67:20] reg entries_5_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_5_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_5_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_5_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_5_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_5_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_5_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_5_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_6_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_6_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_6_bits_addr; // @[XactTracker.scala:67:20] reg entries_6_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_6_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_6_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_6_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_6_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_6_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_6_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_6_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_7_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_7_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_7_bits_addr; // @[XactTracker.scala:67:20] reg entries_7_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_7_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_7_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_7_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_7_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_7_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_7_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_7_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_8_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_8_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_8_bits_addr; // @[XactTracker.scala:67:20] reg entries_8_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_8_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_8_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_8_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_8_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_8_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_8_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_8_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_9_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_9_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_9_bits_addr; // @[XactTracker.scala:67:20] reg entries_9_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_9_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_9_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_9_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_9_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_9_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_9_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_9_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_10_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_10_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_10_bits_addr; // @[XactTracker.scala:67:20] reg entries_10_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_10_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_10_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_10_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_10_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_10_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_10_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_10_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_11_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_11_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_11_bits_addr; // @[XactTracker.scala:67:20] reg entries_11_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_11_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_11_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_11_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_11_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_11_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_11_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_11_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_12_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_12_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_12_bits_addr; // @[XactTracker.scala:67:20] reg entries_12_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_12_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_12_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_12_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_12_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_12_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_12_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_12_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_13_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_13_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_13_bits_addr; // @[XactTracker.scala:67:20] reg entries_13_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_13_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_13_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_13_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_13_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_13_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_13_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_13_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_14_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_14_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_14_bits_addr; // @[XactTracker.scala:67:20] reg entries_14_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_14_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_14_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_14_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_14_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_14_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_14_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_14_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_15_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_15_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_15_bits_addr; // @[XactTracker.scala:67:20] reg entries_15_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_15_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_15_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_15_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_15_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_15_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_15_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_15_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_16_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_16_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_16_bits_addr; // @[XactTracker.scala:67:20] reg entries_16_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_16_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_16_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_16_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_16_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_16_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_16_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_16_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_16_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_16_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_16_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_17_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_17_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_17_bits_addr; // @[XactTracker.scala:67:20] reg entries_17_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_17_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_17_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_17_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_17_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_17_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_17_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_17_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_17_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_17_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_17_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_18_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_18_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_18_bits_addr; // @[XactTracker.scala:67:20] reg entries_18_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_18_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_18_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_18_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_18_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_18_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_18_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_18_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_18_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_18_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_18_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_19_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_19_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_19_bits_addr; // @[XactTracker.scala:67:20] reg entries_19_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_19_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_19_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_19_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_19_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_19_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_19_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_19_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_19_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_19_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_19_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_20_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_20_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_20_bits_addr; // @[XactTracker.scala:67:20] reg entries_20_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_20_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_20_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_20_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_20_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_20_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_20_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_20_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_20_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_20_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_20_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_21_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_21_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_21_bits_addr; // @[XactTracker.scala:67:20] reg entries_21_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_21_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_21_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_21_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_21_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_21_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_21_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_21_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_21_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_21_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_21_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_22_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_22_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_22_bits_addr; // @[XactTracker.scala:67:20] reg entries_22_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_22_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_22_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_22_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_22_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_22_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_22_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_22_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_22_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_22_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_22_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_23_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_23_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_23_bits_addr; // @[XactTracker.scala:67:20] reg entries_23_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_23_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_23_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_23_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_23_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_23_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_23_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_23_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_23_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_23_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_23_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_24_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_24_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_24_bits_addr; // @[XactTracker.scala:67:20] reg entries_24_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_24_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_24_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_24_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_24_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_24_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_24_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_24_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_24_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_24_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_24_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_25_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_25_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_25_bits_addr; // @[XactTracker.scala:67:20] reg entries_25_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_25_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_25_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_25_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_25_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_25_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_25_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_25_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_25_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_25_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_25_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_26_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_26_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_26_bits_addr; // @[XactTracker.scala:67:20] reg entries_26_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_26_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_26_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_26_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_26_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_26_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_26_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_26_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_26_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_26_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_26_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_27_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_27_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_27_bits_addr; // @[XactTracker.scala:67:20] reg entries_27_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_27_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_27_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_27_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_27_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_27_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_27_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_27_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_27_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_27_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_27_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_28_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_28_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_28_bits_addr; // @[XactTracker.scala:67:20] reg entries_28_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_28_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_28_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_28_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_28_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_28_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_28_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_28_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_28_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_28_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_28_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_29_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_29_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_29_bits_addr; // @[XactTracker.scala:67:20] reg entries_29_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_29_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_29_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_29_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_29_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_29_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_29_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_29_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_29_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_29_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_29_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_30_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_30_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_30_bits_addr; // @[XactTracker.scala:67:20] reg entries_30_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_30_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_30_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_30_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_30_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_30_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_30_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_30_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_30_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_30_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_30_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_31_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_31_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_31_bits_addr; // @[XactTracker.scala:67:20] reg entries_31_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_31_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_31_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_31_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_31_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_31_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_31_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_31_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_31_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_31_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_31_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_32_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_32_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_32_bits_addr; // @[XactTracker.scala:67:20] reg entries_32_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_32_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_32_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_32_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_32_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_32_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_32_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_32_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_32_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_32_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_32_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_33_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_33_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_33_bits_addr; // @[XactTracker.scala:67:20] reg entries_33_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_33_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_33_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_33_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_33_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_33_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_33_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_33_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_33_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_33_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_33_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_34_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_34_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_34_bits_addr; // @[XactTracker.scala:67:20] reg entries_34_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_34_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_34_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_34_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_34_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_34_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_34_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_34_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_34_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_34_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_34_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_35_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_35_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_35_bits_addr; // @[XactTracker.scala:67:20] reg entries_35_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_35_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_35_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_35_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_35_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_35_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_35_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_35_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_35_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_35_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_35_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_36_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_36_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_36_bits_addr; // @[XactTracker.scala:67:20] reg entries_36_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_36_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_36_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_36_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_36_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_36_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_36_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_36_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_36_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_36_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_36_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_37_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_37_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_37_bits_addr; // @[XactTracker.scala:67:20] reg entries_37_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_37_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_37_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_37_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_37_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_37_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_37_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_37_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_37_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_37_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_37_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_38_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_38_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_38_bits_addr; // @[XactTracker.scala:67:20] reg entries_38_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_38_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_38_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_38_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_38_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_38_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_38_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_38_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_38_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_38_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_38_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_39_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_39_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_39_bits_addr; // @[XactTracker.scala:67:20] reg entries_39_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_39_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_39_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_39_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_39_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_39_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_39_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_39_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_39_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_39_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_39_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_40_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_40_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_40_bits_addr; // @[XactTracker.scala:67:20] reg entries_40_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_40_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_40_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_40_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_40_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_40_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_40_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_40_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_40_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_40_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_40_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_41_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_41_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_41_bits_addr; // @[XactTracker.scala:67:20] reg entries_41_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_41_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_41_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_41_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_41_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_41_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_41_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_41_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_41_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_41_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_41_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_42_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_42_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_42_bits_addr; // @[XactTracker.scala:67:20] reg entries_42_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_42_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_42_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_42_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_42_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_42_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_42_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_42_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_42_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_42_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_42_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_43_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_43_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_43_bits_addr; // @[XactTracker.scala:67:20] reg entries_43_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_43_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_43_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_43_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_43_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_43_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_43_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_43_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_43_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_43_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_43_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_44_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_44_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_44_bits_addr; // @[XactTracker.scala:67:20] reg entries_44_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_44_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_44_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_44_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_44_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_44_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_44_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_44_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_44_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_44_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_44_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_45_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_45_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_45_bits_addr; // @[XactTracker.scala:67:20] reg entries_45_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_45_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_45_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_45_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_45_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_45_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_45_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_45_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_45_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_45_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_45_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_46_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_46_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_46_bits_addr; // @[XactTracker.scala:67:20] reg entries_46_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_46_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_46_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_46_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_46_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_46_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_46_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_46_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_46_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_46_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_46_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_47_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_47_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_47_bits_addr; // @[XactTracker.scala:67:20] reg entries_47_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_47_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_47_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_47_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_47_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_47_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_47_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_47_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_47_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_47_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_47_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_48_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_48_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_48_bits_addr; // @[XactTracker.scala:67:20] reg entries_48_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_48_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_48_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_48_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_48_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_48_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_48_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_48_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_48_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_48_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_48_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_49_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_49_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_49_bits_addr; // @[XactTracker.scala:67:20] reg entries_49_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_49_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_49_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_49_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_49_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_49_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_49_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_49_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_49_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_49_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_49_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_50_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_50_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_50_bits_addr; // @[XactTracker.scala:67:20] reg entries_50_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_50_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_50_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_50_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_50_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_50_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_50_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_50_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_50_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_50_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_50_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_51_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_51_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_51_bits_addr; // @[XactTracker.scala:67:20] reg entries_51_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_51_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_51_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_51_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_51_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_51_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_51_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_51_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_51_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_51_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_51_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_52_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_52_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_52_bits_addr; // @[XactTracker.scala:67:20] reg entries_52_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_52_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_52_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_52_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_52_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_52_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_52_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_52_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_52_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_52_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_52_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_53_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_53_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_53_bits_addr; // @[XactTracker.scala:67:20] reg entries_53_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_53_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_53_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_53_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_53_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_53_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_53_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_53_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_53_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_53_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_53_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_54_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_54_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_54_bits_addr; // @[XactTracker.scala:67:20] reg entries_54_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_54_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_54_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_54_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_54_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_54_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_54_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_54_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_54_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_54_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_54_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_55_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_55_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_55_bits_addr; // @[XactTracker.scala:67:20] reg entries_55_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_55_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_55_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_55_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_55_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_55_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_55_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_55_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_55_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_55_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_55_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_56_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_56_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_56_bits_addr; // @[XactTracker.scala:67:20] reg entries_56_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_56_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_56_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_56_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_56_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_56_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_56_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_56_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_56_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_56_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_56_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_57_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_57_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_57_bits_addr; // @[XactTracker.scala:67:20] reg entries_57_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_57_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_57_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_57_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_57_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_57_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_57_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_57_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_57_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_57_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_57_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_58_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_58_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_58_bits_addr; // @[XactTracker.scala:67:20] reg entries_58_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_58_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_58_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_58_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_58_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_58_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_58_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_58_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_58_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_58_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_58_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_59_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_59_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_59_bits_addr; // @[XactTracker.scala:67:20] reg entries_59_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_59_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_59_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_59_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_59_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_59_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_59_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_59_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_59_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_59_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_59_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_60_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_60_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_60_bits_addr; // @[XactTracker.scala:67:20] reg entries_60_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_60_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_60_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_60_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_60_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_60_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_60_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_60_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_60_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_60_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_60_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_61_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_61_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_61_bits_addr; // @[XactTracker.scala:67:20] reg entries_61_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_61_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_61_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_61_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_61_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_61_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_61_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_61_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_61_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_61_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_61_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_62_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_62_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_62_bits_addr; // @[XactTracker.scala:67:20] reg entries_62_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_62_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_62_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_62_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_62_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_62_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_62_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_62_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_62_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_62_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_62_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_63_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_63_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_63_bits_addr; // @[XactTracker.scala:67:20] reg entries_63_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_63_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_63_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_63_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_63_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_63_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_63_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_63_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_63_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_63_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg [2:0] entries_63_bits_cmd_id; // @[XactTracker.scala:67:20] wire _free_entry_T = ~entries_0_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_1 = ~entries_1_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_2 = ~entries_2_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_3 = ~entries_3_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_4 = ~entries_4_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_5 = ~entries_5_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_6 = ~entries_6_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_7 = ~entries_7_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_8 = ~entries_8_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_9 = ~entries_9_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_10 = ~entries_10_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_11 = ~entries_11_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_12 = ~entries_12_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_13 = ~entries_13_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_14 = ~entries_14_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_15 = ~entries_15_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_16 = ~entries_16_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_17 = ~entries_17_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_18 = ~entries_18_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_19 = ~entries_19_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_20 = ~entries_20_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_21 = ~entries_21_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_22 = ~entries_22_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_23 = ~entries_23_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_24 = ~entries_24_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_25 = ~entries_25_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_26 = ~entries_26_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_27 = ~entries_27_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_28 = ~entries_28_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_29 = ~entries_29_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_30 = ~entries_30_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_31 = ~entries_31_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_32 = ~entries_32_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_33 = ~entries_33_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_34 = ~entries_34_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_35 = ~entries_35_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_36 = ~entries_36_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_37 = ~entries_37_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_38 = ~entries_38_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_39 = ~entries_39_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_40 = ~entries_40_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_41 = ~entries_41_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_42 = ~entries_42_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_43 = ~entries_43_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_44 = ~entries_44_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_45 = ~entries_45_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_46 = ~entries_46_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_47 = ~entries_47_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_48 = ~entries_48_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_49 = ~entries_49_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_50 = ~entries_50_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_51 = ~entries_51_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_52 = ~entries_52_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_53 = ~entries_53_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_54 = ~entries_54_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_55 = ~entries_55_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_56 = ~entries_56_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_57 = ~entries_57_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_58 = ~entries_58_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_59 = ~entries_59_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_60 = ~entries_60_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_61 = ~entries_61_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_62 = ~entries_62_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_63 = ~entries_63_valid; // @[XactTracker.scala:67:20, :69:84] wire [5:0] _free_entry_T_65 = {5'h1F, ~_free_entry_T_62}; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_66 = _free_entry_T_61 ? 6'h3D : _free_entry_T_65; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_67 = _free_entry_T_60 ? 6'h3C : _free_entry_T_66; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_68 = _free_entry_T_59 ? 6'h3B : _free_entry_T_67; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_69 = _free_entry_T_58 ? 6'h3A : _free_entry_T_68; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_70 = _free_entry_T_57 ? 6'h39 : _free_entry_T_69; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_71 = _free_entry_T_56 ? 6'h38 : _free_entry_T_70; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_72 = _free_entry_T_55 ? 6'h37 : _free_entry_T_71; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_73 = _free_entry_T_54 ? 6'h36 : _free_entry_T_72; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_74 = _free_entry_T_53 ? 6'h35 : _free_entry_T_73; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_75 = _free_entry_T_52 ? 6'h34 : _free_entry_T_74; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_76 = _free_entry_T_51 ? 6'h33 : _free_entry_T_75; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_77 = _free_entry_T_50 ? 6'h32 : _free_entry_T_76; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_78 = _free_entry_T_49 ? 6'h31 : _free_entry_T_77; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_79 = _free_entry_T_48 ? 6'h30 : _free_entry_T_78; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_80 = _free_entry_T_47 ? 6'h2F : _free_entry_T_79; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_81 = _free_entry_T_46 ? 6'h2E : _free_entry_T_80; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_82 = _free_entry_T_45 ? 6'h2D : _free_entry_T_81; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_83 = _free_entry_T_44 ? 6'h2C : _free_entry_T_82; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_84 = _free_entry_T_43 ? 6'h2B : _free_entry_T_83; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_85 = _free_entry_T_42 ? 6'h2A : _free_entry_T_84; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_86 = _free_entry_T_41 ? 6'h29 : _free_entry_T_85; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_87 = _free_entry_T_40 ? 6'h28 : _free_entry_T_86; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_88 = _free_entry_T_39 ? 6'h27 : _free_entry_T_87; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_89 = _free_entry_T_38 ? 6'h26 : _free_entry_T_88; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_90 = _free_entry_T_37 ? 6'h25 : _free_entry_T_89; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_91 = _free_entry_T_36 ? 6'h24 : _free_entry_T_90; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_92 = _free_entry_T_35 ? 6'h23 : _free_entry_T_91; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_93 = _free_entry_T_34 ? 6'h22 : _free_entry_T_92; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_94 = _free_entry_T_33 ? 6'h21 : _free_entry_T_93; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_95 = _free_entry_T_32 ? 6'h20 : _free_entry_T_94; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_96 = _free_entry_T_31 ? 6'h1F : _free_entry_T_95; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_97 = _free_entry_T_30 ? 6'h1E : _free_entry_T_96; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_98 = _free_entry_T_29 ? 6'h1D : _free_entry_T_97; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_99 = _free_entry_T_28 ? 6'h1C : _free_entry_T_98; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_100 = _free_entry_T_27 ? 6'h1B : _free_entry_T_99; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_101 = _free_entry_T_26 ? 6'h1A : _free_entry_T_100; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_102 = _free_entry_T_25 ? 6'h19 : _free_entry_T_101; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_103 = _free_entry_T_24 ? 6'h18 : _free_entry_T_102; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_104 = _free_entry_T_23 ? 6'h17 : _free_entry_T_103; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_105 = _free_entry_T_22 ? 6'h16 : _free_entry_T_104; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_106 = _free_entry_T_21 ? 6'h15 : _free_entry_T_105; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_107 = _free_entry_T_20 ? 6'h14 : _free_entry_T_106; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_108 = _free_entry_T_19 ? 6'h13 : _free_entry_T_107; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_109 = _free_entry_T_18 ? 6'h12 : _free_entry_T_108; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_110 = _free_entry_T_17 ? 6'h11 : _free_entry_T_109; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_111 = _free_entry_T_16 ? 6'h10 : _free_entry_T_110; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_112 = _free_entry_T_15 ? 6'hF : _free_entry_T_111; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_113 = _free_entry_T_14 ? 6'hE : _free_entry_T_112; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_114 = _free_entry_T_13 ? 6'hD : _free_entry_T_113; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_115 = _free_entry_T_12 ? 6'hC : _free_entry_T_114; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_116 = _free_entry_T_11 ? 6'hB : _free_entry_T_115; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_117 = _free_entry_T_10 ? 6'hA : _free_entry_T_116; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_118 = _free_entry_T_9 ? 6'h9 : _free_entry_T_117; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_119 = _free_entry_T_8 ? 6'h8 : _free_entry_T_118; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_120 = _free_entry_T_7 ? 6'h7 : _free_entry_T_119; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_121 = _free_entry_T_6 ? 6'h6 : _free_entry_T_120; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_122 = _free_entry_T_5 ? 6'h5 : _free_entry_T_121; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_123 = _free_entry_T_4 ? 6'h4 : _free_entry_T_122; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_124 = _free_entry_T_3 ? 6'h3 : _free_entry_T_123; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_125 = _free_entry_T_2 ? 6'h2 : _free_entry_T_124; // @[Mux.scala:126:16] wire [5:0] _free_entry_T_126 = _free_entry_T_1 ? 6'h1 : _free_entry_T_125; // @[Mux.scala:126:16] assign free_entry = _free_entry_T ? 6'h0 : _free_entry_T_126; // @[Mux.scala:126:16] assign io_alloc_xactid_0 = free_entry; // @[Mux.scala:126:16] wire _io_alloc_ready_T = entries_0_valid & entries_1_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_1 = _io_alloc_ready_T & entries_2_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_2 = _io_alloc_ready_T_1 & entries_3_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_3 = _io_alloc_ready_T_2 & entries_4_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_4 = _io_alloc_ready_T_3 & entries_5_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_5 = _io_alloc_ready_T_4 & entries_6_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_6 = _io_alloc_ready_T_5 & entries_7_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_7 = _io_alloc_ready_T_6 & entries_8_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_8 = _io_alloc_ready_T_7 & entries_9_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_9 = _io_alloc_ready_T_8 & entries_10_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_10 = _io_alloc_ready_T_9 & entries_11_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_11 = _io_alloc_ready_T_10 & entries_12_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_12 = _io_alloc_ready_T_11 & entries_13_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_13 = _io_alloc_ready_T_12 & entries_14_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_14 = _io_alloc_ready_T_13 & entries_15_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_15 = _io_alloc_ready_T_14 & entries_16_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_16 = _io_alloc_ready_T_15 & entries_17_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_17 = _io_alloc_ready_T_16 & entries_18_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_18 = _io_alloc_ready_T_17 & entries_19_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_19 = _io_alloc_ready_T_18 & entries_20_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_20 = _io_alloc_ready_T_19 & entries_21_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_21 = _io_alloc_ready_T_20 & entries_22_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_22 = _io_alloc_ready_T_21 & entries_23_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_23 = _io_alloc_ready_T_22 & entries_24_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_24 = _io_alloc_ready_T_23 & entries_25_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_25 = _io_alloc_ready_T_24 & entries_26_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_26 = _io_alloc_ready_T_25 & entries_27_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_27 = _io_alloc_ready_T_26 & entries_28_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_28 = _io_alloc_ready_T_27 & entries_29_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_29 = _io_alloc_ready_T_28 & entries_30_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_30 = _io_alloc_ready_T_29 & entries_31_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_31 = _io_alloc_ready_T_30 & entries_32_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_32 = _io_alloc_ready_T_31 & entries_33_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_33 = _io_alloc_ready_T_32 & entries_34_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_34 = _io_alloc_ready_T_33 & entries_35_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_35 = _io_alloc_ready_T_34 & entries_36_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_36 = _io_alloc_ready_T_35 & entries_37_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_37 = _io_alloc_ready_T_36 & entries_38_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_38 = _io_alloc_ready_T_37 & entries_39_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_39 = _io_alloc_ready_T_38 & entries_40_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_40 = _io_alloc_ready_T_39 & entries_41_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_41 = _io_alloc_ready_T_40 & entries_42_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_42 = _io_alloc_ready_T_41 & entries_43_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_43 = _io_alloc_ready_T_42 & entries_44_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_44 = _io_alloc_ready_T_43 & entries_45_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_45 = _io_alloc_ready_T_44 & entries_46_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_46 = _io_alloc_ready_T_45 & entries_47_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_47 = _io_alloc_ready_T_46 & entries_48_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_48 = _io_alloc_ready_T_47 & entries_49_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_49 = _io_alloc_ready_T_48 & entries_50_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_50 = _io_alloc_ready_T_49 & entries_51_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_51 = _io_alloc_ready_T_50 & entries_52_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_52 = _io_alloc_ready_T_51 & entries_53_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_53 = _io_alloc_ready_T_52 & entries_54_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_54 = _io_alloc_ready_T_53 & entries_55_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_55 = _io_alloc_ready_T_54 & entries_56_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_56 = _io_alloc_ready_T_55 & entries_57_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_57 = _io_alloc_ready_T_56 & entries_58_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_58 = _io_alloc_ready_T_57 & entries_59_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_59 = _io_alloc_ready_T_58 & entries_60_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_60 = _io_alloc_ready_T_59 & entries_61_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_61 = _io_alloc_ready_T_60 & entries_62_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_62 = _io_alloc_ready_T_61 & entries_63_valid; // @[XactTracker.scala:67:20, :70:52] assign _io_alloc_ready_T_63 = ~_io_alloc_ready_T_62; // @[XactTracker.scala:70:{21,52}] assign io_alloc_ready_0 = _io_alloc_ready_T_63; // @[XactTracker.scala:56:7, :70:21] wire [63:0] _GEN = {{entries_63_valid}, {entries_62_valid}, {entries_61_valid}, {entries_60_valid}, {entries_59_valid}, {entries_58_valid}, {entries_57_valid}, {entries_56_valid}, {entries_55_valid}, {entries_54_valid}, {entries_53_valid}, {entries_52_valid}, {entries_51_valid}, {entries_50_valid}, {entries_49_valid}, {entries_48_valid}, {entries_47_valid}, {entries_46_valid}, {entries_45_valid}, {entries_44_valid}, {entries_43_valid}, {entries_42_valid}, {entries_41_valid}, {entries_40_valid}, {entries_39_valid}, {entries_38_valid}, {entries_37_valid}, {entries_36_valid}, {entries_35_valid}, {entries_34_valid}, {entries_33_valid}, {entries_32_valid}, {entries_31_valid}, {entries_30_valid}, {entries_29_valid}, {entries_28_valid}, {entries_27_valid}, {entries_26_valid}, {entries_25_valid}, {entries_24_valid}, {entries_23_valid}, {entries_22_valid}, {entries_21_valid}, {entries_20_valid}, {entries_19_valid}, {entries_18_valid}, {entries_17_valid}, {entries_16_valid}, {entries_15_valid}, {entries_14_valid}, {entries_13_valid}, {entries_12_valid}, {entries_11_valid}, {entries_10_valid}, {entries_9_valid}, {entries_8_valid}, {entries_7_valid}, {entries_6_valid}, {entries_5_valid}, {entries_4_valid}, {entries_3_valid}, {entries_2_valid}, {entries_1_valid}, {entries_0_valid}}; // @[XactTracker.scala:67:20, :73:17] wire [63:0][5:0] _GEN_0 = {{entries_63_bits_shift}, {entries_62_bits_shift}, {entries_61_bits_shift}, {entries_60_bits_shift}, {entries_59_bits_shift}, {entries_58_bits_shift}, {entries_57_bits_shift}, {entries_56_bits_shift}, {entries_55_bits_shift}, {entries_54_bits_shift}, {entries_53_bits_shift}, {entries_52_bits_shift}, {entries_51_bits_shift}, {entries_50_bits_shift}, {entries_49_bits_shift}, {entries_48_bits_shift}, {entries_47_bits_shift}, {entries_46_bits_shift}, {entries_45_bits_shift}, {entries_44_bits_shift}, {entries_43_bits_shift}, {entries_42_bits_shift}, {entries_41_bits_shift}, {entries_40_bits_shift}, {entries_39_bits_shift}, {entries_38_bits_shift}, {entries_37_bits_shift}, {entries_36_bits_shift}, {entries_35_bits_shift}, {entries_34_bits_shift}, {entries_33_bits_shift}, {entries_32_bits_shift}, {entries_31_bits_shift}, {entries_30_bits_shift}, {entries_29_bits_shift}, {entries_28_bits_shift}, {entries_27_bits_shift}, {entries_26_bits_shift}, {entries_25_bits_shift}, {entries_24_bits_shift}, {entries_23_bits_shift}, {entries_22_bits_shift}, {entries_21_bits_shift}, {entries_20_bits_shift}, {entries_19_bits_shift}, {entries_18_bits_shift}, {entries_17_bits_shift}, {entries_16_bits_shift}, {entries_15_bits_shift}, {entries_14_bits_shift}, {entries_13_bits_shift}, {entries_12_bits_shift}, {entries_11_bits_shift}, {entries_10_bits_shift}, {entries_9_bits_shift}, {entries_8_bits_shift}, {entries_7_bits_shift}, {entries_6_bits_shift}, {entries_5_bits_shift}, {entries_4_bits_shift}, {entries_3_bits_shift}, {entries_2_bits_shift}, {entries_1_bits_shift}, {entries_0_bits_shift}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_shift_0 = _GEN_0[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][13:0] _GEN_1 = {{entries_63_bits_addr}, {entries_62_bits_addr}, {entries_61_bits_addr}, {entries_60_bits_addr}, {entries_59_bits_addr}, {entries_58_bits_addr}, {entries_57_bits_addr}, {entries_56_bits_addr}, {entries_55_bits_addr}, {entries_54_bits_addr}, {entries_53_bits_addr}, {entries_52_bits_addr}, {entries_51_bits_addr}, {entries_50_bits_addr}, {entries_49_bits_addr}, {entries_48_bits_addr}, {entries_47_bits_addr}, {entries_46_bits_addr}, {entries_45_bits_addr}, {entries_44_bits_addr}, {entries_43_bits_addr}, {entries_42_bits_addr}, {entries_41_bits_addr}, {entries_40_bits_addr}, {entries_39_bits_addr}, {entries_38_bits_addr}, {entries_37_bits_addr}, {entries_36_bits_addr}, {entries_35_bits_addr}, {entries_34_bits_addr}, {entries_33_bits_addr}, {entries_32_bits_addr}, {entries_31_bits_addr}, {entries_30_bits_addr}, {entries_29_bits_addr}, {entries_28_bits_addr}, {entries_27_bits_addr}, {entries_26_bits_addr}, {entries_25_bits_addr}, {entries_24_bits_addr}, {entries_23_bits_addr}, {entries_22_bits_addr}, {entries_21_bits_addr}, {entries_20_bits_addr}, {entries_19_bits_addr}, {entries_18_bits_addr}, {entries_17_bits_addr}, {entries_16_bits_addr}, {entries_15_bits_addr}, {entries_14_bits_addr}, {entries_13_bits_addr}, {entries_12_bits_addr}, {entries_11_bits_addr}, {entries_10_bits_addr}, {entries_9_bits_addr}, {entries_8_bits_addr}, {entries_7_bits_addr}, {entries_6_bits_addr}, {entries_5_bits_addr}, {entries_4_bits_addr}, {entries_3_bits_addr}, {entries_2_bits_addr}, {entries_1_bits_addr}, {entries_0_bits_addr}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_addr_0 = _GEN_1[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0] _GEN_2 = {{entries_63_bits_is_acc}, {entries_62_bits_is_acc}, {entries_61_bits_is_acc}, {entries_60_bits_is_acc}, {entries_59_bits_is_acc}, {entries_58_bits_is_acc}, {entries_57_bits_is_acc}, {entries_56_bits_is_acc}, {entries_55_bits_is_acc}, {entries_54_bits_is_acc}, {entries_53_bits_is_acc}, {entries_52_bits_is_acc}, {entries_51_bits_is_acc}, {entries_50_bits_is_acc}, {entries_49_bits_is_acc}, {entries_48_bits_is_acc}, {entries_47_bits_is_acc}, {entries_46_bits_is_acc}, {entries_45_bits_is_acc}, {entries_44_bits_is_acc}, {entries_43_bits_is_acc}, {entries_42_bits_is_acc}, {entries_41_bits_is_acc}, {entries_40_bits_is_acc}, {entries_39_bits_is_acc}, {entries_38_bits_is_acc}, {entries_37_bits_is_acc}, {entries_36_bits_is_acc}, {entries_35_bits_is_acc}, {entries_34_bits_is_acc}, {entries_33_bits_is_acc}, {entries_32_bits_is_acc}, {entries_31_bits_is_acc}, {entries_30_bits_is_acc}, {entries_29_bits_is_acc}, {entries_28_bits_is_acc}, {entries_27_bits_is_acc}, {entries_26_bits_is_acc}, {entries_25_bits_is_acc}, {entries_24_bits_is_acc}, {entries_23_bits_is_acc}, {entries_22_bits_is_acc}, {entries_21_bits_is_acc}, {entries_20_bits_is_acc}, {entries_19_bits_is_acc}, {entries_18_bits_is_acc}, {entries_17_bits_is_acc}, {entries_16_bits_is_acc}, {entries_15_bits_is_acc}, {entries_14_bits_is_acc}, {entries_13_bits_is_acc}, {entries_12_bits_is_acc}, {entries_11_bits_is_acc}, {entries_10_bits_is_acc}, {entries_9_bits_is_acc}, {entries_8_bits_is_acc}, {entries_7_bits_is_acc}, {entries_6_bits_is_acc}, {entries_5_bits_is_acc}, {entries_4_bits_is_acc}, {entries_3_bits_is_acc}, {entries_2_bits_is_acc}, {entries_1_bits_is_acc}, {entries_0_bits_is_acc}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_is_acc_0 = _GEN_2[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0] _GEN_3 = {{entries_63_bits_accumulate}, {entries_62_bits_accumulate}, {entries_61_bits_accumulate}, {entries_60_bits_accumulate}, {entries_59_bits_accumulate}, {entries_58_bits_accumulate}, {entries_57_bits_accumulate}, {entries_56_bits_accumulate}, {entries_55_bits_accumulate}, {entries_54_bits_accumulate}, {entries_53_bits_accumulate}, {entries_52_bits_accumulate}, {entries_51_bits_accumulate}, {entries_50_bits_accumulate}, {entries_49_bits_accumulate}, {entries_48_bits_accumulate}, {entries_47_bits_accumulate}, {entries_46_bits_accumulate}, {entries_45_bits_accumulate}, {entries_44_bits_accumulate}, {entries_43_bits_accumulate}, {entries_42_bits_accumulate}, {entries_41_bits_accumulate}, {entries_40_bits_accumulate}, {entries_39_bits_accumulate}, {entries_38_bits_accumulate}, {entries_37_bits_accumulate}, {entries_36_bits_accumulate}, {entries_35_bits_accumulate}, {entries_34_bits_accumulate}, {entries_33_bits_accumulate}, {entries_32_bits_accumulate}, {entries_31_bits_accumulate}, {entries_30_bits_accumulate}, {entries_29_bits_accumulate}, {entries_28_bits_accumulate}, {entries_27_bits_accumulate}, {entries_26_bits_accumulate}, {entries_25_bits_accumulate}, {entries_24_bits_accumulate}, {entries_23_bits_accumulate}, {entries_22_bits_accumulate}, {entries_21_bits_accumulate}, {entries_20_bits_accumulate}, {entries_19_bits_accumulate}, {entries_18_bits_accumulate}, {entries_17_bits_accumulate}, {entries_16_bits_accumulate}, {entries_15_bits_accumulate}, {entries_14_bits_accumulate}, {entries_13_bits_accumulate}, {entries_12_bits_accumulate}, {entries_11_bits_accumulate}, {entries_10_bits_accumulate}, {entries_9_bits_accumulate}, {entries_8_bits_accumulate}, {entries_7_bits_accumulate}, {entries_6_bits_accumulate}, {entries_5_bits_accumulate}, {entries_4_bits_accumulate}, {entries_3_bits_accumulate}, {entries_2_bits_accumulate}, {entries_1_bits_accumulate}, {entries_0_bits_accumulate}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_accumulate_0 = _GEN_3[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0] _GEN_4 = {{entries_63_bits_has_acc_bitwidth}, {entries_62_bits_has_acc_bitwidth}, {entries_61_bits_has_acc_bitwidth}, {entries_60_bits_has_acc_bitwidth}, {entries_59_bits_has_acc_bitwidth}, {entries_58_bits_has_acc_bitwidth}, {entries_57_bits_has_acc_bitwidth}, {entries_56_bits_has_acc_bitwidth}, {entries_55_bits_has_acc_bitwidth}, {entries_54_bits_has_acc_bitwidth}, {entries_53_bits_has_acc_bitwidth}, {entries_52_bits_has_acc_bitwidth}, {entries_51_bits_has_acc_bitwidth}, {entries_50_bits_has_acc_bitwidth}, {entries_49_bits_has_acc_bitwidth}, {entries_48_bits_has_acc_bitwidth}, {entries_47_bits_has_acc_bitwidth}, {entries_46_bits_has_acc_bitwidth}, {entries_45_bits_has_acc_bitwidth}, {entries_44_bits_has_acc_bitwidth}, {entries_43_bits_has_acc_bitwidth}, {entries_42_bits_has_acc_bitwidth}, {entries_41_bits_has_acc_bitwidth}, {entries_40_bits_has_acc_bitwidth}, {entries_39_bits_has_acc_bitwidth}, {entries_38_bits_has_acc_bitwidth}, {entries_37_bits_has_acc_bitwidth}, {entries_36_bits_has_acc_bitwidth}, {entries_35_bits_has_acc_bitwidth}, {entries_34_bits_has_acc_bitwidth}, {entries_33_bits_has_acc_bitwidth}, {entries_32_bits_has_acc_bitwidth}, {entries_31_bits_has_acc_bitwidth}, {entries_30_bits_has_acc_bitwidth}, {entries_29_bits_has_acc_bitwidth}, {entries_28_bits_has_acc_bitwidth}, {entries_27_bits_has_acc_bitwidth}, {entries_26_bits_has_acc_bitwidth}, {entries_25_bits_has_acc_bitwidth}, {entries_24_bits_has_acc_bitwidth}, {entries_23_bits_has_acc_bitwidth}, {entries_22_bits_has_acc_bitwidth}, {entries_21_bits_has_acc_bitwidth}, {entries_20_bits_has_acc_bitwidth}, {entries_19_bits_has_acc_bitwidth}, {entries_18_bits_has_acc_bitwidth}, {entries_17_bits_has_acc_bitwidth}, {entries_16_bits_has_acc_bitwidth}, {entries_15_bits_has_acc_bitwidth}, {entries_14_bits_has_acc_bitwidth}, {entries_13_bits_has_acc_bitwidth}, {entries_12_bits_has_acc_bitwidth}, {entries_11_bits_has_acc_bitwidth}, {entries_10_bits_has_acc_bitwidth}, {entries_9_bits_has_acc_bitwidth}, {entries_8_bits_has_acc_bitwidth}, {entries_7_bits_has_acc_bitwidth}, {entries_6_bits_has_acc_bitwidth}, {entries_5_bits_has_acc_bitwidth}, {entries_4_bits_has_acc_bitwidth}, {entries_3_bits_has_acc_bitwidth}, {entries_2_bits_has_acc_bitwidth}, {entries_1_bits_has_acc_bitwidth}, {entries_0_bits_has_acc_bitwidth}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_has_acc_bitwidth_0 = _GEN_4[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][31:0] _GEN_5 = {{entries_63_bits_scale}, {entries_62_bits_scale}, {entries_61_bits_scale}, {entries_60_bits_scale}, {entries_59_bits_scale}, {entries_58_bits_scale}, {entries_57_bits_scale}, {entries_56_bits_scale}, {entries_55_bits_scale}, {entries_54_bits_scale}, {entries_53_bits_scale}, {entries_52_bits_scale}, {entries_51_bits_scale}, {entries_50_bits_scale}, {entries_49_bits_scale}, {entries_48_bits_scale}, {entries_47_bits_scale}, {entries_46_bits_scale}, {entries_45_bits_scale}, {entries_44_bits_scale}, {entries_43_bits_scale}, {entries_42_bits_scale}, {entries_41_bits_scale}, {entries_40_bits_scale}, {entries_39_bits_scale}, {entries_38_bits_scale}, {entries_37_bits_scale}, {entries_36_bits_scale}, {entries_35_bits_scale}, {entries_34_bits_scale}, {entries_33_bits_scale}, {entries_32_bits_scale}, {entries_31_bits_scale}, {entries_30_bits_scale}, {entries_29_bits_scale}, {entries_28_bits_scale}, {entries_27_bits_scale}, {entries_26_bits_scale}, {entries_25_bits_scale}, {entries_24_bits_scale}, {entries_23_bits_scale}, {entries_22_bits_scale}, {entries_21_bits_scale}, {entries_20_bits_scale}, {entries_19_bits_scale}, {entries_18_bits_scale}, {entries_17_bits_scale}, {entries_16_bits_scale}, {entries_15_bits_scale}, {entries_14_bits_scale}, {entries_13_bits_scale}, {entries_12_bits_scale}, {entries_11_bits_scale}, {entries_10_bits_scale}, {entries_9_bits_scale}, {entries_8_bits_scale}, {entries_7_bits_scale}, {entries_6_bits_scale}, {entries_5_bits_scale}, {entries_4_bits_scale}, {entries_3_bits_scale}, {entries_2_bits_scale}, {entries_1_bits_scale}, {entries_0_bits_scale}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_scale_0 = _GEN_5[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][15:0] _GEN_6 = {{entries_63_bits_repeats}, {entries_62_bits_repeats}, {entries_61_bits_repeats}, {entries_60_bits_repeats}, {entries_59_bits_repeats}, {entries_58_bits_repeats}, {entries_57_bits_repeats}, {entries_56_bits_repeats}, {entries_55_bits_repeats}, {entries_54_bits_repeats}, {entries_53_bits_repeats}, {entries_52_bits_repeats}, {entries_51_bits_repeats}, {entries_50_bits_repeats}, {entries_49_bits_repeats}, {entries_48_bits_repeats}, {entries_47_bits_repeats}, {entries_46_bits_repeats}, {entries_45_bits_repeats}, {entries_44_bits_repeats}, {entries_43_bits_repeats}, {entries_42_bits_repeats}, {entries_41_bits_repeats}, {entries_40_bits_repeats}, {entries_39_bits_repeats}, {entries_38_bits_repeats}, {entries_37_bits_repeats}, {entries_36_bits_repeats}, {entries_35_bits_repeats}, {entries_34_bits_repeats}, {entries_33_bits_repeats}, {entries_32_bits_repeats}, {entries_31_bits_repeats}, {entries_30_bits_repeats}, {entries_29_bits_repeats}, {entries_28_bits_repeats}, {entries_27_bits_repeats}, {entries_26_bits_repeats}, {entries_25_bits_repeats}, {entries_24_bits_repeats}, {entries_23_bits_repeats}, {entries_22_bits_repeats}, {entries_21_bits_repeats}, {entries_20_bits_repeats}, {entries_19_bits_repeats}, {entries_18_bits_repeats}, {entries_17_bits_repeats}, {entries_16_bits_repeats}, {entries_15_bits_repeats}, {entries_14_bits_repeats}, {entries_13_bits_repeats}, {entries_12_bits_repeats}, {entries_11_bits_repeats}, {entries_10_bits_repeats}, {entries_9_bits_repeats}, {entries_8_bits_repeats}, {entries_7_bits_repeats}, {entries_6_bits_repeats}, {entries_5_bits_repeats}, {entries_4_bits_repeats}, {entries_3_bits_repeats}, {entries_2_bits_repeats}, {entries_1_bits_repeats}, {entries_0_bits_repeats}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_repeats_0 = _GEN_6[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][7:0] _GEN_7 = {{entries_63_bits_pixel_repeats}, {entries_62_bits_pixel_repeats}, {entries_61_bits_pixel_repeats}, {entries_60_bits_pixel_repeats}, {entries_59_bits_pixel_repeats}, {entries_58_bits_pixel_repeats}, {entries_57_bits_pixel_repeats}, {entries_56_bits_pixel_repeats}, {entries_55_bits_pixel_repeats}, {entries_54_bits_pixel_repeats}, {entries_53_bits_pixel_repeats}, {entries_52_bits_pixel_repeats}, {entries_51_bits_pixel_repeats}, {entries_50_bits_pixel_repeats}, {entries_49_bits_pixel_repeats}, {entries_48_bits_pixel_repeats}, {entries_47_bits_pixel_repeats}, {entries_46_bits_pixel_repeats}, {entries_45_bits_pixel_repeats}, {entries_44_bits_pixel_repeats}, {entries_43_bits_pixel_repeats}, {entries_42_bits_pixel_repeats}, {entries_41_bits_pixel_repeats}, {entries_40_bits_pixel_repeats}, {entries_39_bits_pixel_repeats}, {entries_38_bits_pixel_repeats}, {entries_37_bits_pixel_repeats}, {entries_36_bits_pixel_repeats}, {entries_35_bits_pixel_repeats}, {entries_34_bits_pixel_repeats}, {entries_33_bits_pixel_repeats}, {entries_32_bits_pixel_repeats}, {entries_31_bits_pixel_repeats}, {entries_30_bits_pixel_repeats}, {entries_29_bits_pixel_repeats}, {entries_28_bits_pixel_repeats}, {entries_27_bits_pixel_repeats}, {entries_26_bits_pixel_repeats}, {entries_25_bits_pixel_repeats}, {entries_24_bits_pixel_repeats}, {entries_23_bits_pixel_repeats}, {entries_22_bits_pixel_repeats}, {entries_21_bits_pixel_repeats}, {entries_20_bits_pixel_repeats}, {entries_19_bits_pixel_repeats}, {entries_18_bits_pixel_repeats}, {entries_17_bits_pixel_repeats}, {entries_16_bits_pixel_repeats}, {entries_15_bits_pixel_repeats}, {entries_14_bits_pixel_repeats}, {entries_13_bits_pixel_repeats}, {entries_12_bits_pixel_repeats}, {entries_11_bits_pixel_repeats}, {entries_10_bits_pixel_repeats}, {entries_9_bits_pixel_repeats}, {entries_8_bits_pixel_repeats}, {entries_7_bits_pixel_repeats}, {entries_6_bits_pixel_repeats}, {entries_5_bits_pixel_repeats}, {entries_4_bits_pixel_repeats}, {entries_3_bits_pixel_repeats}, {entries_2_bits_pixel_repeats}, {entries_1_bits_pixel_repeats}, {entries_0_bits_pixel_repeats}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_pixel_repeats_0 = _GEN_7[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][15:0] _GEN_8 = {{entries_63_bits_len}, {entries_62_bits_len}, {entries_61_bits_len}, {entries_60_bits_len}, {entries_59_bits_len}, {entries_58_bits_len}, {entries_57_bits_len}, {entries_56_bits_len}, {entries_55_bits_len}, {entries_54_bits_len}, {entries_53_bits_len}, {entries_52_bits_len}, {entries_51_bits_len}, {entries_50_bits_len}, {entries_49_bits_len}, {entries_48_bits_len}, {entries_47_bits_len}, {entries_46_bits_len}, {entries_45_bits_len}, {entries_44_bits_len}, {entries_43_bits_len}, {entries_42_bits_len}, {entries_41_bits_len}, {entries_40_bits_len}, {entries_39_bits_len}, {entries_38_bits_len}, {entries_37_bits_len}, {entries_36_bits_len}, {entries_35_bits_len}, {entries_34_bits_len}, {entries_33_bits_len}, {entries_32_bits_len}, {entries_31_bits_len}, {entries_30_bits_len}, {entries_29_bits_len}, {entries_28_bits_len}, {entries_27_bits_len}, {entries_26_bits_len}, {entries_25_bits_len}, {entries_24_bits_len}, {entries_23_bits_len}, {entries_22_bits_len}, {entries_21_bits_len}, {entries_20_bits_len}, {entries_19_bits_len}, {entries_18_bits_len}, {entries_17_bits_len}, {entries_16_bits_len}, {entries_15_bits_len}, {entries_14_bits_len}, {entries_13_bits_len}, {entries_12_bits_len}, {entries_11_bits_len}, {entries_10_bits_len}, {entries_9_bits_len}, {entries_8_bits_len}, {entries_7_bits_len}, {entries_6_bits_len}, {entries_5_bits_len}, {entries_4_bits_len}, {entries_3_bits_len}, {entries_2_bits_len}, {entries_1_bits_len}, {entries_0_bits_len}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_len_0 = _GEN_8[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][15:0] _GEN_9 = {{entries_63_bits_block_stride}, {entries_62_bits_block_stride}, {entries_61_bits_block_stride}, {entries_60_bits_block_stride}, {entries_59_bits_block_stride}, {entries_58_bits_block_stride}, {entries_57_bits_block_stride}, {entries_56_bits_block_stride}, {entries_55_bits_block_stride}, {entries_54_bits_block_stride}, {entries_53_bits_block_stride}, {entries_52_bits_block_stride}, {entries_51_bits_block_stride}, {entries_50_bits_block_stride}, {entries_49_bits_block_stride}, {entries_48_bits_block_stride}, {entries_47_bits_block_stride}, {entries_46_bits_block_stride}, {entries_45_bits_block_stride}, {entries_44_bits_block_stride}, {entries_43_bits_block_stride}, {entries_42_bits_block_stride}, {entries_41_bits_block_stride}, {entries_40_bits_block_stride}, {entries_39_bits_block_stride}, {entries_38_bits_block_stride}, {entries_37_bits_block_stride}, {entries_36_bits_block_stride}, {entries_35_bits_block_stride}, {entries_34_bits_block_stride}, {entries_33_bits_block_stride}, {entries_32_bits_block_stride}, {entries_31_bits_block_stride}, {entries_30_bits_block_stride}, {entries_29_bits_block_stride}, {entries_28_bits_block_stride}, {entries_27_bits_block_stride}, {entries_26_bits_block_stride}, {entries_25_bits_block_stride}, {entries_24_bits_block_stride}, {entries_23_bits_block_stride}, {entries_22_bits_block_stride}, {entries_21_bits_block_stride}, {entries_20_bits_block_stride}, {entries_19_bits_block_stride}, {entries_18_bits_block_stride}, {entries_17_bits_block_stride}, {entries_16_bits_block_stride}, {entries_15_bits_block_stride}, {entries_14_bits_block_stride}, {entries_13_bits_block_stride}, {entries_12_bits_block_stride}, {entries_11_bits_block_stride}, {entries_10_bits_block_stride}, {entries_9_bits_block_stride}, {entries_8_bits_block_stride}, {entries_7_bits_block_stride}, {entries_6_bits_block_stride}, {entries_5_bits_block_stride}, {entries_4_bits_block_stride}, {entries_3_bits_block_stride}, {entries_2_bits_block_stride}, {entries_1_bits_block_stride}, {entries_0_bits_block_stride}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_block_stride_0 = _GEN_9[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][8:0] _GEN_10 = {{entries_63_bits_spad_row_offset}, {entries_62_bits_spad_row_offset}, {entries_61_bits_spad_row_offset}, {entries_60_bits_spad_row_offset}, {entries_59_bits_spad_row_offset}, {entries_58_bits_spad_row_offset}, {entries_57_bits_spad_row_offset}, {entries_56_bits_spad_row_offset}, {entries_55_bits_spad_row_offset}, {entries_54_bits_spad_row_offset}, {entries_53_bits_spad_row_offset}, {entries_52_bits_spad_row_offset}, {entries_51_bits_spad_row_offset}, {entries_50_bits_spad_row_offset}, {entries_49_bits_spad_row_offset}, {entries_48_bits_spad_row_offset}, {entries_47_bits_spad_row_offset}, {entries_46_bits_spad_row_offset}, {entries_45_bits_spad_row_offset}, {entries_44_bits_spad_row_offset}, {entries_43_bits_spad_row_offset}, {entries_42_bits_spad_row_offset}, {entries_41_bits_spad_row_offset}, {entries_40_bits_spad_row_offset}, {entries_39_bits_spad_row_offset}, {entries_38_bits_spad_row_offset}, {entries_37_bits_spad_row_offset}, {entries_36_bits_spad_row_offset}, {entries_35_bits_spad_row_offset}, {entries_34_bits_spad_row_offset}, {entries_33_bits_spad_row_offset}, {entries_32_bits_spad_row_offset}, {entries_31_bits_spad_row_offset}, {entries_30_bits_spad_row_offset}, {entries_29_bits_spad_row_offset}, {entries_28_bits_spad_row_offset}, {entries_27_bits_spad_row_offset}, {entries_26_bits_spad_row_offset}, {entries_25_bits_spad_row_offset}, {entries_24_bits_spad_row_offset}, {entries_23_bits_spad_row_offset}, {entries_22_bits_spad_row_offset}, {entries_21_bits_spad_row_offset}, {entries_20_bits_spad_row_offset}, {entries_19_bits_spad_row_offset}, {entries_18_bits_spad_row_offset}, {entries_17_bits_spad_row_offset}, {entries_16_bits_spad_row_offset}, {entries_15_bits_spad_row_offset}, {entries_14_bits_spad_row_offset}, {entries_13_bits_spad_row_offset}, {entries_12_bits_spad_row_offset}, {entries_11_bits_spad_row_offset}, {entries_10_bits_spad_row_offset}, {entries_9_bits_spad_row_offset}, {entries_8_bits_spad_row_offset}, {entries_7_bits_spad_row_offset}, {entries_6_bits_spad_row_offset}, {entries_5_bits_spad_row_offset}, {entries_4_bits_spad_row_offset}, {entries_3_bits_spad_row_offset}, {entries_2_bits_spad_row_offset}, {entries_1_bits_spad_row_offset}, {entries_0_bits_spad_row_offset}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_spad_row_offset_0 = _GEN_10[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][6:0] _GEN_11 = {{entries_63_bits_bytes_to_read}, {entries_62_bits_bytes_to_read}, {entries_61_bits_bytes_to_read}, {entries_60_bits_bytes_to_read}, {entries_59_bits_bytes_to_read}, {entries_58_bits_bytes_to_read}, {entries_57_bits_bytes_to_read}, {entries_56_bits_bytes_to_read}, {entries_55_bits_bytes_to_read}, {entries_54_bits_bytes_to_read}, {entries_53_bits_bytes_to_read}, {entries_52_bits_bytes_to_read}, {entries_51_bits_bytes_to_read}, {entries_50_bits_bytes_to_read}, {entries_49_bits_bytes_to_read}, {entries_48_bits_bytes_to_read}, {entries_47_bits_bytes_to_read}, {entries_46_bits_bytes_to_read}, {entries_45_bits_bytes_to_read}, {entries_44_bits_bytes_to_read}, {entries_43_bits_bytes_to_read}, {entries_42_bits_bytes_to_read}, {entries_41_bits_bytes_to_read}, {entries_40_bits_bytes_to_read}, {entries_39_bits_bytes_to_read}, {entries_38_bits_bytes_to_read}, {entries_37_bits_bytes_to_read}, {entries_36_bits_bytes_to_read}, {entries_35_bits_bytes_to_read}, {entries_34_bits_bytes_to_read}, {entries_33_bits_bytes_to_read}, {entries_32_bits_bytes_to_read}, {entries_31_bits_bytes_to_read}, {entries_30_bits_bytes_to_read}, {entries_29_bits_bytes_to_read}, {entries_28_bits_bytes_to_read}, {entries_27_bits_bytes_to_read}, {entries_26_bits_bytes_to_read}, {entries_25_bits_bytes_to_read}, {entries_24_bits_bytes_to_read}, {entries_23_bits_bytes_to_read}, {entries_22_bits_bytes_to_read}, {entries_21_bits_bytes_to_read}, {entries_20_bits_bytes_to_read}, {entries_19_bits_bytes_to_read}, {entries_18_bits_bytes_to_read}, {entries_17_bits_bytes_to_read}, {entries_16_bits_bytes_to_read}, {entries_15_bits_bytes_to_read}, {entries_14_bits_bytes_to_read}, {entries_13_bits_bytes_to_read}, {entries_12_bits_bytes_to_read}, {entries_11_bits_bytes_to_read}, {entries_10_bits_bytes_to_read}, {entries_9_bits_bytes_to_read}, {entries_8_bits_bytes_to_read}, {entries_7_bits_bytes_to_read}, {entries_6_bits_bytes_to_read}, {entries_5_bits_bytes_to_read}, {entries_4_bits_bytes_to_read}, {entries_3_bits_bytes_to_read}, {entries_2_bits_bytes_to_read}, {entries_1_bits_bytes_to_read}, {entries_0_bits_bytes_to_read}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_bytes_to_read_0 = _GEN_11[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [63:0][2:0] _GEN_12 = {{entries_63_bits_cmd_id}, {entries_62_bits_cmd_id}, {entries_61_bits_cmd_id}, {entries_60_bits_cmd_id}, {entries_59_bits_cmd_id}, {entries_58_bits_cmd_id}, {entries_57_bits_cmd_id}, {entries_56_bits_cmd_id}, {entries_55_bits_cmd_id}, {entries_54_bits_cmd_id}, {entries_53_bits_cmd_id}, {entries_52_bits_cmd_id}, {entries_51_bits_cmd_id}, {entries_50_bits_cmd_id}, {entries_49_bits_cmd_id}, {entries_48_bits_cmd_id}, {entries_47_bits_cmd_id}, {entries_46_bits_cmd_id}, {entries_45_bits_cmd_id}, {entries_44_bits_cmd_id}, {entries_43_bits_cmd_id}, {entries_42_bits_cmd_id}, {entries_41_bits_cmd_id}, {entries_40_bits_cmd_id}, {entries_39_bits_cmd_id}, {entries_38_bits_cmd_id}, {entries_37_bits_cmd_id}, {entries_36_bits_cmd_id}, {entries_35_bits_cmd_id}, {entries_34_bits_cmd_id}, {entries_33_bits_cmd_id}, {entries_32_bits_cmd_id}, {entries_31_bits_cmd_id}, {entries_30_bits_cmd_id}, {entries_29_bits_cmd_id}, {entries_28_bits_cmd_id}, {entries_27_bits_cmd_id}, {entries_26_bits_cmd_id}, {entries_25_bits_cmd_id}, {entries_24_bits_cmd_id}, {entries_23_bits_cmd_id}, {entries_22_bits_cmd_id}, {entries_21_bits_cmd_id}, {entries_20_bits_cmd_id}, {entries_19_bits_cmd_id}, {entries_18_bits_cmd_id}, {entries_17_bits_cmd_id}, {entries_16_bits_cmd_id}, {entries_15_bits_cmd_id}, {entries_14_bits_cmd_id}, {entries_13_bits_cmd_id}, {entries_12_bits_cmd_id}, {entries_11_bits_cmd_id}, {entries_10_bits_cmd_id}, {entries_9_bits_cmd_id}, {entries_8_bits_cmd_id}, {entries_7_bits_cmd_id}, {entries_6_bits_cmd_id}, {entries_5_bits_cmd_id}, {entries_4_bits_cmd_id}, {entries_3_bits_cmd_id}, {entries_2_bits_cmd_id}, {entries_1_bits_cmd_id}, {entries_0_bits_cmd_id}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_cmd_id_0 = _GEN_12[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire _io_busy_T = entries_0_valid | entries_1_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_1 = _io_busy_T | entries_2_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_2 = _io_busy_T_1 | entries_3_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_3 = _io_busy_T_2 | entries_4_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_4 = _io_busy_T_3 | entries_5_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_5 = _io_busy_T_4 | entries_6_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_6 = _io_busy_T_5 | entries_7_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_7 = _io_busy_T_6 | entries_8_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_8 = _io_busy_T_7 | entries_9_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_9 = _io_busy_T_8 | entries_10_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_10 = _io_busy_T_9 | entries_11_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_11 = _io_busy_T_10 | entries_12_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_12 = _io_busy_T_11 | entries_13_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_13 = _io_busy_T_12 | entries_14_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_14 = _io_busy_T_13 | entries_15_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_15 = _io_busy_T_14 | entries_16_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_16 = _io_busy_T_15 | entries_17_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_17 = _io_busy_T_16 | entries_18_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_18 = _io_busy_T_17 | entries_19_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_19 = _io_busy_T_18 | entries_20_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_20 = _io_busy_T_19 | entries_21_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_21 = _io_busy_T_20 | entries_22_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_22 = _io_busy_T_21 | entries_23_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_23 = _io_busy_T_22 | entries_24_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_24 = _io_busy_T_23 | entries_25_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_25 = _io_busy_T_24 | entries_26_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_26 = _io_busy_T_25 | entries_27_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_27 = _io_busy_T_26 | entries_28_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_28 = _io_busy_T_27 | entries_29_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_29 = _io_busy_T_28 | entries_30_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_30 = _io_busy_T_29 | entries_31_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_31 = _io_busy_T_30 | entries_32_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_32 = _io_busy_T_31 | entries_33_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_33 = _io_busy_T_32 | entries_34_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_34 = _io_busy_T_33 | entries_35_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_35 = _io_busy_T_34 | entries_36_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_36 = _io_busy_T_35 | entries_37_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_37 = _io_busy_T_36 | entries_38_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_38 = _io_busy_T_37 | entries_39_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_39 = _io_busy_T_38 | entries_40_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_40 = _io_busy_T_39 | entries_41_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_41 = _io_busy_T_40 | entries_42_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_42 = _io_busy_T_41 | entries_43_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_43 = _io_busy_T_42 | entries_44_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_44 = _io_busy_T_43 | entries_45_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_45 = _io_busy_T_44 | entries_46_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_46 = _io_busy_T_45 | entries_47_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_47 = _io_busy_T_46 | entries_48_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_48 = _io_busy_T_47 | entries_49_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_49 = _io_busy_T_48 | entries_50_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_50 = _io_busy_T_49 | entries_51_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_51 = _io_busy_T_50 | entries_52_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_52 = _io_busy_T_51 | entries_53_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_53 = _io_busy_T_52 | entries_54_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_54 = _io_busy_T_53 | entries_55_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_55 = _io_busy_T_54 | entries_56_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_56 = _io_busy_T_55 | entries_57_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_57 = _io_busy_T_56 | entries_58_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_58 = _io_busy_T_57 | entries_59_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_59 = _io_busy_T_58 | entries_60_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_60 = _io_busy_T_59 | entries_61_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_61 = _io_busy_T_60 | entries_62_valid; // @[XactTracker.scala:67:20, :75:44] assign _io_busy_T_62 = _io_busy_T_61 | entries_63_valid; // @[XactTracker.scala:67:20, :75:44] assign io_busy_0 = _io_busy_T_62; // @[XactTracker.scala:56:7, :75:44] wire _GEN_13 = io_peek_pop_0 & ~reset; // @[XactTracker.scala:56:7, :84:11] reg [31:0] total_latency; // @[XactTracker.scala:94:30] assign io_counter_external_values_6_0 = total_latency; // @[XactTracker.scala:56:7, :94:30] wire [1:0] _total_latency_T = {1'h0, entries_0_valid} + {1'h0, entries_1_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_1 = _total_latency_T; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_2 = {1'h0, entries_2_valid} + {1'h0, entries_3_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_3 = _total_latency_T_2; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_4 = {1'h0, _total_latency_T_1} + {1'h0, _total_latency_T_3}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_5 = _total_latency_T_4; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_6 = {1'h0, entries_4_valid} + {1'h0, entries_5_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_7 = _total_latency_T_6; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_8 = {1'h0, entries_6_valid} + {1'h0, entries_7_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_9 = _total_latency_T_8; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_10 = {1'h0, _total_latency_T_7} + {1'h0, _total_latency_T_9}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_11 = _total_latency_T_10; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_12 = {1'h0, _total_latency_T_5} + {1'h0, _total_latency_T_11}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_13 = _total_latency_T_12; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_14 = {1'h0, entries_8_valid} + {1'h0, entries_9_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_15 = _total_latency_T_14; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_16 = {1'h0, entries_10_valid} + {1'h0, entries_11_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_17 = _total_latency_T_16; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_18 = {1'h0, _total_latency_T_15} + {1'h0, _total_latency_T_17}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_19 = _total_latency_T_18; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_20 = {1'h0, entries_12_valid} + {1'h0, entries_13_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_21 = _total_latency_T_20; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_22 = {1'h0, entries_14_valid} + {1'h0, entries_15_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_23 = _total_latency_T_22; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_24 = {1'h0, _total_latency_T_21} + {1'h0, _total_latency_T_23}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_25 = _total_latency_T_24; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_26 = {1'h0, _total_latency_T_19} + {1'h0, _total_latency_T_25}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_27 = _total_latency_T_26; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_28 = {1'h0, _total_latency_T_13} + {1'h0, _total_latency_T_27}; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_29 = _total_latency_T_28; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_30 = {1'h0, entries_16_valid} + {1'h0, entries_17_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_31 = _total_latency_T_30; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_32 = {1'h0, entries_18_valid} + {1'h0, entries_19_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_33 = _total_latency_T_32; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_34 = {1'h0, _total_latency_T_31} + {1'h0, _total_latency_T_33}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_35 = _total_latency_T_34; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_36 = {1'h0, entries_20_valid} + {1'h0, entries_21_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_37 = _total_latency_T_36; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_38 = {1'h0, entries_22_valid} + {1'h0, entries_23_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_39 = _total_latency_T_38; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_40 = {1'h0, _total_latency_T_37} + {1'h0, _total_latency_T_39}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_41 = _total_latency_T_40; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_42 = {1'h0, _total_latency_T_35} + {1'h0, _total_latency_T_41}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_43 = _total_latency_T_42; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_44 = {1'h0, entries_24_valid} + {1'h0, entries_25_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_45 = _total_latency_T_44; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_46 = {1'h0, entries_26_valid} + {1'h0, entries_27_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_47 = _total_latency_T_46; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_48 = {1'h0, _total_latency_T_45} + {1'h0, _total_latency_T_47}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_49 = _total_latency_T_48; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_50 = {1'h0, entries_28_valid} + {1'h0, entries_29_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_51 = _total_latency_T_50; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_52 = {1'h0, entries_30_valid} + {1'h0, entries_31_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_53 = _total_latency_T_52; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_54 = {1'h0, _total_latency_T_51} + {1'h0, _total_latency_T_53}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_55 = _total_latency_T_54; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_56 = {1'h0, _total_latency_T_49} + {1'h0, _total_latency_T_55}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_57 = _total_latency_T_56; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_58 = {1'h0, _total_latency_T_43} + {1'h0, _total_latency_T_57}; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_59 = _total_latency_T_58; // @[XactTracker.scala:98:46] wire [5:0] _total_latency_T_60 = {1'h0, _total_latency_T_29} + {1'h0, _total_latency_T_59}; // @[XactTracker.scala:98:46] wire [5:0] _total_latency_T_61 = _total_latency_T_60; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_62 = {1'h0, entries_32_valid} + {1'h0, entries_33_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_63 = _total_latency_T_62; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_64 = {1'h0, entries_34_valid} + {1'h0, entries_35_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_65 = _total_latency_T_64; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_66 = {1'h0, _total_latency_T_63} + {1'h0, _total_latency_T_65}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_67 = _total_latency_T_66; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_68 = {1'h0, entries_36_valid} + {1'h0, entries_37_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_69 = _total_latency_T_68; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_70 = {1'h0, entries_38_valid} + {1'h0, entries_39_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_71 = _total_latency_T_70; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_72 = {1'h0, _total_latency_T_69} + {1'h0, _total_latency_T_71}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_73 = _total_latency_T_72; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_74 = {1'h0, _total_latency_T_67} + {1'h0, _total_latency_T_73}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_75 = _total_latency_T_74; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_76 = {1'h0, entries_40_valid} + {1'h0, entries_41_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_77 = _total_latency_T_76; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_78 = {1'h0, entries_42_valid} + {1'h0, entries_43_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_79 = _total_latency_T_78; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_80 = {1'h0, _total_latency_T_77} + {1'h0, _total_latency_T_79}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_81 = _total_latency_T_80; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_82 = {1'h0, entries_44_valid} + {1'h0, entries_45_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_83 = _total_latency_T_82; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_84 = {1'h0, entries_46_valid} + {1'h0, entries_47_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_85 = _total_latency_T_84; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_86 = {1'h0, _total_latency_T_83} + {1'h0, _total_latency_T_85}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_87 = _total_latency_T_86; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_88 = {1'h0, _total_latency_T_81} + {1'h0, _total_latency_T_87}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_89 = _total_latency_T_88; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_90 = {1'h0, _total_latency_T_75} + {1'h0, _total_latency_T_89}; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_91 = _total_latency_T_90; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_92 = {1'h0, entries_48_valid} + {1'h0, entries_49_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_93 = _total_latency_T_92; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_94 = {1'h0, entries_50_valid} + {1'h0, entries_51_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_95 = _total_latency_T_94; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_96 = {1'h0, _total_latency_T_93} + {1'h0, _total_latency_T_95}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_97 = _total_latency_T_96; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_98 = {1'h0, entries_52_valid} + {1'h0, entries_53_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_99 = _total_latency_T_98; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_100 = {1'h0, entries_54_valid} + {1'h0, entries_55_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_101 = _total_latency_T_100; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_102 = {1'h0, _total_latency_T_99} + {1'h0, _total_latency_T_101}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_103 = _total_latency_T_102; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_104 = {1'h0, _total_latency_T_97} + {1'h0, _total_latency_T_103}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_105 = _total_latency_T_104; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_106 = {1'h0, entries_56_valid} + {1'h0, entries_57_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_107 = _total_latency_T_106; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_108 = {1'h0, entries_58_valid} + {1'h0, entries_59_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_109 = _total_latency_T_108; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_110 = {1'h0, _total_latency_T_107} + {1'h0, _total_latency_T_109}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_111 = _total_latency_T_110; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_112 = {1'h0, entries_60_valid} + {1'h0, entries_61_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_113 = _total_latency_T_112; // @[XactTracker.scala:98:46] wire [1:0] _total_latency_T_114 = {1'h0, entries_62_valid} + {1'h0, entries_63_valid}; // @[XactTracker.scala:67:20, :98:46] wire [1:0] _total_latency_T_115 = _total_latency_T_114; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_116 = {1'h0, _total_latency_T_113} + {1'h0, _total_latency_T_115}; // @[XactTracker.scala:98:46] wire [2:0] _total_latency_T_117 = _total_latency_T_116; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_118 = {1'h0, _total_latency_T_111} + {1'h0, _total_latency_T_117}; // @[XactTracker.scala:98:46] wire [3:0] _total_latency_T_119 = _total_latency_T_118; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_120 = {1'h0, _total_latency_T_105} + {1'h0, _total_latency_T_119}; // @[XactTracker.scala:98:46] wire [4:0] _total_latency_T_121 = _total_latency_T_120; // @[XactTracker.scala:98:46] wire [5:0] _total_latency_T_122 = {1'h0, _total_latency_T_91} + {1'h0, _total_latency_T_121}; // @[XactTracker.scala:98:46] wire [5:0] _total_latency_T_123 = _total_latency_T_122; // @[XactTracker.scala:98:46] wire [6:0] _total_latency_T_124 = {1'h0, _total_latency_T_61} + {1'h0, _total_latency_T_123}; // @[XactTracker.scala:98:46] wire [6:0] _total_latency_T_125 = _total_latency_T_124; // @[XactTracker.scala:98:46] wire [32:0] _total_latency_T_126 = {1'h0, total_latency} + {26'h0, _total_latency_T_125}; // @[XactTracker.scala:94:30, :98:{36,46}] wire [31:0] _total_latency_T_127 = _total_latency_T_126[31:0]; // @[XactTracker.scala:98:36] reg [18:0] cntr_value; // @[Counter.scala:61:40] wire wrap = cntr_value == 19'h7A11F; // @[Counter.scala:61:40, :73:24] wire [19:0] _value_T = {1'h0, cntr_value} + 20'h1; // @[Counter.scala:61:40, :77:24] wire [18:0] _value_T_1 = _value_T[18:0]; // @[Counter.scala:77:24] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_190( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_296( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_40 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_23( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [3:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [3:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [3:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [36:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] reg [3:0] mask; // @[InputUnit.scala:250:21] wire [3:0] _vcalloc_filter_T_3 = {vcalloc_vals_3, 1'h0, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [7:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 8'h1 : _vcalloc_filter_T_3[1] ? 8'h2 : _vcalloc_filter_T_3[2] ? 8'h4 : _vcalloc_filter_T_3[3] ? 8'h8 : vcalloc_vals_0 ? 8'h10 : vcalloc_vals_1 ? 8'h20 : {vcalloc_vals_3, 7'h0}; // @[OneHot.scala:85:71] wire [3:0] vcalloc_sel = vcalloc_filter[3:0] | vcalloc_filter[7:4]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_3; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_117( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `β†’`: target of arrow is generated by source * * {{{ * (from the other node) * β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€[[InwardNode.uiParams]]─────────────┐ * ↓ β”‚ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ β”‚ * [[InwardNode.accPI]] β”‚ β”‚ β”‚ * β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ ↓ β”‚ * ↓ β”‚ β”‚ β”‚ * (immobilize after elaboration) (inward port from [[OutwardNode]]) β”‚ ↓ β”‚ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] β”‚ * β”‚ β”‚ ↑ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[OutwardNode.doParams]] β”‚ β”‚ * β”‚ β”‚ β”‚ (from the other node) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ └────────┬─────────────── β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ (from the other node) β”‚ ↓ β”‚ * β”‚ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] β”‚ [[MixedNode.edgesIn]]───┐ β”‚ * β”‚ ↑ ↑ β”‚ β”‚ ↓ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ [[MixedNode.in]] β”‚ * β”‚ β”‚ β”‚ β”‚ ↓ ↑ β”‚ * β”‚ (solve star connection) β”‚ β”‚ β”‚ [[MixedNode.bundleIn]]β”€β”€β”˜ β”‚ * β”œβ”€β”€β”€[[MixedNode.resolveStar]]→─┼────────────────────────────── └────────────────────────────────────┐ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.bundleOut]]─┐ β”‚ β”‚ * β”‚ β”‚ β”‚ ↑ ↓ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.out]] β”‚ β”‚ * β”‚ ↓ ↓ β”‚ ↑ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]β”€β”€β”˜ β”‚ β”‚ * β”‚ β”‚ (from the other node) ↑ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.outer.edgeO]] β”‚ β”‚ * β”‚ β”‚ β”‚ (based on protocol) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * (immobilize after elaboration)β”‚ ↓ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.oBindings]]β”€β”˜ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] β”‚ β”‚ * ↑ (inward port from [[OutwardNode]]) β”‚ β”‚ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.accPO]] β”‚ ↓ β”‚ β”‚ β”‚ * (binding node when elaboration) β”‚ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ * β”‚ ↑ β”‚ β”‚ * β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ * β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a32d128s3k7z4u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_1_b_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_1_b_ready_0 = auto_in_1_b_ready; // @[Buffer.scala:40:9] wire auto_in_1_c_valid_0 = auto_in_1_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_c_bits_opcode_0 = auto_in_1_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_c_bits_param_0 = auto_in_1_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_c_bits_size_0 = auto_in_1_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_c_bits_source_0 = auto_in_1_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_1_c_bits_address_0 = auto_in_1_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_1_c_bits_data_0 = auto_in_1_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[Buffer.scala:40:9] wire auto_in_1_e_valid_0 = auto_in_1_e_valid; // @[Buffer.scala:40:9] wire [6:0] auto_in_1_e_bits_sink_0 = auto_in_1_e_bits_sink; // @[Buffer.scala:40:9] wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[Buffer.scala:40:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[Buffer.scala:40:9] wire auto_out_1_b_valid_0 = auto_out_1_b_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_b_bits_opcode_0 = auto_out_1_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_b_bits_param_0 = auto_out_1_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_b_bits_size_0 = auto_out_1_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_b_bits_source_0 = auto_out_1_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_1_b_bits_address_0 = auto_out_1_b_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_out_1_b_bits_mask_0 = auto_out_1_b_bits_mask; // @[Buffer.scala:40:9] wire auto_out_1_c_ready_0 = auto_out_1_c_ready; // @[Buffer.scala:40:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[Buffer.scala:40:9] wire [6:0] auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_1_e_ready_0 = auto_out_1_e_ready; // @[Buffer.scala:40:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[Buffer.scala:40:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[Buffer.scala:40:9] wire [6:0] auto_out_0_d_bits_sink_0 = auto_out_0_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire [127:0] auto_out_1_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] x1_nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_0_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire auto_in_1_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_1_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_0_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_1_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_1_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_1_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire x1_nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_1_b_ready = auto_in_1_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_1_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_1_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_1_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_1_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_1_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_1_c_valid = auto_in_1_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_c_bits_opcode = auto_in_1_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_c_bits_param = auto_in_1_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_1_c_bits_size = auto_in_1_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_1_c_bits_source = auto_in_1_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_1_c_bits_address = auto_in_1_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_1_c_bits_data = auto_in_1_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_1_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_1_e_valid = auto_in_1_e_valid_0; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_1_e_bits_sink = auto_in_1_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_b_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_b_valid = auto_out_1_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_b_bits_opcode = auto_out_1_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_b_bits_param = auto_out_1_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_b_bits_size = auto_out_1_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_b_bits_source = auto_out_1_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] x1_nodeOut_b_bits_address = auto_out_1_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] x1_nodeOut_b_bits_mask = auto_out_1_b_bits_mask_0; // @[Buffer.scala:40:9] wire x1_nodeOut_c_ready = auto_out_1_c_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] x1_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_e_ready = auto_out_1_e_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [6:0] x1_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_sink = auto_out_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_1_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_1_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_1_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_1_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_1_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_1_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_1_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_1_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_1_e_ready_0; // @[Buffer.scala:40:9] wire auto_in_0_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_1_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_1_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_1_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_1_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_1_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_1_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_1_d_ready_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_1_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_1_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_0_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_0_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[Buffer.scala:40:9] assign auto_in_1_b_valid_0 = nodeIn_1_b_valid; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_opcode_0 = nodeIn_1_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_param_0 = nodeIn_1_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_size_0 = nodeIn_1_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_source_0 = nodeIn_1_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_address_0 = nodeIn_1_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_mask_0 = nodeIn_1_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_data_0 = nodeIn_1_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_corrupt_0 = nodeIn_1_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_1_c_ready_0 = nodeIn_1_c_ready; // @[Buffer.scala:40:9] assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_1_e_ready_0 = nodeIn_1_e_ready; // @[Buffer.scala:40:9] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_1_b_ready_0 = x1_nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_1_c_valid_0 = x1_nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_opcode_0 = x1_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_param_0 = x1_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_size_0 = x1_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_source_0 = x1_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_address_0 = x1_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_data_0 = x1_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_corrupt_0 = x1_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_1_e_valid_0 = x1_nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_1_e_bits_sink_0 = x1_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_84 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_85 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_1_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_1_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_1_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_1_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_1_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_1_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_1_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_1_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_1_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_1_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_1_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_1_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_1_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_1_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_1_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_1_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_1_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_1_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_1_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_1_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_1_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s3k7z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s3k7z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d128s2k7z4c nodeOut_a_q_1 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_1_a_ready), .io_enq_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_a_valid), .io_deq_bits_opcode (x1_nodeOut_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_a_bits_param), .io_deq_bits_size (x1_nodeOut_a_bits_size), .io_deq_bits_source (x1_nodeOut_a_bits_source), .io_deq_bits_address (x1_nodeOut_a_bits_address), .io_deq_bits_mask (x1_nodeOut_a_bits_mask), .io_deq_bits_data (x1_nodeOut_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s2k7z4c nodeIn_d_q_1 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_d_ready), .io_enq_valid (x1_nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_1_d_valid), .io_deq_bits_opcode (nodeIn_1_d_bits_opcode), .io_deq_bits_param (nodeIn_1_d_bits_param), .io_deq_bits_size (nodeIn_1_d_bits_size), .io_deq_bits_source (nodeIn_1_d_bits_source), .io_deq_bits_sink (nodeIn_1_d_bits_sink), .io_deq_bits_denied (nodeIn_1_d_bits_denied), .io_deq_bits_data (nodeIn_1_d_bits_data), .io_deq_bits_corrupt (nodeIn_1_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s2k7z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_b_ready), .io_enq_valid (x1_nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_b_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (x1_nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_enq_bits_mask (x1_nodeOut_b_bits_mask), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_1_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_1_b_valid), .io_deq_bits_opcode (nodeIn_1_b_bits_opcode), .io_deq_bits_param (nodeIn_1_b_bits_param), .io_deq_bits_size (nodeIn_1_b_bits_size), .io_deq_bits_source (nodeIn_1_b_bits_source), .io_deq_bits_address (nodeIn_1_b_bits_address), .io_deq_bits_mask (nodeIn_1_b_bits_mask), .io_deq_bits_data (nodeIn_1_b_bits_data), .io_deq_bits_corrupt (nodeIn_1_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s2k7z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_1_c_ready), .io_enq_valid (nodeIn_1_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_1_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_1_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_1_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_1_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_1_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_1_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_c_valid), .io_deq_bits_opcode (x1_nodeOut_c_bits_opcode), .io_deq_bits_param (x1_nodeOut_c_bits_param), .io_deq_bits_size (x1_nodeOut_c_bits_size), .io_deq_bits_source (x1_nodeOut_c_bits_source), .io_deq_bits_address (x1_nodeOut_c_bits_address), .io_deq_bits_data (x1_nodeOut_c_bits_data), .io_deq_bits_corrupt (x1_nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s2k7z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_1_e_ready), .io_enq_valid (nodeIn_1_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_1_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_e_valid), .io_deq_bits_sink (x1_nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_1_b_valid = auto_in_1_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_opcode = auto_in_1_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_param = auto_in_1_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_size = auto_in_1_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_source = auto_in_1_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_address = auto_in_1_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_mask = auto_in_1_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_data = auto_in_1_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_1_b_bits_corrupt = auto_in_1_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_1_c_ready = auto_in_1_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_1_e_ready = auto_in_1_e_ready_0; // @[Buffer.scala:40:9] assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_param = auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_sink = auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_1_b_ready = auto_out_1_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_1_c_valid = auto_out_1_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_opcode = auto_out_1_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_param = auto_out_1_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_size = auto_out_1_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_source = auto_out_1_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_address = auto_out_1_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_data = auto_out_1_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_1_c_bits_corrupt = auto_out_1_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_1_e_valid = auto_out_1_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_1_e_bits_sink = auto_out_1_e_bits_sink_0; // @[Buffer.scala:40:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_147( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_251 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `β†’`: target of arrow is generated by source * * {{{ * (from the other node) * β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€[[InwardNode.uiParams]]─────────────┐ * ↓ β”‚ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ β”‚ * [[InwardNode.accPI]] β”‚ β”‚ β”‚ * β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ ↓ β”‚ * ↓ β”‚ β”‚ β”‚ * (immobilize after elaboration) (inward port from [[OutwardNode]]) β”‚ ↓ β”‚ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] β”‚ * β”‚ β”‚ ↑ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[OutwardNode.doParams]] β”‚ β”‚ * β”‚ β”‚ β”‚ (from the other node) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ └────────┬─────────────── β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ (from the other node) β”‚ ↓ β”‚ * β”‚ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] β”‚ [[MixedNode.edgesIn]]───┐ β”‚ * β”‚ ↑ ↑ β”‚ β”‚ ↓ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ [[MixedNode.in]] β”‚ * β”‚ β”‚ β”‚ β”‚ ↓ ↑ β”‚ * β”‚ (solve star connection) β”‚ β”‚ β”‚ [[MixedNode.bundleIn]]β”€β”€β”˜ β”‚ * β”œβ”€β”€β”€[[MixedNode.resolveStar]]→─┼────────────────────────────── └────────────────────────────────────┐ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.bundleOut]]─┐ β”‚ β”‚ * β”‚ β”‚ β”‚ ↑ ↓ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.out]] β”‚ β”‚ * β”‚ ↓ ↓ β”‚ ↑ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]β”€β”€β”˜ β”‚ β”‚ * β”‚ β”‚ (from the other node) ↑ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.outer.edgeO]] β”‚ β”‚ * β”‚ β”‚ β”‚ (based on protocol) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * (immobilize after elaboration)β”‚ ↓ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.oBindings]]β”€β”˜ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] β”‚ β”‚ * ↑ (inward port from [[OutwardNode]]) β”‚ β”‚ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.accPO]] β”‚ ↓ β”‚ β”‚ β”‚ * (binding node when elaboration) β”‚ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ * β”‚ ↑ β”‚ β”‚ * β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ * β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [3:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [15:0] auto_anon_in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] in_1_a_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] portsAOI_filtered_1_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_anon_in_1_a_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_a_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] in_1_a_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_c_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] portsAOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] _out_0_a_bits_T_4 = 128'h0; // @[Mux.scala:30:73] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [7:0] beatsAI_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsCI_decode_1 = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsCI_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_b_bits_source = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_source = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_e_bits_sink = 4'h0; // @[Xbar.scala:159:18] wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] requestEIO_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_0_bits_source = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [3:0] in_1_a_bits_source = 4'h8; // @[Xbar.scala:159:18] wire [3:0] _in_1_a_bits_source_T = 4'h8; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_source = 4'h8; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [7:0] beatsAI_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [15:0] in_1_b_bits_mask = 16'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire [2:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [15:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [127:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [15:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [127:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [15:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [127:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [3:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [3:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [3:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [3:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [3:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [15:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [2:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[3]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 4'h8; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire [2:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[3]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 4'h8; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [3:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsBO_decode = _beatsBO_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode = _beatsCI_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File Periphery.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.experimental.{noPrefix, IntParam} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools */ sealed trait DebugExportProtocol case object DMI extends DebugExportProtocol case object JTAG extends DebugExportProtocol case object CJTAG extends DebugExportProtocol case object APB extends DebugExportProtocol /** Options for possible debug interfaces */ case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) def cjtag = protocols.contains(CJTAG) def apb = protocols.contains(APB) } case object ExportDebug extends Field(DebugAttachParams()) class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) { val clock = Clock() val reset = Reset() } class DebugIO(implicit val p: Parameters) extends Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO())) val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO) val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32)))) //------------------------------ val ndreset = Output(Bool()) val dmactive = Output(Bool()) val dmactiveAck = Input(Bool()) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool())) } class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO { } class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle { val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool()))) val hartIsInReset = Input(Vec(nComponents, Bool())) } /** Either adds a JTAG DTM to system, and exports a JTAG interface, * or exports the Debug Module Interface (DMI), or exports and hooks up APB, * based on a global parameter. */ trait HasPeripheryDebug { this: BaseSubsystem => private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode domain } lazy val debugOpt = p(DebugModuleKey).map { params => val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes)) tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => slave := master } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } tlDM } val debugNode = debugOpt.map(_.intnode) val psd = InModuleBody { val psd = IO(new PSDIO) psd } val resetctrl = InModuleBody { debugOpt.map { debug => debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size)) debug.module.io.hartIsInReset := resetctrl.hartIsInReset resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} resetctrl } } // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 val debug = InModuleBody { noPrefix(debugOpt.map { debugmod => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), "You cannot have both DMI and JTAG interface in HasPeripheryDebug") require(!(debug.clockeddmi.isDefined && debug.apb.isDefined), "You cannot have both DMI and APB interface in HasPeripheryDebug") require(!(debug.systemjtag.isDefined && debug.apb.isDefined), "You cannot have both APB and JTAG interface in HasPeripheryDebug") debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg } (debug.apb zip apbDebugNodeOpt zip debugmod.module.io.apb_clock zip debugmod.module.io.apb_reset).foreach { case (((io, apb), c ), r) => apb.out(0)._1 <> io c:= io.clock r:= io.reset } debugmod.module.io.debug_reset := debug.reset debugmod.module.io.debug_clock := debug.clock debug.ndreset := debugmod.module.io.ctrl.ndreset debug.dmactive := debugmod.module.io.ctrl.dmactive debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}} // TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down" debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug })} val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) } def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled dtm.io.jtag_clock := sj.jtag.TCK dtm.io.jtag_reset := sj.reset dtm.io.jtag_mfr_id := sj.mfr_id dtm.io.jtag_part_number := sj.part_number dtm.io.jtag_version := sj.version dtm.rf_reset := sj.reset debugOpt.map { outerdebug => outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK outerdebug.module.io.dmi.get.dmiReset := sj.reset } dtm } } /** BlackBox to export DMI interface */ class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Bool()) val debug = new DMIIO val exit = Output(UInt(32.W)) }) def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = { io.clk := tbclk io.reset := tbreset dutio.dmi <> io.debug dutio.dmiClock := tbclk dutio.dmiReset := tbreset tbsuccess := io.exit === 1.U assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimDTM.v") addResource("/csrc/SimDTM.cc") } /** BlackBox to export JTAG interface */ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val jtag = new JTAGIO(hasTRSTn = true) val enable = Input(Bool()) val init_done = Input(Bool()) val exit = Output(UInt(32.W)) }) def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = { dutio.TCK := io.jtag.TCK dutio.TMS := io.jtag.TMS dutio.TDI := io.jtag.TDI io.jtag.TDO := dutio.TDO io.clock := tbclock io.reset := tbreset io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.init_done := init_done // Success is determined by the gdbserver // which is controlling this simulation. tbsuccess := io.exit === 1.U assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimJTAG.v") addResource("/csrc/SimJTAG.cc") addResource("/csrc/remote_bitbang.h") addResource("/csrc/remote_bitbang.cc") } object Debug { def connectDebug( debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO], psdio: PSDIO, c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode())) (implicit p: Parameters): Unit = { connectDebugClockAndReset(debugOpt, c) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }} debugOpt.map { debug => debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } debug.systemjtag.foreach { sj => val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out) sj.reset := r.asAsyncReset sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) sj.version := p(JtagDTMKey).idcodeVersion.U(4.W) } debug.apb.foreach { apb => require(false, "No support for connectDebug for an APB debug connection.") } psdio.psd.foreach { _ <> psd } debug.disableDebug.foreach { x => x := false.B } } } def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { debugOpt.foreach { debug => val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) | debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) | debug.apb.map(_.reset.asBool).getOrElse(false.B) connectDebugClockHelper(debug, dmi_reset, c, sync) } } def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { val debug_reset = Wire(Bool()) withClockAndReset(c, dmi_reset) { val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset debug_reset := debug_reset_syncd } // Need to clock DM during debug_reset because of synchronous reset, so keep // the clock alive for one cycle after debug_reset asserts to action this behavior. // The unit should also be clocked when dmactive is high. withClockAndReset(c, debug_reset.asAsyncReset) { val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive val clock_en = RegNext(next=dmactiveAck, init=true.B) val gated_clock = if (!p(DebugModuleKey).get.clockGate) c else ClockGate(c, clock_en, "debug_clock_gate") debug.clock := gated_clock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset) debug.dmactiveAck := dmactiveAck } } def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = { psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } ) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }} debugOpt.map { debug => debug.clock := true.B.asClock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset) debug.systemjtag.foreach { sj => sj.jtag.TCK := true.B.asClock sj.jtag.TMS := true.B sj.jtag.TDI := true.B sj.jtag.TRSTn.foreach { r => r := true.B } sj.reset := true.B.asAsyncReset sj.mfr_id := 0.U sj.part_number := 0.U sj.version := 0.U } debug.clockeddmi.foreach { d => d.dmi.req.valid := false.B d.dmi.req.bits.addr := 0.U d.dmi.req.bits.data := 0.U d.dmi.req.bits.op := 0.U d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B.asAsyncReset } debug.apb.foreach { apb => apb.clock := false.B.asClock apb.reset := true.B.asAsyncReset apb.pready := false.B apb.pslverr := false.B apb.prdata := 0.U apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser)) apb.psel := false.B apb.penable := false.B } debug.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } debug.disableDebug.foreach { x => x := false.B } debug.dmactiveAck := false.B debug.ndreset }.getOrElse(false.B) } } File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * */ case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) || (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit */ class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get || !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get || errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File CanHaveClockTap.scala: package chipyard.clocking import chisel3._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO") val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) clockTap := ClockGroup() := allClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { val clock_tap = IO(Output(Clock())) clock_tap := node.in.head._1.clock clock_tap }} } File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node) (out_xbar.node :*= fixer_node :*= TLBuffer(pa.buffer) :*= (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) :*= in_xbar.node) } .getOrElse { TLXbar() :*= fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File BankedCoherenceParams.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.interrupts.IntOutwardNode import freechips.rocketchip.tilelink.{ TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode } import freechips.rocketchip.util.Location import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. */ case object CacheBlockBytes extends Field[Int](64) /** LLC Broadcast Hub configuration */ case object BroadcastKey extends Field(BroadcastParams()) case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false, controlAddress: Option[BigInt] = None, filterFactory: TLBroadcast.ProbeFilterFactory = BroadcastFilter.factory) /** Coherence manager configuration */ case object SubsystemBankedCoherenceKey extends Field(BankedCoherenceParams()) case class ClusterBankedCoherenceKey(clusterId: Int) extends Field(BankedCoherenceParams(nBanks=0)) case class BankedCoherenceParams( nBanks: Int = 1, coherenceManager: CoherenceManagerInstantiationFn = broadcastManager ) { require (isPow2(nBanks) || nBanks == 0) } case class CoherenceManagerWrapperParams( blockBytes: Int, beatBytes: Int, nBanks: Int, name: String, dtsFrequency: Option[BigInt] = None) (val coherenceManager: CoherenceManagerInstantiationFn) extends HasTLBusParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = { val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context)) cmWrapper.suggestName(loc.name + "_wrapper") cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) } context.tlBusWrapperLocationMap += (loc -> cmWrapper) cmWrapper } } class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) { val (tempIn, tempOut, halt) = params.coherenceManager(context) private val coherent_jbar = LazyModule(new TLJbar) def busView: TLEdge = coherent_jbar.node.edges.out.head val inwardNode = tempIn :*= coherent_jbar.node val builtInDevices = BuiltInDevices.none val prefixNode = None private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) :*= node } val outwardNode = banked(tempOut) } object CoherenceManagerWrapper { type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode]) def broadcastManagerFn( name: String, location: HierarchicalLocation, controlPortsSlaveWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( lineBytes = p(CacheBlockBytes), numTrackers = nTrackers, bufferless = bufferless, control = controlAddress.map(x => TLBroadcastControlParams(AddressSet(x, 0xfff), cbus.beatBytes)), filterFactory = filterFactory))) bh.suggestName(name) bh.controlNode.foreach { _ := cbus.coupleTo(s"${name}_ctrl") { TLBuffer(1) := TLFragmenter(cbus) := _ } } bh.intNode.foreach { context.ibus.fromSync := _ } (bh.node, bh.node, None) } val broadcastManager = broadcastManagerFn("broadcast", InSystem, CBUS) val incoherentManager: CoherenceManagerInstantiationFn = { _ => val node = TLNameNode("no_coherence_manager") (node, node, None) } } File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /** For determining static tile id */ case object NumTiles extends Field[Int](0) /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. */ case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. */ case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. */ case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /** These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. */ trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /** tileHartIdNode is used to collect publishers and subscribers of hartids. */ val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. */ val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */ val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */ val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. */ val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. */ val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. */ trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. */ trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /** Narrow waist through which all tiles are intended to pass while being instantiated. */ def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /** Connect the port where the tile is the master to a TileLink interconnect. */ def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. */ def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } /** Connect the various interrupts sent to and and raised by the tile. */ def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */ def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /** Function to handle all trace crossings when tile is instantiated inside domains */ def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File BusWrapper.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} import freechips.rocketchip.prci.{ ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing } import freechips.rocketchip.subsystem.{ HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, CanInstantiateWithinContextThatHasTileLinkLocations } import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC */ trait HasTLBusParams { def beatBytes: Int def blockBytes: Int def beatBits: Int = beatBytes * 8 def blockBits: Int = blockBytes * 8 def blockBeats: Int = blockBytes / beatBytes def blockOffset: Int = log2Up(blockBytes) def dtsFrequency: Option[BigInt] def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0)) require (isPow2(beatBytes)) require (isPow2(blockBytes)) } abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters) extends ClockDomain with HasTLBusParams with CanHaveBuiltInDevices { private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups") private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true }) val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here val clockNode = clockGroup.node val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt))) clockGroup.node := clockGroupAggregator.node fixedClockNode := clockGroup.node // first member of group is always domain's own clock clockSinkNode := fixedClockNode InModuleBody { // make sure the above connections work properly because mismatched-by-name signals will just be ignored. (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) => require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}") } } def clockBundle = clockSinkNode.in.head._1 def beatBytes = params.beatBytes def blockBytes = params.blockBytes def dtsFrequency = params.dtsFrequency val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption /* If you violate this requirement, you will have a rough time. * The codebase is riddled with the assumption that this is true. */ require(blockBytes >= beatBytes) def inwardNode: TLInwardNode def outwardNode: TLOutwardNode def busView: TLEdge def prefixNode: Option[BundleBridgeNode[UInt]] def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) def generateSynchronousDomain(domainName: String): ClockSinkDomain = { val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) def to[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } } } def from[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } } } def coupleTo[T](name: String)(gen: TLOutwardNode => T): T = to(name) { gen(TLNameNode("tl") :*=* outwardNode) } def coupleFrom[T](name: String)(gen: TLInwardNode => T): T = from(name) { gen(inwardNode :*=* TLNameNode("tl")) } def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleTo(s"bus_named_${bus.busName}") { bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _ } } def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleFrom(s"bus_named_${bus.busName}") { _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType) } } } trait TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper } trait TLBusWrapperConnectionLike { val xType: ClockCrossingType def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { /** Backwards compatibility factory for master driving clock and slave setting cardinality */ def crossTo( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } /** Backwards compatibility factory for slave driving clock and master setting cardinality */ def crossFrom( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /** Factory for making generic connections between TLBusWrappers */ def apply (xType: ClockCrossingType = NoCrossing, driveClockFromMaster: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView, masterNodeView, inject) } } /** TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers. * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, * otherwise have either the master or the slave bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. * - masterNodeView: programmatic control of the specific attachment point within the master bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. */ class TLBusWrapperConnection (val xType: ClockCrossingType, val driveClockFromMaster: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { val masterTLBus = context.locateTLBusWrapper(master) val slaveTLBus = context.locateTLBusWrapper(slave) def bindClocks(implicit p: Parameters) = driveClockFromMaster match { case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_QUERY => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) case BIND_STAR => slaveNodeView(slaveTLBus, p) :*= TLWidthWidget(masterTLBus.beatBytes) :*= inject(p) :*= masterNodeView(masterTLBus, p) case BIND_FLEX => slaveNodeView(slaveTLBus, p) :*=* TLWidthWidget(masterTLBus.beatBytes) :*=* inject(p) :*=* masterNodeView(masterTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } } class TLBusWrapperTopology( val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)], val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)] ) extends CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations { def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } } } trait HasTLXbarPhy { this: TLBusWrapper => private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar") override def shouldBeInlined = xbar.node.circuitIdentity def inwardNode: TLInwardNode = xbar.node def outwardNode: TLOutwardNode = xbar.node def busView: TLEdge = xbar.node.edges.in.head } case class AddressAdjusterWrapperParams( blockBytes: Int, beatBytes: Int, replication: Option[ReplicatedRegion], forceLocal: Seq[AddressSet] = Nil, localBaseAddressDefault: Option[BigInt] = None, policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile, ordered: Boolean = true ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = { val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name)) aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> aaWrapper) aaWrapper } } class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) } private val viewNode = TLIdentityNode() val inwardNode: TLInwardNode = address_adjuster.map(_.node :*=* TLFIFOFixer(params.policy) :*=* viewNode).getOrElse(viewNode) def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode) def busView: TLEdge = viewNode.edges.in.head val prefixNode = address_adjuster.map { a => a.prefix := addressPrefixNexusNode addressPrefixNexusNode } val builtInDevices = BuiltInDevices.none override def shouldBeInlined = !params.replication.isDefined } case class TLJBarWrapperParams( blockBytes: Int, beatBytes: Int ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = { val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name)) jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> jbarWrapper) jbarWrapper } } class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val jbar = LazyModule(new TLJbar) val inwardNode: TLInwardNode = jbar.node val outwardNode: TLOutwardNode = jbar.node def busView: TLEdge = jbar.node.edges.in.head val prefixNode = None val builtInDevices = BuiltInDevices.none override def shouldBeInlined = jbar.node.circuitIdentity } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Scratchpad.scala: package testchipip.soc import chisel3._ import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.resources.{DiplomacyUtils} import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters} import scala.collection.immutable.{ListMap} case class BankedScratchpadParams( base: BigInt, size: BigInt, busWhere: TLBusWrapperLocation = SBUS, banks: Int = 4, subBanks: Int = 2, name: String = "banked-scratchpad", disableMonitors: Boolean = false, buffer: BufferParams = BufferParams.none, outerBuffer: BufferParams = BufferParams.none, dtsEnabled: Boolean = false ) case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil) class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { val mask = (subBanks - 1) * p(CacheBlockBytes) val xbar = TLXbar() (0 until subBanks).map { sb => val ram = LazyModule(new TLRAM( address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask), beatBytes = beatBytes, devOverride = Some(devOverride)) { override lazy val desiredName = s"TLRAM_ScratchpadBank" }) ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar } override lazy val desiredName = "ScratchpadBank" } trait CanHaveBankedScratchpad { this: BaseSubsystem => p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) => val bus = locateTLBusWrapper(params.busWhere) require (params.subBanks >= 1) val name = params.name val banks = params.banks val bankStripe = p(CacheBlockBytes)*params.subBanks val mask = (params.banks-1)*bankStripe val device = new MemoryDevice { override def describe(resources: ResourceBindings): Description = { Description(describeName("memory", resources), ListMap( "reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList, "device_type" -> Seq(ResourceString("memory")), "status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled")) )) } } def genBanks()(implicit p: Parameters) = (0 until banks).map { b => val bank = LazyModule(new ScratchpadBank( params.subBanks, AddressSet(params.base + bankStripe * b, params.size - 1 - mask), bus.beatBytes, device, params.buffer)) bank.clockNode := bus.fixedClockNode bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ } } if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks() } } File ClockGroupCombiner.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ object ClockGroupCombiner { def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { LazyModule(new ClockGroupCombiner()).node } } case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => { case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) /** This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey * The ClockGroupCombinersKey contains a list of tuples of: * - The name of the combined group * - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node * This node will fail if * - Multiple grouping functions match a single clock group * - A grouping function matches zero clock groups * - A grouping function matches clock groups with different requested frequncies */ class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule { val combiners = p(ClockGroupCombinerKey) val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m } val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u => var i = 0 val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) => val (g, r) = rest.partition(c(_)) val name = combiners(i)._1 i = i + 1 require(g.size >= 1) val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group '$name' has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) } ClockGroupSinkParameters( name = u.name, members = grouped ++ rest ) } val node = ClockGroupAdapterNode(sourceFn, sinkFn) lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, oe), (i, ie)) => { val inMap = (i.member.data zip ie.sink.members).map { case (id, im) => im.name.get -> id }.toMap (o.member.data zip oe.sink.members).map { case (od, om) => val matches = combiners.filter(c => c._2(om)) require(matches.size <= 1) if (matches.size == 0) { od := inMap(om.name.get) } else { od := inMap(matches(0)._1) } } } } } } File SinkNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, IO} import org.chipsalliance.diplomacy.ValName /** A node which represents a node in the graph which has only inward edges, no outward edges. * * A [[SinkNode]] cannot appear cannot appear right of a `:=`, `:*=`, `:=*`, or `:*=*` * * There are no "Mixed" [[SinkNode]]s because each one only has an inward side. */ class SinkNode[D, U, EO, EI, B <: Data]( imp: NodeImp[D, U, EO, EI, B] )(pi: Seq[U] )( implicit valName: ValName) extends MixedNode(imp, imp) { override def description = "sink" protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { def resolveStarInfo: String = s"""$context |$bindingInfo |number of known := bindings to inward nodes: $iKnown |number of known := bindings to outward nodes: $oKnown |number of binding queries from inward nodes: $iStars |number of binding queries from outward nodes: $oStars |${pi.size} inward parameters: [${pi.map(_.toString).mkString(",")}] |""".stripMargin require( iStars <= 1, s"""Diplomacy has detected a problem with your graph: |The following node appears left of a :*= $iStars times; at most once is allowed. |$resolveStarInfo |""".stripMargin ) require( oStars == 0, s"""Diplomacy has detected a problem with your graph: |The following node cannot appear right of a :=* |$resolveStarInfo |""".stripMargin ) require( oKnown == 0, s"""Diplomacy has detected a problem with your graph: |The following node cannot appear right of a := |$resolveStarInfo |""".stripMargin ) if (iStars == 0) require( pi.size == iKnown, s"""Diplomacy has detected a problem with your graph: |The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. |Either the number of inward := bindings should be exactly equal to the number of sink, or connect this node on the left-hand side of a :*= |$resolveStarInfo |""".stripMargin ) else require( pi.size >= iKnown, s"""Diplomacy has detected a problem with your graph: |The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. |To resolve :*=, size of inward parameters can not be less than bindings. |$resolveStarInfo |""".stripMargin ) (pi.size - iKnown, 0) } protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq() protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi def makeIOs( )( implicit valName: ValName ): HeterogeneousBag[B] = { val bundles = this.in.map(_._1) val ios = IO(new HeterogeneousBag(bundles)) ios.suggestName(valName.value) bundles.zip(ios).foreach { case (bundle, io) => io <> bundle } ios } } File DigitalTop.scala: package chipyard import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // BOOM and/or Rocket Top Level Systems // ------------------------------------ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop File FrontBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = { val fbus = LazyModule(new FrontBus(this, loc.name)) fbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> fbus) fbus } } class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) with HasTLXbarPhy { val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) val prefixNode = None } File PeripheryTLSerial.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.util.{ClockedIO} import testchipip.soc.{OBUS} // Parameters for a read-only-memory that appears over serial-TL case class ManagerROMParams( address: BigInt = 0x20000, size: Int = 0x10000, contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE // Parameters for a read/write memory that appears over serial-TL case class ManagerRAMParams( address: BigInt, size: BigInt) // Parameters for a coherent cacheable read/write memory that appears over serial-TL case class ManagerCOHParams( address: BigInt, size: BigInt) // Parameters for a set of memory regions that appear over serial-TL case class SerialTLManagerParams( memParams: Seq[ManagerRAMParams] = Nil, romParams: Seq[ManagerROMParams] = Nil, cohParams: Seq[ManagerCOHParams] = Nil, isMemoryDevice: Boolean = false, sinkIdBits: Int = 8, totalIdBits: Int = 8, cacheIdBits: Int = 2, slaveWhere: TLBusWrapperLocation = OBUS ) // Parameters for a TL client which may probe this system over serial-TL case class SerialTLClientParams( totalIdBits: Int = 8, cacheIdBits: Int = 2, masterWhere: TLBusWrapperLocation = FBUS, supportsProbe: Boolean = false ) // The SerialTL can be configured to be bidirectional if serialTLManagerParams is set case class SerialTLParams( client: Option[SerialTLClientParams] = None, manager: Option[SerialTLManagerParams] = None, phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(), bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS) case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil) trait CanHavePeripheryTLSerial { this: BaseSubsystem => private val portName = "serial-tl" val tlChannels = 5 val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) => val name = s"serial_tl_$sid" lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere)) lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere)) val clientPortParams = params.client.map { c => TLMasterPortParameters.v1( clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1( name = s"serial_tl_${sid}_${i}", sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)), supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none )} )} val managerPortParams = params.manager.map { m => val memParams = m.memParams val romParams = m.romParams val cohParams = m.cohParams val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil) val romDevice = new SimpleDevice("lbwif-readonly", Nil) val blockBytes = manager_bus.get.blockBytes TLSlavePortParameters.v1( managers = memParams.map { memParams => TLSlaveParameters.v1( address = AddressSet.misaligned(memParams.address, memParams.size), resources = memDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )} ++ romParams.map { romParams => TLSlaveParameters.v1( address = List(AddressSet(romParams.address, romParams.size-1)), resources = romDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), fifoId = Some(0) )} ++ cohParams.map { cohParams => TLSlaveParameters.v1( address = AddressSet.misaligned(cohParams.address, cohParams.size), regionType = RegionType.TRACKED, // cacheable executable = true, supportsAcquireT = TransferSizes(1, blockBytes), supportsAcquireB = TransferSizes(1, blockBytes), supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )}, beatBytes = manager_bus.get.beatBytes, endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits), minLatency = 1 ) } val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid"))) serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined, s"Manager bus ${manager_bus.get.busName} must provide a frequency") if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined, s"Client bus ${client_bus.get.busName} must provide a frequency") if (manager_bus.isDefined && client_bus.isDefined) { val managerFreq = manager_bus.get.dtsFrequency.get val clientFreq = client_bus.get.dtsFrequency.get require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq") } val serdesser = serial_tl_domain { LazyModule(new TLSerdesser( flitWidth = params.phyParams.flitWidth, clientPortParams = clientPortParams, managerPortParams = managerPortParams, bundleParams = params.bundleParams, nameSuffix = Some(name) )) } serdesser.managerNode.foreach { managerNode => val maxClients = 1 << params.manager.get.cacheIdBits val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits) manager_bus.get.coupleTo(s"port_named_${name}_out") { (managerNode := TLProbeBlocker(p(CacheBlockBytes)) := TLSourceAdjuster(maxClients, maxIdsPerClient) := TLSourceCombiner(maxIdsPerClient) := TLWidthWidget(manager_bus.get.beatBytes) := _) } } serdesser.clientNode.foreach { clientNode => client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode } } // If we provide a clock, generate a clock domain for the outgoing clock val serial_tl_clock_freqMHz = params.phyParams match { case params: InternalSyncSerialPhyParams => Some(params.freqMHz) case params: ExternalSyncSerialPhyParams => None case params: SourceSyncSerialPhyParams => Some(params.freqMHz) } val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f => serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) } } serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode) val inner_io = serial_tl_domain { InModuleBody { val inner_io = IO(params.phyParams.genIO).suggestName(name) inner_io match { case io: InternalSyncPhitIO => { // Outer clock comes from the clock node. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = serial_tl_clock_node.get.in.head._1.clock io.clock_out := outer_clock val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: ExternalSyncPhitIO => { // Outer clock comes from the IO. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = io.clock_in val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: SourceSyncPhitIO => { // 3 clock domains - // - serdesser's "Inner clock": synchronizes signals going to the digital logic // - outgoing clock: synchronizes signals going out // - incoming clock: synchronizes signals coming in val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool) val incoming_clock = io.clock_in val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool) io.clock_out := outgoing_clock io.reset_out := outgoing_reset.asAsyncReset val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams)) phy.io.incoming_clock := incoming_clock phy.io.incoming_reset := incoming_reset phy.io.outgoing_clock := outgoing_clock phy.io.outgoing_reset := outgoing_reset phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.inner_ser <> serdesser.module.io.ser phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth)) } } inner_io }} val outer_io = InModuleBody { val outer_io = IO(params.phyParams.genIO).suggestName(name) outer_io <> inner_io outer_io } val inner_debug_io = serial_tl_domain { InModuleBody { val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") inner_debug_io := serdesser.module.io.debug inner_debug_io }} val outer_debug_io = InModuleBody { val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") outer_debug_io := inner_debug_io outer_debug_io } (serdesser, outer_io, outer_debug_io) }.unzip3 } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File InterruptBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain} import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC */ class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { override def shouldBeInlined = true val int_bus = LazyModule(new IntXbar) // Interrupt crossbar private val int_in_xing = this.crossIn(int_bus.intnode) private val int_out_xing = this.crossOut(int_bus.intnode) def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) :=* IntNameNode(name) def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) :*= int_out_xing(xing) def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3)) def fromRational: IntInwardNode = from(None)(RationalCrossing()) def fromSync: IntInwardNode = int_bus.intnode def toPLIC: IntOutwardNode = int_bus.intnode } /** Specifies the number of external interrupts */ case object NExtTopInterrupts extends Field[Int](0) /** This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below * synchronization wiring child traits should be used. */ abstract trait HasExtInterrupts { this: BaseSubsystem => private val device = new Device with DeviceInterrupts { def describe(resources: ResourceBindings): Description = { Description("soc/external-interrupts", describeInterrupts(resources)) } } val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) } /** This trait should be used if the External Interrupts have NOT * already been synchronized to the Periphery (PLIC) Clock. */ trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromAsync := extInterrupts } } } /** This trait can be used if the External Interrupts have already been synchronized * to the Periphery (PLIC) Clock. */ trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromSync := extInterrupts } } } /** Common io name and methods for propagating or tying off the port bundle */ trait HasExtInterruptsBundle { val interrupts: UInt def tieOffInterrupts(dummy: Int = 1): Unit = { interrupts := 0.U } } /** This trait performs the translation from a UInt IO into Diplomatic Interrupts. * The wiring must be done in the concrete LazyModuleImp. */ trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle { val outer: HasExtInterrupts val interrupts = IO(Input(UInt(outer.nExtInterrupts.W))) outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) } } File BundleBridgeSink.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output} import chisel3.reflect.DataMirror import chisel3.reflect.DataMirror.internal.chiselTypeClone import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.SinkNode case class BundleBridgeSink[T <: Data]( genOpt: Option[() => T] = None )( implicit valName: ValName) extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) { def bundle: T = in(0)._1 private def inferOutput = getElements(bundle).forall { elt => DataMirror.directionOf(elt) == ActualDirection.Unspecified } def makeIO( )( implicit valName: ValName ): T = { val io: T = IO( if (inferOutput) Output(chiselTypeOf(bundle)) else chiselTypeClone(bundle) ) io.suggestName(valName.value) io <> bundle io } def makeIO(name: String): T = makeIO()(ValName(name)) } object BundleBridgeSink { def apply[T <: Data]( )( implicit valName: ValName ): BundleBridgeSink[T] = { BundleBridgeSink(None) } } File Buses.scala: package constellation.soc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import constellation.noc.{NoCParams} import constellation.protocol._ import scala.collection.immutable.{ListMap} case class ConstellationSystemBusParams( sbusParams: SystemBusParams, tlNoCParams: TLNoCParams, inlineNoC: Boolean ) extends TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper] )(implicit p: Parameters): ConstellationSystemBus = { val constellation = LazyModule(new ConstellationSystemBus( sbusParams, tlNoCParams, loc.name, context, inlineNoC)) constellation.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> constellation) constellation } } class ConstellationSystemBus( sbus_params: SystemBusParams, noc_params: TLNoCParams, name: String, context: HasTileLinkLocations, inlineNoC: Boolean )(implicit p: Parameters) extends TLBusWrapper(sbus_params, name) { private val replicator = sbus_params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } override def shouldBeInlined = inlineNoC private val system_bus_noc = noc_params match { case params: GlobalTLNoCParams => context.asInstanceOf[CanHaveGlobalNoC].globalNoCDomain { LazyModule(new TLGlobalNoC(params, name)) } case params: SimpleTLNoCParams => LazyModule(new TLNoC(params, name, inlineNoC)) case params: SplitACDxBETLNoCParams => LazyModule(new TLSplitACDxBENoC(params, name, inlineNoC)) } val inwardNode: TLInwardNode = (system_bus_noc.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())) val outwardNode: TLOutwardNode = system_bus_noc.node def busView: TLEdge = system_bus_noc.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(sbus_params, outwardNode) } case class ConstellationMemoryBusParams( mbusParams: MemoryBusParams, tlNoCParams: TLNoCParams, inlineNoC: Boolean ) extends TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper] )(implicit p: Parameters): ConstellationMemoryBus = { val constellation = LazyModule(new ConstellationMemoryBus( mbusParams, tlNoCParams, loc.name, context, inlineNoC)) constellation.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> constellation) constellation } } class ConstellationMemoryBus(mbus_params: MemoryBusParams, noc_params: TLNoCParams, name: String, context: HasTileLinkLocations, inlineNoC: Boolean) (implicit p: Parameters) extends TLBusWrapper(mbus_params, name) { private val replicator = mbus_params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val memory_bus_noc = noc_params match { case params: GlobalTLNoCParams => context.asInstanceOf[CanHaveGlobalNoC].globalNoCDomain { LazyModule(new TLGlobalNoC(params, name)) } case params: SimpleTLNoCParams => LazyModule(new TLNoC(params, name, inlineNoC)) case params: SplitACDxBETLNoCParams => LazyModule(new TLSplitACDxBENoC(params, name, inlineNoC)) } val inwardNode: TLInwardNode = replicator.map(memory_bus_noc.node :*=* TLFIFOFixer(TLFIFOFixer.all) :*=* _.node) .getOrElse(memory_bus_noc.node :*=* TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() :*= memory_bus_noc.node def busView: TLEdge = memory_bus_noc.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(mbus_params, outwardNode) } case class ConstellationPeripheryBusParams( pbusParams: PeripheryBusParams, tlNoCParams: TLNoCParams, inlineNoC: Boolean ) extends TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper] )(implicit p: Parameters): ConstellationPeripheryBus = { val constellation = LazyModule(new ConstellationPeripheryBus(pbusParams, tlNoCParams, loc.name, context, inlineNoC)) constellation.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> constellation) constellation } } class ConstellationPeripheryBus(pbus_params: PeripheryBusParams, noc_params: TLNoCParams, name: String, context: HasTileLinkLocations, inlineNoC: Boolean) (implicit p: Parameters) extends TLBusWrapper(pbus_params, name) { private val replicator = pbus_params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } def genNoC()(implicit valName: ValName): TLNoCLike = noc_params match { case params: GlobalTLNoCParams => context.asInstanceOf[CanHaveGlobalNoC].globalNoCDomain { LazyModule(new TLGlobalNoC(params, name)) } case params: SimpleTLNoCParams => LazyModule(new TLNoC(params, name, inlineNoC)) case params: SplitACDxBETLNoCParams => LazyModule(new TLSplitACDxBENoC(params, name, inlineNoC)) } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = pbus_params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar) val out_noc = genNoC() val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node) (out_noc.node :*= fixer_node :*= TLBuffer(pa.buffer) :*= (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic) }) :*= in_xbar.node) } .getOrElse { val noc = genNoC() noc.node :*= fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(pbus_params, outwardNode) }
module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_1, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_2, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_3, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_4, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_5, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_6, // @[Periphery.scala:116:25] input resetctrl_hartIsInReset_7, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_3_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_3_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_3_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_3_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_3_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_3_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_3_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_3_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_3_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_3_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_3_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_3_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_3_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_3_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_3_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_3_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_3_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_3_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_3_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_3_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_3_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_3_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_3_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_3_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_3_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_3_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_3_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_3_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_3_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_3_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_3_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_3_r_bits_last, // @[SinkNode.scala:76:21] input mem_axi4_2_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_2_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_2_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_2_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_2_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_2_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_2_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_2_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_2_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_2_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_2_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_2_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_2_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_2_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_2_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_2_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_2_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_2_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_2_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_2_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_2_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_2_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_2_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_2_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_2_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_2_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_2_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_2_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_2_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_2_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_2_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_2_r_bits_last, // @[SinkNode.scala:76:21] input mem_axi4_1_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_1_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_1_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_1_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_1_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_1_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_1_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_1_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_1_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_1_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_1_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_1_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_1_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_1_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_1_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_1_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_1_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_1_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_1_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_1_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_1_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_1_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_1_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_1_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_1_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_1_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_1_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_1_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_1_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_1_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_1_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_1_r_bits_last, // @[SinkNode.scala:76:21] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [5:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_7_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_6_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_5_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_4_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_3_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_2_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_1_sync_0; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_0_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_15_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_14_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_13_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_12_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_11_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_10_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_9_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_8_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_7_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_6_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_5_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_4_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_3_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_2_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_1_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_0_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire [2:0] _tileHartIdNexusNode_auto_out_7; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_6; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_5; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_4; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_3; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_2; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_1; // @[HasTiles.scala:75:39] wire [2:0] _tileHartIdNexusNode_auto_out_0; // @[HasTiles.scala:75:39] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_7_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_6_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [4:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_3_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_2_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_1_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_0_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[Buses.scala:69:35] wire [5:0] _mbus_auto_buffer_out_a_bits_source; // @[Buses.scala:69:35] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[Buses.scala:69:35] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[Buses.scala:69:35] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[Buses.scala:69:35] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[Buses.scala:69:35] wire _mbus_auto_buffer_out_d_ready; // @[Buses.scala:69:35] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[Buses.scala:69:35] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_3_a_ready; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_3_d_valid; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_opcode; // @[Buses.scala:69:35] wire [1:0] _mbus_auto_bus_xing_in_3_d_bits_param; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_3_d_bits_size; // @[Buses.scala:69:35] wire [3:0] _mbus_auto_bus_xing_in_3_d_bits_source; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_3_d_bits_sink; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_3_d_bits_denied; // @[Buses.scala:69:35] wire [63:0] _mbus_auto_bus_xing_in_3_d_bits_data; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_3_d_bits_corrupt; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_2_a_ready; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_2_d_valid; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_opcode; // @[Buses.scala:69:35] wire [1:0] _mbus_auto_bus_xing_in_2_d_bits_param; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_2_d_bits_size; // @[Buses.scala:69:35] wire [3:0] _mbus_auto_bus_xing_in_2_d_bits_source; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_2_d_bits_sink; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_2_d_bits_denied; // @[Buses.scala:69:35] wire [63:0] _mbus_auto_bus_xing_in_2_d_bits_data; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_2_d_bits_corrupt; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_1_a_ready; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_1_d_valid; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_opcode; // @[Buses.scala:69:35] wire [1:0] _mbus_auto_bus_xing_in_1_d_bits_param; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_1_d_bits_size; // @[Buses.scala:69:35] wire [3:0] _mbus_auto_bus_xing_in_1_d_bits_source; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_1_d_bits_sink; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_1_d_bits_denied; // @[Buses.scala:69:35] wire [63:0] _mbus_auto_bus_xing_in_1_d_bits_data; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_1_d_bits_corrupt; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_0_a_ready; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_0_d_valid; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_opcode; // @[Buses.scala:69:35] wire [1:0] _mbus_auto_bus_xing_in_0_d_bits_param; // @[Buses.scala:69:35] wire [2:0] _mbus_auto_bus_xing_in_0_d_bits_size; // @[Buses.scala:69:35] wire [3:0] _mbus_auto_bus_xing_in_0_d_bits_source; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_0_d_bits_sink; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_0_d_bits_denied; // @[Buses.scala:69:35] wire [63:0] _mbus_auto_bus_xing_in_0_d_bits_data; // @[Buses.scala:69:35] wire _mbus_auto_bus_xing_in_0_d_bits_corrupt; // @[Buses.scala:69:35] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[Buses.scala:111:35] wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[Buses.scala:111:35] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[Buses.scala:111:35] wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[Buses.scala:111:35] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[Buses.scala:111:35] wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[Buses.scala:111:35] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[Buses.scala:111:35] wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[Buses.scala:111:35] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[Buses.scala:111:35] wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[Buses.scala:111:35] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[Buses.scala:111:35] wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[Buses.scala:111:35] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[Buses.scala:111:35] wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[Buses.scala:111:35] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[Buses.scala:111:35] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[Buses.scala:111:35] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[Buses.scala:111:35] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[Buses.scala:111:35] wire _cbus_auto_bus_xing_in_a_ready; // @[Buses.scala:111:35] wire _cbus_auto_bus_xing_in_d_valid; // @[Buses.scala:111:35] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[Buses.scala:111:35] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[Buses.scala:111:35] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[Buses.scala:111:35] wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[Buses.scala:111:35] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[Buses.scala:111:35] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[Buses.scala:111:35] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[Buses.scala:111:35] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[Buses.scala:111:35] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_7_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_6_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_5_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_4_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_a_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_b_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_address; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_c_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_d_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_e_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_3_e_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_a_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_b_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_address; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_c_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_d_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_e_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_2_e_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_a_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_b_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_address; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_c_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_d_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_e_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_1_e_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_a_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_b_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_param; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_source; // @[Buses.scala:25:35] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_address; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_c_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_d_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_e_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_0_e_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[Buses.scala:25:35] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[Buses.scala:25:35] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[Buses.scala:25:35] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[Buses.scala:25:35] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[Buses.scala:25:35] wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[Buses.scala:25:35] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[Buses.scala:25:35] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[Buses.scala:25:35] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[Buses.scala:25:35] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_8_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_8_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_7_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_7_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_6_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_6_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_5_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_5_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_4_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_4_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_3_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_3_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[Buses.scala:25:35] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[Buses.scala:25:35] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[Buses.scala:25:35] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[Buses.scala:25:35] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_29( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File LoadSegmenter.scala: package saturn.mem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ class LoadSegmenter(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val valid = Input(Bool()) val done = Output(Bool()) val op = Input(new VectorMemMacroOp) val compactor = Decoupled(new CompactorReq(dLenB)) val compactor_data = Input(UInt(dLen.W)) val resp = Decoupled(new Bundle { val data = UInt(dLen.W) val debug_id = UInt(debugIdSz.W) }) }) val segbuf = Module(new LoadSegmentBuffer(vParams.doubleBufferSegments)) val r_eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val r_head = RegInit(true.B) val r_sidx = Reg(UInt(3.W)) val eidx = Mux(r_head, io.op.vstart, r_eidx) val sidx = Mux(r_head, io.op.segstart, r_sidx) val mem_size = io.op.elem_size val incr = (dLenB.U - (Mux(io.op.seg_nf === 0.U, eidx, sidx) << mem_size)(dLenOffBits-1,0)) >> mem_size val eidx_incr = Mux(io.op.seg_nf =/= 0.U, 1.U, incr) val sidx_incr = incr val next_eidx = eidx +& eidx_incr val next_sidx = sidx +& sidx_incr val sidx_tail = next_sidx > io.op.seg_nf val eidx_tail = next_eidx >= io.op.vl when (io.op.seg_nf === 0.U) { io.compactor.valid := io.valid && !segbuf.io.busy && io.resp.ready io.compactor.bits.head := eidx << mem_size io.compactor.bits.tail := Mux(eidx_tail, io.op.vl << mem_size, 0.U) } .otherwise { io.compactor.valid := io.valid && segbuf.io.in.ready io.compactor.bits.head := sidx << mem_size io.compactor.bits.tail := Mux(sidx_tail, (io.op.nf +& 1.U) << mem_size, 0.U) } segbuf.io.in.valid := io.valid && io.op.seg_nf =/= 0.U && io.compactor.ready segbuf.io.in.bits.eew := mem_size segbuf.io.in.bits.nf := io.op.nf segbuf.io.in.bits.data := io.compactor_data segbuf.io.in.bits.eidx := eidx segbuf.io.in.bits.sidx := sidx segbuf.io.in.bits.sidx_tail := sidx_tail segbuf.io.in.bits.tail := eidx_tail segbuf.io.in.bits.segstart := io.op.segstart segbuf.io.in.bits.debug_id := io.op.debug_id segbuf.io.out.ready := io.resp.ready io.resp.valid := Mux(segbuf.io.busy, segbuf.io.out.valid, io.compactor.ready && io.valid && io.op.seg_nf === 0.U) io.resp.bits.data := Mux(segbuf.io.busy, segbuf.io.out.bits.data, io.compactor_data) io.resp.bits.debug_id := Mux(segbuf.io.busy, segbuf.io.out.bits.debug_id, io.op.debug_id) val seg_ready = Mux(io.op.seg_nf === 0.U, !segbuf.io.busy && io.compactor.ready && io.resp.ready, segbuf.io.in.ready && io.compactor.ready && sidx_tail) when (segbuf.io.in.fire) { r_head := false.B when (r_head) { r_eidx := io.op.vstart } r_sidx := next_sidx when (next_sidx > io.op.nf) { r_sidx := 0.U } } io.done := false.B when (seg_ready && io.valid) { r_head := eidx_tail r_eidx := next_eidx io.done := eidx_tail } } File Bundles.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val base_offset = UInt(pgIdxBits.W) val page = UInt((paddrBits - pgIdxBits).W) val stride = UInt(pgIdxBits.W) val segstart = UInt(3.W) val segend = UInt(3.W) val vstart = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val mop = UInt(2.W) val vm = Bool() val nf = UInt(3.W) val idx_size = UInt(2.W) val elem_size = UInt(2.W) val whole_reg = Bool() val store = Bool() val fast_sg = Bool() def indexed = !mop.isOneOf(mopUnit, mopStrided) def seg_nf = Mux(whole_reg, 0.U, nf) def wr_nf = Mux(whole_reg, nf, 0.U) } class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val pc = UInt(vaddrBitsExtended.W) val bits = UInt(32.W) val vconfig = new VConfig val vstart = UInt(log2Ceil(maxVLMax).W) val segstart = UInt(3.W) val segend = UInt(3.W) val rs1_data = UInt(xLen.W) val rs2_data = UInt(xLen.W) val page = UInt((paddrBits - pgIdxBits).W) val vat = UInt(vParams.vatSz.W) val rm = UInt(3.W) val emul = UInt(2.W) val fast_sg = Bool() val debug_id = UInt(debugIdSz.W) val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this def opcode = bits(6,0) def store = opcode(5) def mem_idx_size = bits(13,12) def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12)) def vm = bits(25) def orig_mop = bits(27,26) def umop = bits(24,20) def nf = bits(31,29) def wr = orig_mop === mopUnit && umop === lumopWhole def seg_nf = Mux(wr, 0.U, nf) def wr_nf = Mux(wr, nf, 0.U) def vmu = opcode.isOneOf(opcLoad, opcStore) def rs1 = bits(19,15) def rs2 = bits(24,20) def rd = bits(11,7) def may_write_v0 = rd === 0.U && opcode =/= opcStore def funct3 = bits(14,12) def imm5 = bits(19,15) def imm5_sext = Cat(Fill(59, imm5(4)), imm5) def funct6 = bits(31,26) def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) || (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0)) def writes_frf = !vmu && (funct3 === OPFVV) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) } class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) { val reduction = Bool() // accumulates into vd[0] val scalar_to_vd0 = Bool() // mv scalar to vd[0] val wide_vd = Bool() // vd reads/writes at 2xSEW val wide_vs2 = Bool() // vs2 reads at 2xSEW val writes_mask = Bool() // writes dest as a mask val reads_vs1_mask = Bool() // vs1 read as mask val reads_vs2_mask = Bool() // vs2 read as mask val rs1_is_rs2 = Bool() val nf_log2 = UInt(2.W) val renv1 = Bool() val renv2 = Bool() val renvd = Bool() val renvm = Bool() val wvd = Bool() } class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) { val seq = UInt(nSeqs.W) } class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(32 * vLen / writeBits).W) def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0) val data = UInt(writeBits.W) val mask = UInt(writeBits.W) } class ScalarWrite extends Bundle { val data = UInt(64.W) val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) } class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(egsTotal).W) val oldest = Bool() } class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val req = Decoupled(new VectorReadReq) val resp = Input(UInt(dLen.W)) } class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val vrs = Input(UInt(5.W)) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val eew = Input(UInt(2.W)) val idx = Output(UInt(64.W)) } class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val mask = Output(Bool()) } class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val data = UInt(8.W) val mask = Bool() } class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eidx = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val rvs1_data = UInt(dLen.W) val rvs2_data = UInt(dLen.W) val rvd_data = UInt(dLen.W) val rvm_data = UInt(dLen.W) val rvs1_elem = UInt(64.W) val rvs2_elem = UInt(64.W) val rvd_elem = UInt(64.W) val rvs1_eew = UInt(2.W) val rvs2_eew = UInt(2.W) val rvd_eew = UInt(2.W) val vd_eew = UInt(2.W) val rmask = UInt(dLenB.W) val wmask = UInt(dLenB.W) val full_tail_mask = UInt(dLen.W) val wvd_eg = UInt(log2Ceil(egsTotal).W) val funct3 = UInt(3.W) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) def vd_eew8 = vd_eew === 0.U def vd_eew16 = vd_eew === 1.U def vd_eew32 = vd_eew === 2.U def vd_eew64 = vd_eew === 3.U val funct6 = UInt(6.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rd = UInt(5.W) val vm = Bool() val head = Bool() val tail = Bool() val vat = UInt(vParams.vatSz.W) val acc = Bool() val rm = UInt(3.W) def vxrm = rm(1,0) def frm = rm } class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val stdata = UInt(dLen.W) val stmask = UInt(dLenB.W) val debug_id = UInt(debugIdSz.W) val tail = Bool() val vat = UInt(vParams.vatSz.W) def asMaskedBytes = { val bytes = Wire(Vec(dLenB, new MaskedByte)) for (i <- 0 until dLenB) { bytes(i).data := stdata(((i+1)*8)-1,i*8) bytes(i).mask := stmask(i) bytes(i).debug_id := debug_id } bytes } } class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val wvd_eg = UInt(log2Ceil(egsTotal).W) val wmask = UInt(dLenB.W) val tail = Bool() val debug_id = UInt(debugIdSz.W) val vat = UInt(vParams.vatSz.W) } class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val renv2 = Bool() val renvm = Bool() val rvs2_data = UInt(dLen.W) val eidx = UInt(log2Ceil(maxVLMax).W) val rvs2_eew = UInt(2.W) val rvm_data = UInt(dLen.W) val vmu = Bool() val vl = UInt((1+log2Ceil(maxVLMax)).W) val tail = Bool() } class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val latency = UInt(log2Ceil(pipe_depth).W) val eg = UInt(log2Ceil(egsTotal).W) def eg_oh = UIntToOH(eg) } class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(egsTotal.W) val wintent = UInt(egsTotal.W) } class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(32.W) val wintent = UInt(32.W) }
module LoadSegmenter( // @[LoadSegmenter.scala:11:7] input clock, // @[LoadSegmenter.scala:11:7] input reset, // @[LoadSegmenter.scala:11:7] input io_valid, // @[LoadSegmenter.scala:12:14] output io_done, // @[LoadSegmenter.scala:12:14] input [15:0] io_op_debug_id, // @[LoadSegmenter.scala:12:14] input [2:0] io_op_segstart, // @[LoadSegmenter.scala:12:14] input [7:0] io_op_vstart, // @[LoadSegmenter.scala:12:14] input [8:0] io_op_vl, // @[LoadSegmenter.scala:12:14] input [2:0] io_op_nf, // @[LoadSegmenter.scala:12:14] input [1:0] io_op_elem_size, // @[LoadSegmenter.scala:12:14] input io_op_whole_reg, // @[LoadSegmenter.scala:12:14] input io_compactor_ready, // @[LoadSegmenter.scala:12:14] output io_compactor_valid, // @[LoadSegmenter.scala:12:14] output [3:0] io_compactor_bits_head, // @[LoadSegmenter.scala:12:14] output [3:0] io_compactor_bits_tail, // @[LoadSegmenter.scala:12:14] input [127:0] io_compactor_data, // @[LoadSegmenter.scala:12:14] input io_resp_ready, // @[LoadSegmenter.scala:12:14] output io_resp_valid, // @[LoadSegmenter.scala:12:14] output [127:0] io_resp_bits_data, // @[LoadSegmenter.scala:12:14] output [15:0] io_resp_bits_debug_id // @[LoadSegmenter.scala:12:14] ); wire _segbuf_io_in_ready; // @[LoadSegmenter.scala:26:22] wire _segbuf_io_out_valid; // @[LoadSegmenter.scala:26:22] wire [127:0] _segbuf_io_out_bits_data; // @[LoadSegmenter.scala:26:22] wire [15:0] _segbuf_io_out_bits_debug_id; // @[LoadSegmenter.scala:26:22] wire _segbuf_io_busy; // @[LoadSegmenter.scala:26:22] reg [7:0] r_eidx; // @[LoadSegmenter.scala:28:19] reg r_head; // @[LoadSegmenter.scala:29:23] reg [2:0] r_sidx; // @[LoadSegmenter.scala:30:19] wire [7:0] eidx = r_head ? io_op_vstart : r_eidx; // @[LoadSegmenter.scala:28:19, :29:23, :31:17] wire [2:0] sidx = r_head ? io_op_segstart : r_sidx; // @[LoadSegmenter.scala:29:23, :30:19, :32:17] wire [2:0] _seg_ready_T = io_op_whole_reg ? 3'h0 : io_op_nf; // @[Bundles.scala:33:19] wire [10:0] _GEN = {9'h0, io_op_elem_size}; // @[LoadSegmenter.scala:35:64] wire [10:0] _incr_T_3 = {3'h0, (|_seg_ready_T) ? {5'h0, sidx} : eidx} << _GEN; // @[LoadSegmenter.scala:31:17, :32:17, :35:{29,43,64}] wire [4:0] incr = 5'h10 - {1'h0, _incr_T_3[3:0]} >> io_op_elem_size; // @[LoadSegmenter.scala:11:7, :35:{23,64,76,95}] wire [8:0] next_eidx = {1'h0, eidx} + {4'h0, (|_seg_ready_T) ? 5'h1 : incr}; // @[LoadSegmenter.scala:11:7, :31:17, :35:95, :36:{22,36}, :38:24] wire [5:0] _GEN_0 = {3'h0, sidx}; // @[LoadSegmenter.scala:32:17, :39:24] wire [5:0] next_sidx = _GEN_0 + {1'h0, incr}; // @[LoadSegmenter.scala:11:7, :35:95, :39:24] wire sidx_tail = next_sidx > {3'h0, _seg_ready_T}; // @[LoadSegmenter.scala:39:24, :41:29] wire eidx_tail = next_eidx >= io_op_vl; // @[LoadSegmenter.scala:38:24, :42:29] wire [10:0] _io_compactor_bits_head_T = {3'h0, eidx} << _GEN; // @[LoadSegmenter.scala:31:17, :35:64, :46:36] wire [11:0] _io_compactor_bits_tail_T = {3'h0, io_op_vl} << io_op_elem_size; // @[LoadSegmenter.scala:47:55] wire [5:0] _io_compactor_bits_head_T_1 = _GEN_0 << io_op_elem_size; // @[LoadSegmenter.scala:39:24, :50:36] wire [6:0] _io_compactor_bits_tail_T_3 = {3'h0, {1'h0, io_op_nf} + 4'h1} << io_op_elem_size; // @[LoadSegmenter.scala:11:7, :51:{56,64}] wire segbuf_io_in_valid = io_valid & (|_seg_ready_T) & io_compactor_ready; // @[LoadSegmenter.scala:54:{34,50,58}] wire _GEN_1 = ((|_seg_ready_T) ? _segbuf_io_in_ready & io_compactor_ready & sidx_tail : ~_segbuf_io_busy & io_compactor_ready & io_resp_ready) & io_valid; // @[LoadSegmenter.scala:26:22, :35:43, :41:29, :74:22, :75:{5,21,43}, :76:{24,46}, :88:19] wire _GEN_2 = _segbuf_io_in_ready & segbuf_io_in_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoadSegmenter.scala:11:7] if (_GEN_1) // @[LoadSegmenter.scala:88:19] r_eidx <= next_eidx[7:0]; // @[LoadSegmenter.scala:28:19, :38:24, :90:12] else if (_GEN_2 & r_head) // @[Decoupled.scala:51:35] r_eidx <= io_op_vstart; // @[LoadSegmenter.scala:28:19] if (_GEN_2) // @[Decoupled.scala:51:35] r_sidx <= next_sidx > {3'h0, io_op_nf} ? 3'h0 : next_sidx[2:0]; // @[LoadSegmenter.scala:30:19, :39:24, :82:12, :83:{21,33}, :84:14] if (reset) // @[LoadSegmenter.scala:11:7] r_head <= 1'h1; // @[LoadSegmenter.scala:11:7, :29:23] else // @[LoadSegmenter.scala:11:7] r_head <= _GEN_1 ? eidx_tail : ~_GEN_2 & r_head; // @[Decoupled.scala:51:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e8_s24_15( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_15 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SourceA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceARequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val param = UInt(3.W) val source = UInt(params.outer.bundle.sourceBits.W) val block = Bool() } class SourceA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceARequest(params))) val a = Decoupled(new TLBundleA(params.outer.bundle)) }) // ready must be a register, because we derive valid from ready require (!params.micro.outerBuf.a.pipe && params.micro.outerBuf.a.isDefined) val a = Wire(chiselTypeOf(io.a)) io.a <> params.micro.outerBuf.a(a) io.req.ready := a.ready a.valid := io.req.valid params.ccover(a.valid && !a.ready, "SOURCEA_STALL", "Backpressured when issuing an Acquire") a.bits.opcode := Mux(io.req.bits.block, TLMessages.AcquireBlock, TLMessages.AcquirePerm) a.bits.param := io.req.bits.param a.bits.size := params.offsetBits.U a.bits.source := io.req.bits.source a.bits.address := params.expandAddress(io.req.bits.tag, io.req.bits.set, 0.U) a.bits.mask := ~0.U(params.outer.manager.beatBytes.W) a.bits.data := 0.U a.bits.corrupt := false.B }
module SourceA( // @[SourceA.scala:33:7] input clock, // @[SourceA.scala:33:7] input reset, // @[SourceA.scala:33:7] output io_req_ready, // @[SourceA.scala:35:14] input io_req_valid, // @[SourceA.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceA.scala:35:14] input [9:0] io_req_bits_set, // @[SourceA.scala:35:14] input [2:0] io_req_bits_param, // @[SourceA.scala:35:14] input [3:0] io_req_bits_source, // @[SourceA.scala:35:14] input io_req_bits_block, // @[SourceA.scala:35:14] input io_a_ready, // @[SourceA.scala:35:14] output io_a_valid, // @[SourceA.scala:35:14] output [2:0] io_a_bits_opcode, // @[SourceA.scala:35:14] output [2:0] io_a_bits_param, // @[SourceA.scala:35:14] output [2:0] io_a_bits_size, // @[SourceA.scala:35:14] output [3:0] io_a_bits_source, // @[SourceA.scala:35:14] output [31:0] io_a_bits_address, // @[SourceA.scala:35:14] output [7:0] io_a_bits_mask, // @[SourceA.scala:35:14] output [63:0] io_a_bits_data, // @[SourceA.scala:35:14] output io_a_bits_corrupt // @[SourceA.scala:35:14] ); Queue2_TLBundleA_a32d64s4k3z3c io_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (io_req_ready), .io_enq_valid (io_req_valid), .io_enq_bits_opcode ({2'h3, ~io_req_bits_block}), // @[SourceA.scala:50:24] .io_enq_bits_param (io_req_bits_param), .io_enq_bits_source (io_req_bits_source), .io_enq_bits_address ({io_req_bits_tag[12], 3'h0, io_req_bits_tag[11:0], io_req_bits_set, 6'h0}), // @[Parameters.scala:229:72, :230:8] .io_deq_ready (io_a_ready), .io_deq_valid (io_a_valid), .io_deq_bits_opcode (io_a_bits_opcode), .io_deq_bits_param (io_a_bits_param), .io_deq_bits_size (io_a_bits_size), .io_deq_bits_source (io_a_bits_source), .io_deq_bits_address (io_a_bits_address), .io_deq_bits_mask (io_a_bits_mask), .io_deq_bits_data (io_a_bits_data), .io_deq_bits_corrupt (io_a_bits_corrupt) ); // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncQueueSink_TLBundleD_a9d32s1k1z2u( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [2:0] io_deq_bits_opcode, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_param, // @[AsyncQueue.scala:139:14] output [1:0] io_deq_bits_size, // @[AsyncQueue.scala:139:14] output io_deq_bits_source, // @[AsyncQueue.scala:139:14] output io_deq_bits_sink, // @[AsyncQueue.scala:139:14] output io_deq_bits_denied, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_data, // @[AsyncQueue.scala:139:14] output io_deq_bits_corrupt, // @[AsyncQueue.scala:139:14] input [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:139:14] input [1:0] io_async_mem_0_size, // @[AsyncQueue.scala:139:14] input io_async_mem_0_source, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_data, // @[AsyncQueue.scala:139:14] output io_async_ridx, // @[AsyncQueue.scala:139:14] input io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire io_deq_valid_0; // @[AsyncQueue.scala:166:29] wire _source_valid_io_out; // @[AsyncQueue.scala:176:31] wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire [42:0] _io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala:207:25] wire _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire ridx = _source_valid_io_out & ridx_ridx_bin + (io_deq_ready & io_deq_valid_0); // @[Decoupled.scala:51:35] wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q; // @[ShiftReg.scala:45:23] reg valid_reg; // @[AsyncQueue.scala:165:56] assign io_deq_valid_0 = valid_reg & _source_valid_io_out; // @[AsyncQueue.scala:165:56, :166:29, :176:31] reg ridx_gray; // @[AsyncQueue.scala:168:55] always @(posedge clock or posedge reset) begin // @[AsyncQueue.scala:136:7] if (reset) begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= 1'h0; // @[AsyncQueue.scala:52:25, :136:7] valid_reg <= 1'h0; // @[AsyncQueue.scala:136:7, :165:56] ridx_gray <= 1'h0; // @[AsyncQueue.scala:136:7, :168:55] end else begin // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx; // @[AsyncQueue.scala:52:25, :53:23] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] ridx_gray <= ridx; // @[AsyncQueue.scala:53:23, :168:55] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_62( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_318 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } }
module NoCMonitor_124( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 4'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 4'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 4'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 4'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 4'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 4'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 4'h8; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }
module IssueSlot_30( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_147( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_84( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_139( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_239 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [4097:0] _c_sizes_set_T_1 = 4098'h0; // @[Monitor.scala:768:52] wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77] wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35] wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35] wire [1279:0] c_opcodes_set = 1280'h0; // @[Monitor.scala:740:34] wire [1279:0] c_sizes_set = 1280'h0; // @[Monitor.scala:741:34] wire [319:0] c_set = 320'h0; // @[Monitor.scala:738:34] wire [319:0] c_set_wo_ready = 320'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [8:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [8:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [8:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 9'h140; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [319:0] inflight; // @[Monitor.scala:614:27] reg [1279:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1279:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [319:0] a_set; // @[Monitor.scala:626:34] wire [319:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1279:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1279:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [1279:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1279:0] _a_opcode_lookup_T_6 = {1276'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1279:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1279:0] _a_size_lookup_T_6 = {1276'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1279:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4097:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[1279:0] : 1280'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [319:0] d_clr; // @[Monitor.scala:664:34] wire [319:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1279:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1279:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[1279:0] : 1280'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [319:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [319:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [319:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1279:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1279:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1279:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [319:0] inflight_1; // @[Monitor.scala:726:35] wire [319:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [1279:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [1279:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1279:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1279:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1279:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1279:0] _c_opcode_lookup_T_6 = {1276'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1279:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1279:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1279:0] _c_size_lookup_T_6 = {1276'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1279:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1279:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [319:0] d_clr_1; // @[Monitor.scala:774:34] wire [319:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1279:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1279:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[319:0] : 320'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[1279:0] : 1280'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113] wire [319:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [319:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1279:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1279:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1279:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }
module TLNoC_router_5ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_5 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_UInt_7( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [2:0] io_x, // @[package.scala:268:18] output [2:0] io_y // @[package.scala:268:18] ); wire [2:0] io_x_0 = io_x; // @[package.scala:267:30] wire [2:0] io_y_0 = io_x_0; // @[package.scala:267:30] assign io_y = io_y_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_263( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_60( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `β†’`: target of arrow is generated by source * * {{{ * (from the other node) * β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€[[InwardNode.uiParams]]─────────────┐ * ↓ β”‚ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ β”‚ * [[InwardNode.accPI]] β”‚ β”‚ β”‚ * β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ ↓ β”‚ * ↓ β”‚ β”‚ β”‚ * (immobilize after elaboration) (inward port from [[OutwardNode]]) β”‚ ↓ β”‚ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] β”‚ * β”‚ β”‚ ↑ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[OutwardNode.doParams]] β”‚ β”‚ * β”‚ β”‚ β”‚ (from the other node) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ └────────┬─────────────── β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ (based on protocol) β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.inner.edgeI]] β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ (from the other node) β”‚ ↓ β”‚ * β”‚ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] β”‚ [[MixedNode.edgesIn]]───┐ β”‚ * β”‚ ↑ ↑ β”‚ β”‚ ↓ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ [[MixedNode.in]] β”‚ * β”‚ β”‚ β”‚ β”‚ ↓ ↑ β”‚ * β”‚ (solve star connection) β”‚ β”‚ β”‚ [[MixedNode.bundleIn]]β”€β”€β”˜ β”‚ * β”œβ”€β”€β”€[[MixedNode.resolveStar]]→─┼────────────────────────────── └────────────────────────────────────┐ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.bundleOut]]─┐ β”‚ β”‚ * β”‚ β”‚ β”‚ ↑ ↓ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ [[MixedNode.out]] β”‚ β”‚ * β”‚ ↓ ↓ β”‚ ↑ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]β”€β”€β”˜ β”‚ β”‚ * β”‚ β”‚ (from the other node) ↑ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ [[MixedNode.outer.edgeO]] β”‚ β”‚ * β”‚ β”‚ β”‚ (based on protocol) β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * (immobilize after elaboration)β”‚ ↓ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.oBindings]]β”€β”˜ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] β”‚ β”‚ * ↑ (inward port from [[OutwardNode]]) β”‚ β”‚ β”‚ β”‚ * β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * β”‚ β”‚ β”‚ β”‚ β”‚ β”‚ * [[OutwardNode.accPO]] β”‚ ↓ β”‚ β”‚ β”‚ * (binding node when elaboration) β”‚ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ * β”‚ ↑ β”‚ β”‚ * β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ * β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a21d64s7k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [20:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [20:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [20:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_28 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a21d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a21d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_11( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_108( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 4'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 4'h1; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }
module Repeater_TLBundleA_a28d64s5k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [27:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [27:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [27:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_67( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object consts { /*------------------------------------------------------------------------ | For rounding to integer values, rounding mode 'odd' rounds to minimum | magnitude instead, same as 'minMag'. *------------------------------------------------------------------------*/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }
module MulAddRecFNToRaw_preMul_e8_s24_2( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_33( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_33 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module MulAddRecFNToRaw_preMul_e8_s24_67( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLBToNoC_4( // @[TilelinkAdapters.scala:133:7] input clock, // @[TilelinkAdapters.scala:133:7] input reset, // @[TilelinkAdapters.scala:133:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body | (&_q_io_deq_bits_mask)); // @[TilelinkAdapters.scala:26:17, :39:24, :41:{35,47}, :139:70] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = is_body | (&_q_io_deq_bits_mask); // @[TilelinkAdapters.scala:26:17, :39:24, :44:47, :139:70] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:133:7] if (reset) begin // @[TilelinkAdapters.scala:133:7] head_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :133:7] end else begin // @[TilelinkAdapters.scala:133:7] if (q_io_deq_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35] head_counter <= head ? 3'h0 : head_counter - 3'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21] is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_7( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_105( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }
module EgressUnit_59( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30]
Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }
module OutputUnit_13( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [36:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [36:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [3:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [3:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_3_occupied; // @[OutputUnit.scala:66:19] reg states_3_c; // @[OutputUnit.scala:66:19] reg states_2_occupied; // @[OutputUnit.scala:66:19] reg states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg states_1_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_68( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_50( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_175( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_190 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_195( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_451 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File VectorUnit.scala: package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ case class RocketCoreVectorParams( build: Parameters => RocketVectorUnit, vLen: Int, eLen: Int, vfLen: Int, vfh: Boolean, vMemDataBits: Int, decoder: Parameters => RocketVectorDecoder, useDCache: Boolean, issueVConfig: Boolean, vExts: Seq[String] ) class VectorCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val status = Input(new MStatus) val ex = new Bundle { val valid = Input(Bool()) val ready = Output(Bool()) val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val vconfig = Input(new VConfig) val vstart = Input(UInt(log2Ceil(maxVLMax).W)) val rs1 = Input(UInt(xLen.W)) val rs2 = Input(UInt(xLen.W)) } val killm = Input(Bool()) val mem = new Bundle { val frs1 = Input(UInt(fLen.W)) val block_mem = Output(Bool()) val block_all = Output(Bool()) } val wb = new Bundle { val store_pending = Input(Bool()) val replay = Output(Bool()) val retire = Output(Bool()) val inst = Output(UInt(32.W)) val rob_should_wb = Output(Bool()) // debug val rob_should_wb_fp = Output(Bool()) // debug val pc = Output(UInt(vaddrBitsExtended.W)) val xcpt = Output(Bool()) val cause = Output(UInt(log2Ceil(Causes.all.max).W)) val tval = Output(UInt(coreMaxAddrBits.W)) val vxrm = Input(UInt(2.W)) val frm = Input(UInt(3.W)) } val resp = Decoupled(new Bundle { val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) val data = UInt((xLen max fLen).W) }) val set_vstart = Valid(UInt(log2Ceil(maxVLMax).W)) val set_vxsat = Output(Bool()) val set_vconfig = Valid(new VConfig) val set_fflags = Valid(UInt(5.W)) val trap_check_busy = Output(Bool()) val backend_busy = Output(Bool()) } abstract class RocketVectorUnit(implicit p: Parameters) extends LazyModule { val module: RocketVectorUnitModuleImp val tlNode: TLNode = TLIdentityNode() val atlNode: TLNode = TLIdentityNode() } class RocketVectorUnitModuleImp(outer: RocketVectorUnit) extends LazyModuleImp(outer) { val io = IO(new Bundle { val core = new VectorCoreIO val tlb = Flipped(new DCacheTLBPort) val dmem = new HellaCacheIO val fp_req = Decoupled(new FPInput()) val fp_resp = Flipped(Decoupled(new FPResult())) }) } abstract class RocketVectorDecoder(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val vconfig = Input(new VConfig) val legal = Output(Bool()) val fp = Output(Bool()) val read_rs1 = Output(Bool()) val read_rs2 = Output(Bool()) val read_frs1 = Output(Bool()) val write_rd = Output(Bool()) val write_frd = Output(Bool()) }) } File Integration.scala: package saturn.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ import saturn.common._ import saturn.backend.{VectorBackend} import saturn.mem.{TLSplitInterface, VectorMemUnit} import saturn.frontend.{VectorDispatcher} class SaturnRocketUnit(implicit p: Parameters) extends RocketVectorUnit()(p) with HasVectorParams with HasCoreParameters { if (vParams.useScalarFPFMA || vParams.useScalarFPMisc) { require(coreParams.fpu.isDefined) if (vParams.useScalarFPFMA) { require(coreParams.fpu.get.sfmaLatency == vParams.fmaPipeDepth - 1) require(coreParams.fpu.get.dfmaLatency == vParams.fmaPipeDepth - 1) } } val tl_if = LazyModule(new TLSplitInterface) atlNode := TLBuffer(vParams.tlBuffer) := TLWidthWidget(dLen/8) := tl_if.node override lazy val module = new SaturnRocketImpl class SaturnRocketImpl extends RocketVectorUnitModuleImp(this) with HasVectorParams with HasCoreParameters { val useL1DCache = dLen == vMemDataBits val dis = Module(new VectorDispatcher) val vfu = Module(new SaturnRocketFrontend(tl_if.edge)) val vu = Module(new VectorBackend) val vmu = Module(new VectorMemUnit) val hella_if = Module(new HellaCacheInterface) val scalar_arb = Module(new Arbiter(new ScalarWrite, 2)) dis.io.issue <> vfu.io.issue vfu.io.core <> io.core vfu.io.tlb <> io.tlb vu.io.index_access <> vfu.io.index_access vu.io.mask_access <> vfu.io.mask_access vu.io.vmu <> vmu.io.vu vu.io.vat_tail := dis.io.vat_tail vu.io.vat_head := dis.io.vat_head vu.io.dis <> dis.io.dis dis.io.vat_release := vu.io.vat_release vmu.io.enq <> dis.io.mem vmu.io.scalar_check <> vfu.io.scalar_check io.core.backend_busy := vu.io.busy || tl_if.module.io.mem_busy || hella_if.io.mem_busy || vmu.io.busy io.core.set_vxsat := vu.io.set_vxsat io.core.set_fflags := vu.io.set_fflags scalar_arb.io.in(0) <> vu.io.scalar_resp scalar_arb.io.in(1) <> dis.io.scalar_resp io.core.resp <> Queue(scalar_arb.io.out) io.fp_req <> vu.io.fp_req vu.io.fp_resp.valid := io.fp_resp.valid vu.io.fp_resp.bits := io.fp_resp.bits io.fp_resp.ready := true.B io.dmem <> hella_if.io.dmem hella_if.io.vec_busy := vu.io.busy || vmu.io.busy hella_if.io.status := io.core.status def block[T <: Data](in: DecoupledIO[T], block: Bool): DecoupledIO[T] = { val out = Wire(Decoupled(in.bits.cloneType)) out.bits := in.bits out.valid := in.valid && !block in.ready := out.ready && !block out } val load_use_tl_reg = RegInit(true.B) val store_use_tl_reg = RegInit(true.B) // virtually-addressed requests must go through L1 val load_use_tl = load_use_tl_reg || !useL1DCache.B val store_use_tl = store_use_tl_reg || !useL1DCache.B vmu.io.dmem.load_resp.valid := tl_if.module.io.vec.load_resp.valid || hella_if.io.vec.load_resp.valid vmu.io.dmem.load_resp.bits := Mux1H( Seq(tl_if.module.io.vec.load_resp.valid, hella_if.io.vec.load_resp.valid), Seq(tl_if.module.io.vec.load_resp.bits , hella_if.io.vec.load_resp.bits)) vmu.io.dmem.store_ack.valid := tl_if.module.io.vec.store_ack.valid || hella_if.io.vec.store_ack.valid vmu.io.dmem.store_ack.bits := Mux1H( Seq(tl_if.module.io.vec.store_ack.valid, hella_if.io.vec.store_ack.valid), Seq(tl_if.module.io.vec.store_ack.bits , hella_if.io.vec.store_ack.bits)) when (load_use_tl) { tl_if.module.io.vec.load_req <> block(vmu.io.dmem.load_req, hella_if.io.mem_busy) hella_if.io.vec.load_req.valid := false.B hella_if.io.vec.load_req.bits := DontCare } .otherwise { hella_if.io.vec.load_req <> block(vmu.io.dmem.load_req, tl_if.module.io.mem_busy) tl_if.module.io.vec.load_req.valid := false.B tl_if.module.io.vec.load_req.bits := DontCare } when (store_use_tl) { tl_if.module.io.vec.store_req <> block(vmu.io.dmem.store_req, hella_if.io.mem_busy) hella_if.io.vec.store_req.valid := false.B hella_if.io.vec.store_req.bits := DontCare } .otherwise { hella_if.io.vec.store_req <> block(vmu.io.dmem.store_req, tl_if.module.io.mem_busy) tl_if.module.io.vec.store_req.valid := false.B tl_if.module.io.vec.store_req.bits := DontCare } } }
module SaturnRocketUnit( // @[Integration.scala:31:9] input clock, // @[Integration.scala:31:9] input reset, // @[Integration.scala:31:9] input auto_atl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_atl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_atl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_atl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_atl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_atl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_atl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_atl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_atl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_atl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_atl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_atl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_atl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_atl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_atl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_atl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_atl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_core_status_dv, // @[VectorUnit.scala:80:14] input [1:0] io_core_status_prv, // @[VectorUnit.scala:80:14] input io_core_ex_valid, // @[VectorUnit.scala:80:14] output io_core_ex_ready, // @[VectorUnit.scala:80:14] input [31:0] io_core_ex_inst, // @[VectorUnit.scala:80:14] input [39:0] io_core_ex_pc, // @[VectorUnit.scala:80:14] input [6:0] io_core_ex_vconfig_vl, // @[VectorUnit.scala:80:14] input io_core_ex_vconfig_vtype_vill, // @[VectorUnit.scala:80:14] input [54:0] io_core_ex_vconfig_vtype_reserved, // @[VectorUnit.scala:80:14] input io_core_ex_vconfig_vtype_vma, // @[VectorUnit.scala:80:14] input io_core_ex_vconfig_vtype_vta, // @[VectorUnit.scala:80:14] input [2:0] io_core_ex_vconfig_vtype_vsew, // @[VectorUnit.scala:80:14] input io_core_ex_vconfig_vtype_vlmul_sign, // @[VectorUnit.scala:80:14] input [1:0] io_core_ex_vconfig_vtype_vlmul_mag, // @[VectorUnit.scala:80:14] input [5:0] io_core_ex_vstart, // @[VectorUnit.scala:80:14] input [63:0] io_core_ex_rs1, // @[VectorUnit.scala:80:14] input [63:0] io_core_ex_rs2, // @[VectorUnit.scala:80:14] input io_core_killm, // @[VectorUnit.scala:80:14] input [63:0] io_core_mem_frs1, // @[VectorUnit.scala:80:14] output io_core_mem_block_mem, // @[VectorUnit.scala:80:14] output io_core_mem_block_all, // @[VectorUnit.scala:80:14] input io_core_wb_store_pending, // @[VectorUnit.scala:80:14] output io_core_wb_replay, // @[VectorUnit.scala:80:14] output io_core_wb_retire, // @[VectorUnit.scala:80:14] output [31:0] io_core_wb_inst, // @[VectorUnit.scala:80:14] output [39:0] io_core_wb_pc, // @[VectorUnit.scala:80:14] output io_core_wb_xcpt, // @[VectorUnit.scala:80:14] output [4:0] io_core_wb_cause, // @[VectorUnit.scala:80:14] output [39:0] io_core_wb_tval, // @[VectorUnit.scala:80:14] input [1:0] io_core_wb_vxrm, // @[VectorUnit.scala:80:14] input [2:0] io_core_wb_frm, // @[VectorUnit.scala:80:14] input io_core_resp_ready, // @[VectorUnit.scala:80:14] output io_core_resp_valid, // @[VectorUnit.scala:80:14] output io_core_resp_bits_fp, // @[VectorUnit.scala:80:14] output [1:0] io_core_resp_bits_size, // @[VectorUnit.scala:80:14] output [4:0] io_core_resp_bits_rd, // @[VectorUnit.scala:80:14] output [63:0] io_core_resp_bits_data, // @[VectorUnit.scala:80:14] output io_core_set_vstart_valid, // @[VectorUnit.scala:80:14] output [5:0] io_core_set_vstart_bits, // @[VectorUnit.scala:80:14] output io_core_set_vxsat, // @[VectorUnit.scala:80:14] output io_core_set_vconfig_valid, // @[VectorUnit.scala:80:14] output [6:0] io_core_set_vconfig_bits_vl, // @[VectorUnit.scala:80:14] output io_core_set_vconfig_bits_vtype_vill, // @[VectorUnit.scala:80:14] output [54:0] io_core_set_vconfig_bits_vtype_reserved, // @[VectorUnit.scala:80:14] output io_core_set_vconfig_bits_vtype_vma, // @[VectorUnit.scala:80:14] output io_core_set_vconfig_bits_vtype_vta, // @[VectorUnit.scala:80:14] output [2:0] io_core_set_vconfig_bits_vtype_vsew, // @[VectorUnit.scala:80:14] output io_core_set_vconfig_bits_vtype_vlmul_sign, // @[VectorUnit.scala:80:14] output [1:0] io_core_set_vconfig_bits_vtype_vlmul_mag, // @[VectorUnit.scala:80:14] output io_core_trap_check_busy, // @[VectorUnit.scala:80:14] output io_core_backend_busy, // @[VectorUnit.scala:80:14] output io_tlb_req_valid, // @[VectorUnit.scala:80:14] output [39:0] io_tlb_req_bits_vaddr, // @[VectorUnit.scala:80:14] output [1:0] io_tlb_req_bits_size, // @[VectorUnit.scala:80:14] output [4:0] io_tlb_req_bits_cmd, // @[VectorUnit.scala:80:14] output [1:0] io_tlb_req_bits_prv, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_miss, // @[VectorUnit.scala:80:14] input [31:0] io_tlb_s1_resp_paddr, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_pf_ld, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_pf_st, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_ae_ld, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_ae_st, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_ma_ld, // @[VectorUnit.scala:80:14] input io_tlb_s1_resp_ma_st, // @[VectorUnit.scala:80:14] input [4:0] io_tlb_s1_resp_cmd, // @[VectorUnit.scala:80:14] input io_dmem_req_ready, // @[VectorUnit.scala:80:14] output io_dmem_req_valid, // @[VectorUnit.scala:80:14] output [39:0] io_dmem_req_bits_addr, // @[VectorUnit.scala:80:14] output [7:0] io_dmem_req_bits_tag, // @[VectorUnit.scala:80:14] output [4:0] io_dmem_req_bits_cmd, // @[VectorUnit.scala:80:14] output [1:0] io_dmem_req_bits_size, // @[VectorUnit.scala:80:14] output io_dmem_req_bits_signed, // @[VectorUnit.scala:80:14] output [1:0] io_dmem_req_bits_dprv, // @[VectorUnit.scala:80:14] output io_dmem_req_bits_dv, // @[VectorUnit.scala:80:14] output io_dmem_req_bits_phys, // @[VectorUnit.scala:80:14] output io_dmem_req_bits_no_alloc, // @[VectorUnit.scala:80:14] output io_dmem_req_bits_no_xcpt, // @[VectorUnit.scala:80:14] output [7:0] io_dmem_req_bits_mask, // @[VectorUnit.scala:80:14] output [63:0] io_dmem_s1_data_data, // @[VectorUnit.scala:80:14] output [7:0] io_dmem_s1_data_mask, // @[VectorUnit.scala:80:14] input io_dmem_s2_nack, // @[VectorUnit.scala:80:14] input io_dmem_resp_valid, // @[VectorUnit.scala:80:14] input [7:0] io_dmem_resp_bits_tag, // @[VectorUnit.scala:80:14] input [63:0] io_dmem_resp_bits_data_raw, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_ma_ld, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_ma_st, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_pf_ld, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_pf_st, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_ae_ld, // @[VectorUnit.scala:80:14] input io_dmem_s2_xcpt_ae_st, // @[VectorUnit.scala:80:14] input io_fp_req_ready, // @[VectorUnit.scala:80:14] output io_fp_req_valid, // @[VectorUnit.scala:80:14] output io_fp_req_bits_ren2, // @[VectorUnit.scala:80:14] output io_fp_req_bits_ren3, // @[VectorUnit.scala:80:14] output io_fp_req_bits_swap23, // @[VectorUnit.scala:80:14] output [1:0] io_fp_req_bits_typeTagIn, // @[VectorUnit.scala:80:14] output [1:0] io_fp_req_bits_typeTagOut, // @[VectorUnit.scala:80:14] output io_fp_req_bits_fromint, // @[VectorUnit.scala:80:14] output io_fp_req_bits_toint, // @[VectorUnit.scala:80:14] output io_fp_req_bits_fastpipe, // @[VectorUnit.scala:80:14] output io_fp_req_bits_fma, // @[VectorUnit.scala:80:14] output io_fp_req_bits_div, // @[VectorUnit.scala:80:14] output io_fp_req_bits_sqrt, // @[VectorUnit.scala:80:14] output io_fp_req_bits_wflags, // @[VectorUnit.scala:80:14] output [2:0] io_fp_req_bits_rm, // @[VectorUnit.scala:80:14] output [1:0] io_fp_req_bits_fmaCmd, // @[VectorUnit.scala:80:14] output [1:0] io_fp_req_bits_typ, // @[VectorUnit.scala:80:14] output [64:0] io_fp_req_bits_in1, // @[VectorUnit.scala:80:14] output [64:0] io_fp_req_bits_in2, // @[VectorUnit.scala:80:14] output [64:0] io_fp_req_bits_in3, // @[VectorUnit.scala:80:14] input io_fp_resp_valid, // @[VectorUnit.scala:80:14] input [64:0] io_fp_resp_bits_data // @[VectorUnit.scala:80:14] ); wire _io_core_resp_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _scalar_arb_io_in_0_ready; // @[Integration.scala:41:28] wire _scalar_arb_io_in_1_ready; // @[Integration.scala:41:28] wire _scalar_arb_io_out_valid; // @[Integration.scala:41:28] wire [63:0] _scalar_arb_io_out_bits_data; // @[Integration.scala:41:28] wire _scalar_arb_io_out_bits_fp; // @[Integration.scala:41:28] wire [1:0] _scalar_arb_io_out_bits_size; // @[Integration.scala:41:28] wire [4:0] _scalar_arb_io_out_bits_rd; // @[Integration.scala:41:28] wire _hella_if_io_vec_load_resp_valid; // @[Integration.scala:40:26] wire [63:0] _hella_if_io_vec_load_resp_bits_data; // @[Integration.scala:40:26] wire [3:0] _hella_if_io_vec_load_resp_bits_tag; // @[Integration.scala:40:26] wire _hella_if_io_vec_store_ack_valid; // @[Integration.scala:40:26] wire [3:0] _hella_if_io_vec_store_ack_bits_tag; // @[Integration.scala:40:26] wire _hella_if_io_mem_busy; // @[Integration.scala:40:26] wire _vmu_io_enq_ready; // @[Integration.scala:38:21] wire _vmu_io_dmem_load_req_valid; // @[Integration.scala:38:21] wire [39:0] _vmu_io_dmem_load_req_bits_addr; // @[Integration.scala:38:21] wire [3:0] _vmu_io_dmem_load_req_bits_tag; // @[Integration.scala:38:21] wire _vmu_io_dmem_store_req_valid; // @[Integration.scala:38:21] wire [39:0] _vmu_io_dmem_store_req_bits_addr; // @[Integration.scala:38:21] wire [63:0] _vmu_io_dmem_store_req_bits_data; // @[Integration.scala:38:21] wire [7:0] _vmu_io_dmem_store_req_bits_mask; // @[Integration.scala:38:21] wire [3:0] _vmu_io_dmem_store_req_bits_tag; // @[Integration.scala:38:21] wire _vmu_io_scalar_check_conflict; // @[Integration.scala:38:21] wire _vmu_io_vu_lresp_valid; // @[Integration.scala:38:21] wire [63:0] _vmu_io_vu_lresp_bits_data; // @[Integration.scala:38:21] wire [15:0] _vmu_io_vu_lresp_bits_debug_id; // @[Integration.scala:38:21] wire _vmu_io_vu_sdata_ready; // @[Integration.scala:38:21] wire _vmu_io_vu_mask_pop_valid; // @[Integration.scala:38:21] wire _vmu_io_vu_index_pop_valid; // @[Integration.scala:38:21] wire [2:0] _vmu_io_vu_index_pop_bits_tail; // @[Integration.scala:38:21] wire _vmu_io_busy; // @[Integration.scala:38:21] wire _vu_io_dis_ready; // @[Integration.scala:37:20] wire _vu_io_vmu_lresp_ready; // @[Integration.scala:37:20] wire _vu_io_vmu_sdata_valid; // @[Integration.scala:37:20] wire [63:0] _vu_io_vmu_sdata_bits_stdata; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_sdata_bits_stmask; // @[Integration.scala:37:20] wire [15:0] _vu_io_vmu_sdata_bits_debug_id; // @[Integration.scala:37:20] wire _vu_io_vmu_mask_pop_ready; // @[Integration.scala:37:20] wire _vu_io_vmu_mask_data_0; // @[Integration.scala:37:20] wire _vu_io_vmu_index_pop_ready; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_0; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_1; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_2; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_3; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_4; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_5; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_6; // @[Integration.scala:37:20] wire [7:0] _vu_io_vmu_index_data_7; // @[Integration.scala:37:20] wire _vu_io_busy; // @[Integration.scala:37:20] wire _vu_io_index_access_ready; // @[Integration.scala:37:20] wire [63:0] _vu_io_index_access_idx; // @[Integration.scala:37:20] wire _vu_io_mask_access_ready; // @[Integration.scala:37:20] wire _vu_io_mask_access_mask; // @[Integration.scala:37:20] wire _vu_io_scalar_resp_valid; // @[Integration.scala:37:20] wire [63:0] _vu_io_scalar_resp_bits_data; // @[Integration.scala:37:20] wire _vu_io_scalar_resp_bits_fp; // @[Integration.scala:37:20] wire [1:0] _vu_io_scalar_resp_bits_size; // @[Integration.scala:37:20] wire [4:0] _vu_io_scalar_resp_bits_rd; // @[Integration.scala:37:20] wire _vu_io_vat_release_0_valid; // @[Integration.scala:37:20] wire [2:0] _vu_io_vat_release_0_bits; // @[Integration.scala:37:20] wire _vu_io_vat_release_1_valid; // @[Integration.scala:37:20] wire [2:0] _vu_io_vat_release_1_bits; // @[Integration.scala:37:20] wire _vu_io_vat_release_2_valid; // @[Integration.scala:37:20] wire [2:0] _vu_io_vat_release_2_bits; // @[Integration.scala:37:20] wire _vfu_io_issue_valid; // @[Integration.scala:36:21] wire [31:0] _vfu_io_issue_bits_bits; // @[Integration.scala:36:21] wire [6:0] _vfu_io_issue_bits_vconfig_vl; // @[Integration.scala:36:21] wire [2:0] _vfu_io_issue_bits_vconfig_vtype_vsew; // @[Integration.scala:36:21] wire _vfu_io_issue_bits_vconfig_vtype_vlmul_sign; // @[Integration.scala:36:21] wire [1:0] _vfu_io_issue_bits_vconfig_vtype_vlmul_mag; // @[Integration.scala:36:21] wire [5:0] _vfu_io_issue_bits_vstart; // @[Integration.scala:36:21] wire [2:0] _vfu_io_issue_bits_segstart; // @[Integration.scala:36:21] wire [2:0] _vfu_io_issue_bits_segend; // @[Integration.scala:36:21] wire [63:0] _vfu_io_issue_bits_rs1_data; // @[Integration.scala:36:21] wire [63:0] _vfu_io_issue_bits_rs2_data; // @[Integration.scala:36:21] wire [19:0] _vfu_io_issue_bits_page; // @[Integration.scala:36:21] wire [2:0] _vfu_io_issue_bits_rm; // @[Integration.scala:36:21] wire [1:0] _vfu_io_issue_bits_emul; // @[Integration.scala:36:21] wire [1:0] _vfu_io_issue_bits_mop; // @[Integration.scala:36:21] wire _vfu_io_index_access_valid; // @[Integration.scala:36:21] wire [4:0] _vfu_io_index_access_vrs; // @[Integration.scala:36:21] wire [6:0] _vfu_io_index_access_eidx; // @[Integration.scala:36:21] wire [1:0] _vfu_io_index_access_eew; // @[Integration.scala:36:21] wire _vfu_io_mask_access_valid; // @[Integration.scala:36:21] wire [6:0] _vfu_io_mask_access_eidx; // @[Integration.scala:36:21] wire [39:0] _vfu_io_scalar_check_addr; // @[Integration.scala:36:21] wire _vfu_io_scalar_check_store; // @[Integration.scala:36:21] wire _dis_io_issue_ready; // @[Integration.scala:35:21] wire _dis_io_mem_valid; // @[Integration.scala:35:21] wire [15:0] _dis_io_mem_bits_debug_id; // @[Integration.scala:35:21] wire [11:0] _dis_io_mem_bits_base_offset; // @[Integration.scala:35:21] wire [19:0] _dis_io_mem_bits_page; // @[Integration.scala:35:21] wire [11:0] _dis_io_mem_bits_stride; // @[Integration.scala:35:21] wire [2:0] _dis_io_mem_bits_segstart; // @[Integration.scala:35:21] wire [2:0] _dis_io_mem_bits_segend; // @[Integration.scala:35:21] wire [5:0] _dis_io_mem_bits_vstart; // @[Integration.scala:35:21] wire [6:0] _dis_io_mem_bits_vl; // @[Integration.scala:35:21] wire [1:0] _dis_io_mem_bits_mop; // @[Integration.scala:35:21] wire _dis_io_mem_bits_vm; // @[Integration.scala:35:21] wire [2:0] _dis_io_mem_bits_nf; // @[Integration.scala:35:21] wire [1:0] _dis_io_mem_bits_idx_size; // @[Integration.scala:35:21] wire [1:0] _dis_io_mem_bits_elem_size; // @[Integration.scala:35:21] wire _dis_io_mem_bits_whole_reg; // @[Integration.scala:35:21] wire _dis_io_mem_bits_store; // @[Integration.scala:35:21] wire _dis_io_dis_valid; // @[Integration.scala:35:21] wire [31:0] _dis_io_dis_bits_bits; // @[Integration.scala:35:21] wire [6:0] _dis_io_dis_bits_vconfig_vl; // @[Integration.scala:35:21] wire [2:0] _dis_io_dis_bits_vconfig_vtype_vsew; // @[Integration.scala:35:21] wire _dis_io_dis_bits_vconfig_vtype_vlmul_sign; // @[Integration.scala:35:21] wire [1:0] _dis_io_dis_bits_vconfig_vtype_vlmul_mag; // @[Integration.scala:35:21] wire [5:0] _dis_io_dis_bits_vstart; // @[Integration.scala:35:21] wire [2:0] _dis_io_dis_bits_segstart; // @[Integration.scala:35:21] wire [2:0] _dis_io_dis_bits_segend; // @[Integration.scala:35:21] wire [63:0] _dis_io_dis_bits_rs1_data; // @[Integration.scala:35:21] wire [2:0] _dis_io_dis_bits_vat; // @[Integration.scala:35:21] wire [2:0] _dis_io_dis_bits_rm; // @[Integration.scala:35:21] wire [1:0] _dis_io_dis_bits_emul; // @[Integration.scala:35:21] wire [15:0] _dis_io_dis_bits_debug_id; // @[Integration.scala:35:21] wire [1:0] _dis_io_dis_bits_mop; // @[Integration.scala:35:21] wire _dis_io_scalar_resp_valid; // @[Integration.scala:35:21] wire [63:0] _dis_io_scalar_resp_bits_data; // @[Integration.scala:35:21] wire [4:0] _dis_io_scalar_resp_bits_rd; // @[Integration.scala:35:21] wire [2:0] _dis_io_vat_head; // @[Integration.scala:35:21] wire [2:0] _dis_io_vat_tail; // @[Integration.scala:35:21] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _tl_if_auto_arb_anon_out_a_valid; // @[Integration.scala:27:25] wire [2:0] _tl_if_auto_arb_anon_out_a_bits_opcode; // @[Integration.scala:27:25] wire [3:0] _tl_if_auto_arb_anon_out_a_bits_size; // @[Integration.scala:27:25] wire [4:0] _tl_if_auto_arb_anon_out_a_bits_source; // @[Integration.scala:27:25] wire [31:0] _tl_if_auto_arb_anon_out_a_bits_address; // @[Integration.scala:27:25] wire [7:0] _tl_if_auto_arb_anon_out_a_bits_mask; // @[Integration.scala:27:25] wire [63:0] _tl_if_auto_arb_anon_out_a_bits_data; // @[Integration.scala:27:25] wire _tl_if_auto_arb_anon_out_d_ready; // @[Integration.scala:27:25] wire _tl_if_io_vec_load_req_ready; // @[Integration.scala:27:25] wire _tl_if_io_vec_load_resp_valid; // @[Integration.scala:27:25] wire [63:0] _tl_if_io_vec_load_resp_bits_data; // @[Integration.scala:27:25] wire [3:0] _tl_if_io_vec_load_resp_bits_tag; // @[Integration.scala:27:25] wire _tl_if_io_vec_store_req_ready; // @[Integration.scala:27:25] wire _tl_if_io_vec_store_ack_valid; // @[Integration.scala:27:25] wire [3:0] _tl_if_io_vec_store_ack_bits_tag; // @[Integration.scala:27:25] wire _tl_if_io_mem_busy; // @[Integration.scala:27:25] TLSplitInterface tl_if ( // @[Integration.scala:27:25] .clock (clock), .reset (reset), .auto_arb_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_arb_anon_out_a_valid (_tl_if_auto_arb_anon_out_a_valid), .auto_arb_anon_out_a_bits_opcode (_tl_if_auto_arb_anon_out_a_bits_opcode), .auto_arb_anon_out_a_bits_size (_tl_if_auto_arb_anon_out_a_bits_size), .auto_arb_anon_out_a_bits_source (_tl_if_auto_arb_anon_out_a_bits_source), .auto_arb_anon_out_a_bits_address (_tl_if_auto_arb_anon_out_a_bits_address), .auto_arb_anon_out_a_bits_mask (_tl_if_auto_arb_anon_out_a_bits_mask), .auto_arb_anon_out_a_bits_data (_tl_if_auto_arb_anon_out_a_bits_data), .auto_arb_anon_out_d_ready (_tl_if_auto_arb_anon_out_d_ready), .auto_arb_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .io_vec_load_req_ready (_tl_if_io_vec_load_req_ready), .io_vec_load_req_valid (_vmu_io_dmem_load_req_valid & ~_hella_if_io_mem_busy), // @[Integration.scala:38:21, :40:26, :79:{29,32}] .io_vec_load_req_bits_addr (_vmu_io_dmem_load_req_bits_addr), // @[Integration.scala:38:21] .io_vec_load_req_bits_tag (_vmu_io_dmem_load_req_bits_tag), // @[Integration.scala:38:21] .io_vec_load_resp_valid (_tl_if_io_vec_load_resp_valid), .io_vec_load_resp_bits_data (_tl_if_io_vec_load_resp_bits_data), .io_vec_load_resp_bits_tag (_tl_if_io_vec_load_resp_bits_tag), .io_vec_store_req_ready (_tl_if_io_vec_store_req_ready), .io_vec_store_req_valid (_vmu_io_dmem_store_req_valid & ~_hella_if_io_mem_busy), // @[Integration.scala:38:21, :40:26, :79:{29,32}] .io_vec_store_req_bits_addr (_vmu_io_dmem_store_req_bits_addr), // @[Integration.scala:38:21] .io_vec_store_req_bits_data (_vmu_io_dmem_store_req_bits_data), // @[Integration.scala:38:21] .io_vec_store_req_bits_mask (_vmu_io_dmem_store_req_bits_mask), // @[Integration.scala:38:21] .io_vec_store_req_bits_tag (_vmu_io_dmem_store_req_bits_tag), // @[Integration.scala:38:21] .io_vec_store_ack_valid (_tl_if_io_vec_store_ack_valid), .io_vec_store_ack_bits_tag (_tl_if_io_vec_store_ack_bits_tag), .io_mem_busy (_tl_if_io_mem_busy) ); // @[Integration.scala:27:25] TLBuffer_a32d64s5k3z4u_1 buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_tl_if_auto_arb_anon_out_a_valid), // @[Integration.scala:27:25] .auto_in_a_bits_opcode (_tl_if_auto_arb_anon_out_a_bits_opcode), // @[Integration.scala:27:25] .auto_in_a_bits_size (_tl_if_auto_arb_anon_out_a_bits_size), // @[Integration.scala:27:25] .auto_in_a_bits_source (_tl_if_auto_arb_anon_out_a_bits_source), // @[Integration.scala:27:25] .auto_in_a_bits_address (_tl_if_auto_arb_anon_out_a_bits_address), // @[Integration.scala:27:25] .auto_in_a_bits_mask (_tl_if_auto_arb_anon_out_a_bits_mask), // @[Integration.scala:27:25] .auto_in_a_bits_data (_tl_if_auto_arb_anon_out_a_bits_data), // @[Integration.scala:27:25] .auto_in_d_ready (_tl_if_auto_arb_anon_out_d_ready), // @[Integration.scala:27:25] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_atl_out_a_ready), .auto_out_a_valid (auto_atl_out_a_valid), .auto_out_a_bits_opcode (auto_atl_out_a_bits_opcode), .auto_out_a_bits_param (auto_atl_out_a_bits_param), .auto_out_a_bits_size (auto_atl_out_a_bits_size), .auto_out_a_bits_source (auto_atl_out_a_bits_source), .auto_out_a_bits_address (auto_atl_out_a_bits_address), .auto_out_a_bits_mask (auto_atl_out_a_bits_mask), .auto_out_a_bits_data (auto_atl_out_a_bits_data), .auto_out_a_bits_corrupt (auto_atl_out_a_bits_corrupt), .auto_out_d_ready (auto_atl_out_d_ready), .auto_out_d_valid (auto_atl_out_d_valid), .auto_out_d_bits_opcode (auto_atl_out_d_bits_opcode), .auto_out_d_bits_param (auto_atl_out_d_bits_param), .auto_out_d_bits_size (auto_atl_out_d_bits_size), .auto_out_d_bits_source (auto_atl_out_d_bits_source), .auto_out_d_bits_sink (auto_atl_out_d_bits_sink), .auto_out_d_bits_denied (auto_atl_out_d_bits_denied), .auto_out_d_bits_data (auto_atl_out_d_bits_data), .auto_out_d_bits_corrupt (auto_atl_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] VectorDispatcher dis ( // @[Integration.scala:35:21] .clock (clock), .reset (reset), .io_issue_ready (_dis_io_issue_ready), .io_issue_valid (_vfu_io_issue_valid), // @[Integration.scala:36:21] .io_issue_bits_bits (_vfu_io_issue_bits_bits), // @[Integration.scala:36:21] .io_issue_bits_vconfig_vl (_vfu_io_issue_bits_vconfig_vl), // @[Integration.scala:36:21] .io_issue_bits_vconfig_vtype_vsew (_vfu_io_issue_bits_vconfig_vtype_vsew), // @[Integration.scala:36:21] .io_issue_bits_vconfig_vtype_vlmul_sign (_vfu_io_issue_bits_vconfig_vtype_vlmul_sign), // @[Integration.scala:36:21] .io_issue_bits_vconfig_vtype_vlmul_mag (_vfu_io_issue_bits_vconfig_vtype_vlmul_mag), // @[Integration.scala:36:21] .io_issue_bits_vstart (_vfu_io_issue_bits_vstart), // @[Integration.scala:36:21] .io_issue_bits_segstart (_vfu_io_issue_bits_segstart), // @[Integration.scala:36:21] .io_issue_bits_segend (_vfu_io_issue_bits_segend), // @[Integration.scala:36:21] .io_issue_bits_rs1_data (_vfu_io_issue_bits_rs1_data), // @[Integration.scala:36:21] .io_issue_bits_rs2_data (_vfu_io_issue_bits_rs2_data), // @[Integration.scala:36:21] .io_issue_bits_page (_vfu_io_issue_bits_page), // @[Integration.scala:36:21] .io_issue_bits_rm (_vfu_io_issue_bits_rm), // @[Integration.scala:36:21] .io_issue_bits_emul (_vfu_io_issue_bits_emul), // @[Integration.scala:36:21] .io_issue_bits_mop (_vfu_io_issue_bits_mop), // @[Integration.scala:36:21] .io_mem_ready (_vmu_io_enq_ready), // @[Integration.scala:38:21] .io_mem_valid (_dis_io_mem_valid), .io_mem_bits_debug_id (_dis_io_mem_bits_debug_id), .io_mem_bits_base_offset (_dis_io_mem_bits_base_offset), .io_mem_bits_page (_dis_io_mem_bits_page), .io_mem_bits_stride (_dis_io_mem_bits_stride), .io_mem_bits_segstart (_dis_io_mem_bits_segstart), .io_mem_bits_segend (_dis_io_mem_bits_segend), .io_mem_bits_vstart (_dis_io_mem_bits_vstart), .io_mem_bits_vl (_dis_io_mem_bits_vl), .io_mem_bits_mop (_dis_io_mem_bits_mop), .io_mem_bits_vm (_dis_io_mem_bits_vm), .io_mem_bits_nf (_dis_io_mem_bits_nf), .io_mem_bits_idx_size (_dis_io_mem_bits_idx_size), .io_mem_bits_elem_size (_dis_io_mem_bits_elem_size), .io_mem_bits_whole_reg (_dis_io_mem_bits_whole_reg), .io_mem_bits_store (_dis_io_mem_bits_store), .io_dis_ready (_vu_io_dis_ready), // @[Integration.scala:37:20] .io_dis_valid (_dis_io_dis_valid), .io_dis_bits_bits (_dis_io_dis_bits_bits), .io_dis_bits_vconfig_vl (_dis_io_dis_bits_vconfig_vl), .io_dis_bits_vconfig_vtype_vsew (_dis_io_dis_bits_vconfig_vtype_vsew), .io_dis_bits_vconfig_vtype_vlmul_sign (_dis_io_dis_bits_vconfig_vtype_vlmul_sign), .io_dis_bits_vconfig_vtype_vlmul_mag (_dis_io_dis_bits_vconfig_vtype_vlmul_mag), .io_dis_bits_vstart (_dis_io_dis_bits_vstart), .io_dis_bits_segstart (_dis_io_dis_bits_segstart), .io_dis_bits_segend (_dis_io_dis_bits_segend), .io_dis_bits_rs1_data (_dis_io_dis_bits_rs1_data), .io_dis_bits_vat (_dis_io_dis_bits_vat), .io_dis_bits_rm (_dis_io_dis_bits_rm), .io_dis_bits_emul (_dis_io_dis_bits_emul), .io_dis_bits_debug_id (_dis_io_dis_bits_debug_id), .io_dis_bits_mop (_dis_io_dis_bits_mop), .io_scalar_resp_ready (_scalar_arb_io_in_1_ready), // @[Integration.scala:41:28] .io_scalar_resp_valid (_dis_io_scalar_resp_valid), .io_scalar_resp_bits_data (_dis_io_scalar_resp_bits_data), .io_scalar_resp_bits_rd (_dis_io_scalar_resp_bits_rd), .io_vat_release_0_valid (_vu_io_vat_release_0_valid), // @[Integration.scala:37:20] .io_vat_release_0_bits (_vu_io_vat_release_0_bits), // @[Integration.scala:37:20] .io_vat_release_1_valid (_vu_io_vat_release_1_valid), // @[Integration.scala:37:20] .io_vat_release_1_bits (_vu_io_vat_release_1_bits), // @[Integration.scala:37:20] .io_vat_release_2_valid (_vu_io_vat_release_2_valid), // @[Integration.scala:37:20] .io_vat_release_2_bits (_vu_io_vat_release_2_bits), // @[Integration.scala:37:20] .io_vat_head (_dis_io_vat_head), .io_vat_tail (_dis_io_vat_tail) ); // @[Integration.scala:35:21] SaturnRocketFrontend vfu ( // @[Integration.scala:36:21] .clock (clock), .reset (reset), .io_core_status_prv (io_core_status_prv), .io_core_ex_valid (io_core_ex_valid), .io_core_ex_ready (io_core_ex_ready), .io_core_ex_inst (io_core_ex_inst), .io_core_ex_pc (io_core_ex_pc), .io_core_ex_vconfig_vl (io_core_ex_vconfig_vl), .io_core_ex_vconfig_vtype_vill (io_core_ex_vconfig_vtype_vill), .io_core_ex_vconfig_vtype_reserved (io_core_ex_vconfig_vtype_reserved), .io_core_ex_vconfig_vtype_vma (io_core_ex_vconfig_vtype_vma), .io_core_ex_vconfig_vtype_vta (io_core_ex_vconfig_vtype_vta), .io_core_ex_vconfig_vtype_vsew (io_core_ex_vconfig_vtype_vsew), .io_core_ex_vconfig_vtype_vlmul_sign (io_core_ex_vconfig_vtype_vlmul_sign), .io_core_ex_vconfig_vtype_vlmul_mag (io_core_ex_vconfig_vtype_vlmul_mag), .io_core_ex_vstart (io_core_ex_vstart), .io_core_ex_rs1 (io_core_ex_rs1), .io_core_ex_rs2 (io_core_ex_rs2), .io_core_killm (io_core_killm), .io_core_mem_frs1 (io_core_mem_frs1), .io_core_mem_block_mem (io_core_mem_block_mem), .io_core_mem_block_all (io_core_mem_block_all), .io_core_wb_store_pending (io_core_wb_store_pending), .io_core_wb_replay (io_core_wb_replay), .io_core_wb_retire (io_core_wb_retire), .io_core_wb_inst (io_core_wb_inst), .io_core_wb_pc (io_core_wb_pc), .io_core_wb_xcpt (io_core_wb_xcpt), .io_core_wb_cause (io_core_wb_cause), .io_core_wb_tval (io_core_wb_tval), .io_core_wb_vxrm (io_core_wb_vxrm), .io_core_wb_frm (io_core_wb_frm), .io_core_set_vstart_valid (io_core_set_vstart_valid), .io_core_set_vstart_bits (io_core_set_vstart_bits), .io_core_set_vconfig_valid (io_core_set_vconfig_valid), .io_core_set_vconfig_bits_vl (io_core_set_vconfig_bits_vl), .io_core_set_vconfig_bits_vtype_vill (io_core_set_vconfig_bits_vtype_vill), .io_core_set_vconfig_bits_vtype_reserved (io_core_set_vconfig_bits_vtype_reserved), .io_core_set_vconfig_bits_vtype_vma (io_core_set_vconfig_bits_vtype_vma), .io_core_set_vconfig_bits_vtype_vta (io_core_set_vconfig_bits_vtype_vta), .io_core_set_vconfig_bits_vtype_vsew (io_core_set_vconfig_bits_vtype_vsew), .io_core_set_vconfig_bits_vtype_vlmul_sign (io_core_set_vconfig_bits_vtype_vlmul_sign), .io_core_set_vconfig_bits_vtype_vlmul_mag (io_core_set_vconfig_bits_vtype_vlmul_mag), .io_core_trap_check_busy (io_core_trap_check_busy), .io_tlb_req_valid (io_tlb_req_valid), .io_tlb_req_bits_vaddr (io_tlb_req_bits_vaddr), .io_tlb_req_bits_size (io_tlb_req_bits_size), .io_tlb_req_bits_cmd (io_tlb_req_bits_cmd), .io_tlb_req_bits_prv (io_tlb_req_bits_prv), .io_tlb_s1_resp_miss (io_tlb_s1_resp_miss), .io_tlb_s1_resp_paddr (io_tlb_s1_resp_paddr), .io_tlb_s1_resp_pf_ld (io_tlb_s1_resp_pf_ld), .io_tlb_s1_resp_pf_st (io_tlb_s1_resp_pf_st), .io_tlb_s1_resp_ae_ld (io_tlb_s1_resp_ae_ld), .io_tlb_s1_resp_ae_st (io_tlb_s1_resp_ae_st), .io_tlb_s1_resp_ma_ld (io_tlb_s1_resp_ma_ld), .io_tlb_s1_resp_ma_st (io_tlb_s1_resp_ma_st), .io_tlb_s1_resp_cmd (io_tlb_s1_resp_cmd), .io_issue_ready (_dis_io_issue_ready), // @[Integration.scala:35:21] .io_issue_valid (_vfu_io_issue_valid), .io_issue_bits_bits (_vfu_io_issue_bits_bits), .io_issue_bits_vconfig_vl (_vfu_io_issue_bits_vconfig_vl), .io_issue_bits_vconfig_vtype_vsew (_vfu_io_issue_bits_vconfig_vtype_vsew), .io_issue_bits_vconfig_vtype_vlmul_sign (_vfu_io_issue_bits_vconfig_vtype_vlmul_sign), .io_issue_bits_vconfig_vtype_vlmul_mag (_vfu_io_issue_bits_vconfig_vtype_vlmul_mag), .io_issue_bits_vstart (_vfu_io_issue_bits_vstart), .io_issue_bits_segstart (_vfu_io_issue_bits_segstart), .io_issue_bits_segend (_vfu_io_issue_bits_segend), .io_issue_bits_rs1_data (_vfu_io_issue_bits_rs1_data), .io_issue_bits_rs2_data (_vfu_io_issue_bits_rs2_data), .io_issue_bits_page (_vfu_io_issue_bits_page), .io_issue_bits_rm (_vfu_io_issue_bits_rm), .io_issue_bits_emul (_vfu_io_issue_bits_emul), .io_issue_bits_mop (_vfu_io_issue_bits_mop), .io_index_access_ready (_vu_io_index_access_ready), // @[Integration.scala:37:20] .io_index_access_valid (_vfu_io_index_access_valid), .io_index_access_vrs (_vfu_io_index_access_vrs), .io_index_access_eidx (_vfu_io_index_access_eidx), .io_index_access_eew (_vfu_io_index_access_eew), .io_index_access_idx (_vu_io_index_access_idx), // @[Integration.scala:37:20] .io_mask_access_ready (_vu_io_mask_access_ready), // @[Integration.scala:37:20] .io_mask_access_valid (_vfu_io_mask_access_valid), .io_mask_access_eidx (_vfu_io_mask_access_eidx), .io_mask_access_mask (_vu_io_mask_access_mask), // @[Integration.scala:37:20] .io_scalar_check_addr (_vfu_io_scalar_check_addr), .io_scalar_check_store (_vfu_io_scalar_check_store), .io_scalar_check_conflict (_vmu_io_scalar_check_conflict) // @[Integration.scala:38:21] ); // @[Integration.scala:36:21] VectorBackend vu ( // @[Integration.scala:37:20] .clock (clock), .reset (reset), .io_dis_ready (_vu_io_dis_ready), .io_dis_valid (_dis_io_dis_valid), // @[Integration.scala:35:21] .io_dis_bits_bits (_dis_io_dis_bits_bits), // @[Integration.scala:35:21] .io_dis_bits_vconfig_vl (_dis_io_dis_bits_vconfig_vl), // @[Integration.scala:35:21] .io_dis_bits_vconfig_vtype_vsew (_dis_io_dis_bits_vconfig_vtype_vsew), // @[Integration.scala:35:21] .io_dis_bits_vconfig_vtype_vlmul_sign (_dis_io_dis_bits_vconfig_vtype_vlmul_sign), // @[Integration.scala:35:21] .io_dis_bits_vconfig_vtype_vlmul_mag (_dis_io_dis_bits_vconfig_vtype_vlmul_mag), // @[Integration.scala:35:21] .io_dis_bits_vstart (_dis_io_dis_bits_vstart), // @[Integration.scala:35:21] .io_dis_bits_segstart (_dis_io_dis_bits_segstart), // @[Integration.scala:35:21] .io_dis_bits_segend (_dis_io_dis_bits_segend), // @[Integration.scala:35:21] .io_dis_bits_rs1_data (_dis_io_dis_bits_rs1_data), // @[Integration.scala:35:21] .io_dis_bits_vat (_dis_io_dis_bits_vat), // @[Integration.scala:35:21] .io_dis_bits_rm (_dis_io_dis_bits_rm), // @[Integration.scala:35:21] .io_dis_bits_emul (_dis_io_dis_bits_emul), // @[Integration.scala:35:21] .io_dis_bits_debug_id (_dis_io_dis_bits_debug_id), // @[Integration.scala:35:21] .io_dis_bits_mop (_dis_io_dis_bits_mop), // @[Integration.scala:35:21] .io_vmu_lresp_ready (_vu_io_vmu_lresp_ready), .io_vmu_lresp_valid (_vmu_io_vu_lresp_valid), // @[Integration.scala:38:21] .io_vmu_lresp_bits_data (_vmu_io_vu_lresp_bits_data), // @[Integration.scala:38:21] .io_vmu_lresp_bits_debug_id (_vmu_io_vu_lresp_bits_debug_id), // @[Integration.scala:38:21] .io_vmu_sdata_ready (_vmu_io_vu_sdata_ready), // @[Integration.scala:38:21] .io_vmu_sdata_valid (_vu_io_vmu_sdata_valid), .io_vmu_sdata_bits_stdata (_vu_io_vmu_sdata_bits_stdata), .io_vmu_sdata_bits_stmask (_vu_io_vmu_sdata_bits_stmask), .io_vmu_sdata_bits_debug_id (_vu_io_vmu_sdata_bits_debug_id), .io_vmu_mask_pop_ready (_vu_io_vmu_mask_pop_ready), .io_vmu_mask_pop_valid (_vmu_io_vu_mask_pop_valid), // @[Integration.scala:38:21] .io_vmu_mask_data_0 (_vu_io_vmu_mask_data_0), .io_vmu_index_pop_ready (_vu_io_vmu_index_pop_ready), .io_vmu_index_pop_valid (_vmu_io_vu_index_pop_valid), // @[Integration.scala:38:21] .io_vmu_index_pop_bits_tail (_vmu_io_vu_index_pop_bits_tail), // @[Integration.scala:38:21] .io_vmu_index_data_0 (_vu_io_vmu_index_data_0), .io_vmu_index_data_1 (_vu_io_vmu_index_data_1), .io_vmu_index_data_2 (_vu_io_vmu_index_data_2), .io_vmu_index_data_3 (_vu_io_vmu_index_data_3), .io_vmu_index_data_4 (_vu_io_vmu_index_data_4), .io_vmu_index_data_5 (_vu_io_vmu_index_data_5), .io_vmu_index_data_6 (_vu_io_vmu_index_data_6), .io_vmu_index_data_7 (_vu_io_vmu_index_data_7), .io_busy (_vu_io_busy), .io_index_access_ready (_vu_io_index_access_ready), .io_index_access_valid (_vfu_io_index_access_valid), // @[Integration.scala:36:21] .io_index_access_vrs (_vfu_io_index_access_vrs), // @[Integration.scala:36:21] .io_index_access_eidx (_vfu_io_index_access_eidx), // @[Integration.scala:36:21] .io_index_access_eew (_vfu_io_index_access_eew), // @[Integration.scala:36:21] .io_index_access_idx (_vu_io_index_access_idx), .io_mask_access_ready (_vu_io_mask_access_ready), .io_mask_access_valid (_vfu_io_mask_access_valid), // @[Integration.scala:36:21] .io_mask_access_eidx (_vfu_io_mask_access_eidx), // @[Integration.scala:36:21] .io_mask_access_mask (_vu_io_mask_access_mask), .io_scalar_resp_ready (_scalar_arb_io_in_0_ready), // @[Integration.scala:41:28] .io_scalar_resp_valid (_vu_io_scalar_resp_valid), .io_scalar_resp_bits_data (_vu_io_scalar_resp_bits_data), .io_scalar_resp_bits_fp (_vu_io_scalar_resp_bits_fp), .io_scalar_resp_bits_size (_vu_io_scalar_resp_bits_size), .io_scalar_resp_bits_rd (_vu_io_scalar_resp_bits_rd), .io_set_vxsat (io_core_set_vxsat), .io_fp_req_ready (io_fp_req_ready), .io_fp_req_valid (io_fp_req_valid), .io_fp_req_bits_ren2 (io_fp_req_bits_ren2), .io_fp_req_bits_ren3 (io_fp_req_bits_ren3), .io_fp_req_bits_swap23 (io_fp_req_bits_swap23), .io_fp_req_bits_typeTagIn (io_fp_req_bits_typeTagIn), .io_fp_req_bits_typeTagOut (io_fp_req_bits_typeTagOut), .io_fp_req_bits_fromint (io_fp_req_bits_fromint), .io_fp_req_bits_toint (io_fp_req_bits_toint), .io_fp_req_bits_fastpipe (io_fp_req_bits_fastpipe), .io_fp_req_bits_fma (io_fp_req_bits_fma), .io_fp_req_bits_div (io_fp_req_bits_div), .io_fp_req_bits_sqrt (io_fp_req_bits_sqrt), .io_fp_req_bits_wflags (io_fp_req_bits_wflags), .io_fp_req_bits_rm (io_fp_req_bits_rm), .io_fp_req_bits_fmaCmd (io_fp_req_bits_fmaCmd), .io_fp_req_bits_typ (io_fp_req_bits_typ), .io_fp_req_bits_in1 (io_fp_req_bits_in1), .io_fp_req_bits_in2 (io_fp_req_bits_in2), .io_fp_req_bits_in3 (io_fp_req_bits_in3), .io_fp_resp_valid (io_fp_resp_valid), .io_fp_resp_bits_data (io_fp_resp_bits_data), .io_vat_tail (_dis_io_vat_tail), // @[Integration.scala:35:21] .io_vat_head (_dis_io_vat_head), // @[Integration.scala:35:21] .io_vat_release_0_valid (_vu_io_vat_release_0_valid), .io_vat_release_0_bits (_vu_io_vat_release_0_bits), .io_vat_release_1_valid (_vu_io_vat_release_1_valid), .io_vat_release_1_bits (_vu_io_vat_release_1_bits), .io_vat_release_2_valid (_vu_io_vat_release_2_valid), .io_vat_release_2_bits (_vu_io_vat_release_2_bits) ); // @[Integration.scala:37:20] VectorMemUnit vmu ( // @[Integration.scala:38:21] .clock (clock), .reset (reset), .io_enq_ready (_vmu_io_enq_ready), .io_enq_valid (_dis_io_mem_valid), // @[Integration.scala:35:21] .io_enq_bits_debug_id (_dis_io_mem_bits_debug_id), // @[Integration.scala:35:21] .io_enq_bits_base_offset (_dis_io_mem_bits_base_offset), // @[Integration.scala:35:21] .io_enq_bits_page (_dis_io_mem_bits_page), // @[Integration.scala:35:21] .io_enq_bits_stride (_dis_io_mem_bits_stride), // @[Integration.scala:35:21] .io_enq_bits_segstart (_dis_io_mem_bits_segstart), // @[Integration.scala:35:21] .io_enq_bits_segend (_dis_io_mem_bits_segend), // @[Integration.scala:35:21] .io_enq_bits_vstart (_dis_io_mem_bits_vstart), // @[Integration.scala:35:21] .io_enq_bits_vl (_dis_io_mem_bits_vl), // @[Integration.scala:35:21] .io_enq_bits_mop (_dis_io_mem_bits_mop), // @[Integration.scala:35:21] .io_enq_bits_vm (_dis_io_mem_bits_vm), // @[Integration.scala:35:21] .io_enq_bits_nf (_dis_io_mem_bits_nf), // @[Integration.scala:35:21] .io_enq_bits_idx_size (_dis_io_mem_bits_idx_size), // @[Integration.scala:35:21] .io_enq_bits_elem_size (_dis_io_mem_bits_elem_size), // @[Integration.scala:35:21] .io_enq_bits_whole_reg (_dis_io_mem_bits_whole_reg), // @[Integration.scala:35:21] .io_enq_bits_store (_dis_io_mem_bits_store), // @[Integration.scala:35:21] .io_dmem_load_req_ready (_tl_if_io_vec_load_req_ready & ~_hella_if_io_mem_busy), // @[Integration.scala:27:25, :40:26, :79:32, :80:29] .io_dmem_load_req_valid (_vmu_io_dmem_load_req_valid), .io_dmem_load_req_bits_addr (_vmu_io_dmem_load_req_bits_addr), .io_dmem_load_req_bits_tag (_vmu_io_dmem_load_req_bits_tag), .io_dmem_load_resp_valid (_tl_if_io_vec_load_resp_valid | _hella_if_io_vec_load_resp_valid), // @[Integration.scala:27:25, :40:26, :91:72] .io_dmem_load_resp_bits_data ((_tl_if_io_vec_load_resp_valid ? _tl_if_io_vec_load_resp_bits_data : 64'h0) | (_hella_if_io_vec_load_resp_valid ? _hella_if_io_vec_load_resp_bits_data : 64'h0)), // @[Mux.scala:30:73] .io_dmem_load_resp_bits_tag ((_tl_if_io_vec_load_resp_valid ? _tl_if_io_vec_load_resp_bits_tag : 4'h0) | (_hella_if_io_vec_load_resp_valid ? _hella_if_io_vec_load_resp_bits_tag : 4'h0)), // @[Mux.scala:30:73] .io_dmem_store_req_ready (_tl_if_io_vec_store_req_ready & ~_hella_if_io_mem_busy), // @[Integration.scala:27:25, :40:26, :79:32, :80:29] .io_dmem_store_req_valid (_vmu_io_dmem_store_req_valid), .io_dmem_store_req_bits_addr (_vmu_io_dmem_store_req_bits_addr), .io_dmem_store_req_bits_data (_vmu_io_dmem_store_req_bits_data), .io_dmem_store_req_bits_mask (_vmu_io_dmem_store_req_bits_mask), .io_dmem_store_req_bits_tag (_vmu_io_dmem_store_req_bits_tag), .io_dmem_store_ack_valid (_tl_if_io_vec_store_ack_valid | _hella_if_io_vec_store_ack_valid), // @[Integration.scala:27:25, :40:26, :95:72] .io_dmem_store_ack_bits_tag ((_tl_if_io_vec_store_ack_valid ? _tl_if_io_vec_store_ack_bits_tag : 4'h0) | (_hella_if_io_vec_store_ack_valid ? _hella_if_io_vec_store_ack_bits_tag : 4'h0)), // @[Mux.scala:30:73] .io_scalar_check_addr (_vfu_io_scalar_check_addr), // @[Integration.scala:36:21] .io_scalar_check_store (_vfu_io_scalar_check_store), // @[Integration.scala:36:21] .io_scalar_check_conflict (_vmu_io_scalar_check_conflict), .io_vu_lresp_ready (_vu_io_vmu_lresp_ready), // @[Integration.scala:37:20] .io_vu_lresp_valid (_vmu_io_vu_lresp_valid), .io_vu_lresp_bits_data (_vmu_io_vu_lresp_bits_data), .io_vu_lresp_bits_debug_id (_vmu_io_vu_lresp_bits_debug_id), .io_vu_sdata_ready (_vmu_io_vu_sdata_ready), .io_vu_sdata_valid (_vu_io_vmu_sdata_valid), // @[Integration.scala:37:20] .io_vu_sdata_bits_stdata (_vu_io_vmu_sdata_bits_stdata), // @[Integration.scala:37:20] .io_vu_sdata_bits_stmask (_vu_io_vmu_sdata_bits_stmask), // @[Integration.scala:37:20] .io_vu_sdata_bits_debug_id (_vu_io_vmu_sdata_bits_debug_id), // @[Integration.scala:37:20] .io_vu_mask_pop_ready (_vu_io_vmu_mask_pop_ready), // @[Integration.scala:37:20] .io_vu_mask_pop_valid (_vmu_io_vu_mask_pop_valid), .io_vu_mask_data_0 (_vu_io_vmu_mask_data_0), // @[Integration.scala:37:20] .io_vu_index_pop_ready (_vu_io_vmu_index_pop_ready), // @[Integration.scala:37:20] .io_vu_index_pop_valid (_vmu_io_vu_index_pop_valid), .io_vu_index_pop_bits_tail (_vmu_io_vu_index_pop_bits_tail), .io_vu_index_data_0 (_vu_io_vmu_index_data_0), // @[Integration.scala:37:20] .io_vu_index_data_1 (_vu_io_vmu_index_data_1), // @[Integration.scala:37:20] .io_vu_index_data_2 (_vu_io_vmu_index_data_2), // @[Integration.scala:37:20] .io_vu_index_data_3 (_vu_io_vmu_index_data_3), // @[Integration.scala:37:20] .io_vu_index_data_4 (_vu_io_vmu_index_data_4), // @[Integration.scala:37:20] .io_vu_index_data_5 (_vu_io_vmu_index_data_5), // @[Integration.scala:37:20] .io_vu_index_data_6 (_vu_io_vmu_index_data_6), // @[Integration.scala:37:20] .io_vu_index_data_7 (_vu_io_vmu_index_data_7), // @[Integration.scala:37:20] .io_busy (_vmu_io_busy) ); // @[Integration.scala:38:21] HellaCacheInterface hella_if ( // @[Integration.scala:40:26] .clock (clock), .reset (reset), .io_status_dv (io_core_status_dv), .io_status_prv (io_core_status_prv), .io_dmem_req_ready (io_dmem_req_ready), .io_dmem_req_valid (io_dmem_req_valid), .io_dmem_req_bits_addr (io_dmem_req_bits_addr), .io_dmem_req_bits_tag (io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (io_dmem_req_bits_cmd), .io_dmem_req_bits_size (io_dmem_req_bits_size), .io_dmem_req_bits_signed (io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (io_dmem_req_bits_dv), .io_dmem_req_bits_phys (io_dmem_req_bits_phys), .io_dmem_req_bits_no_alloc (io_dmem_req_bits_no_alloc), .io_dmem_req_bits_no_xcpt (io_dmem_req_bits_no_xcpt), .io_dmem_req_bits_mask (io_dmem_req_bits_mask), .io_dmem_s1_data_data (io_dmem_s1_data_data), .io_dmem_s1_data_mask (io_dmem_s1_data_mask), .io_dmem_s2_nack (io_dmem_s2_nack), .io_dmem_resp_valid (io_dmem_resp_valid), .io_dmem_resp_bits_tag (io_dmem_resp_bits_tag), .io_dmem_resp_bits_data_raw (io_dmem_resp_bits_data_raw), .io_dmem_s2_xcpt_ma_ld (io_dmem_s2_xcpt_ma_ld), .io_dmem_s2_xcpt_ma_st (io_dmem_s2_xcpt_ma_st), .io_dmem_s2_xcpt_pf_ld (io_dmem_s2_xcpt_pf_ld), .io_dmem_s2_xcpt_pf_st (io_dmem_s2_xcpt_pf_st), .io_dmem_s2_xcpt_ae_ld (io_dmem_s2_xcpt_ae_ld), .io_dmem_s2_xcpt_ae_st (io_dmem_s2_xcpt_ae_st), .io_vec_load_req_ready (/* unused */), .io_vec_load_req_bits_addr (_vmu_io_dmem_load_req_bits_addr), // @[Integration.scala:38:21] .io_vec_load_req_bits_tag (_vmu_io_dmem_load_req_bits_tag), // @[Integration.scala:38:21] .io_vec_load_resp_valid (_hella_if_io_vec_load_resp_valid), .io_vec_load_resp_bits_data (_hella_if_io_vec_load_resp_bits_data), .io_vec_load_resp_bits_tag (_hella_if_io_vec_load_resp_bits_tag), .io_vec_store_req_ready (/* unused */), .io_vec_store_req_bits_addr (_vmu_io_dmem_store_req_bits_addr), // @[Integration.scala:38:21] .io_vec_store_req_bits_data (_vmu_io_dmem_store_req_bits_data), // @[Integration.scala:38:21] .io_vec_store_req_bits_mask (_vmu_io_dmem_store_req_bits_mask), // @[Integration.scala:38:21] .io_vec_store_req_bits_tag (_vmu_io_dmem_store_req_bits_tag), // @[Integration.scala:38:21] .io_vec_store_ack_valid (_hella_if_io_vec_store_ack_valid), .io_vec_store_ack_bits_tag (_hella_if_io_vec_store_ack_bits_tag), .io_mem_busy (_hella_if_io_mem_busy) ); // @[Integration.scala:40:26] Arbiter2_ScalarWrite scalar_arb ( // @[Integration.scala:41:28] .io_in_0_ready (_scalar_arb_io_in_0_ready), .io_in_0_valid (_vu_io_scalar_resp_valid), // @[Integration.scala:37:20] .io_in_0_bits_data (_vu_io_scalar_resp_bits_data), // @[Integration.scala:37:20] .io_in_0_bits_fp (_vu_io_scalar_resp_bits_fp), // @[Integration.scala:37:20] .io_in_0_bits_size (_vu_io_scalar_resp_bits_size), // @[Integration.scala:37:20] .io_in_0_bits_rd (_vu_io_scalar_resp_bits_rd), // @[Integration.scala:37:20] .io_in_1_ready (_scalar_arb_io_in_1_ready), .io_in_1_valid (_dis_io_scalar_resp_valid), // @[Integration.scala:35:21] .io_in_1_bits_data (_dis_io_scalar_resp_bits_data), // @[Integration.scala:35:21] .io_in_1_bits_rd (_dis_io_scalar_resp_bits_rd), // @[Integration.scala:35:21] .io_out_ready (_io_core_resp_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_out_valid (_scalar_arb_io_out_valid), .io_out_bits_data (_scalar_arb_io_out_bits_data), .io_out_bits_fp (_scalar_arb_io_out_bits_fp), .io_out_bits_size (_scalar_arb_io_out_bits_size), .io_out_bits_rd (_scalar_arb_io_out_bits_rd) ); // @[Integration.scala:41:28] Queue2_ScalarWrite io_core_resp_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_io_core_resp_q_io_enq_ready), .io_enq_valid (_scalar_arb_io_out_valid), // @[Integration.scala:41:28] .io_enq_bits_data (_scalar_arb_io_out_bits_data), // @[Integration.scala:41:28] .io_enq_bits_fp (_scalar_arb_io_out_bits_fp), // @[Integration.scala:41:28] .io_enq_bits_size (_scalar_arb_io_out_bits_size), // @[Integration.scala:41:28] .io_enq_bits_rd (_scalar_arb_io_out_bits_rd), // @[Integration.scala:41:28] .io_deq_ready (io_core_resp_ready), .io_deq_valid (io_core_resp_valid), .io_deq_bits_data (io_core_resp_bits_data), .io_deq_bits_fp (io_core_resp_bits_fp), .io_deq_bits_size (io_core_resp_bits_size), .io_deq_bits_rd (io_core_resp_bits_rd) ); // @[Decoupled.scala:362:21] assign io_core_backend_busy = _vu_io_busy | _tl_if_io_mem_busy | _hella_if_io_mem_busy | _vmu_io_busy; // @[Integration.scala:27:25, :31:9, :37:20, :38:21, :40:26, :59:{42,70,94}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_68( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module array_5_0_0( // @[DescribedSRAM.scala:17:26] input [7:0] R0_addr, input R0_en, input R0_clk, output [127:0] R0_data, input [7:0] W0_addr, input W0_en, input W0_clk, input [127:0] W0_data, input [1:0] W0_mask ); array_0_0_ext array_0_0_ext ( // @[DescribedSRAM.scala:17:26] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_172( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_116( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_192 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1467 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1467; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1467; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1540 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1540; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1540; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1467 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1393 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1393 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1393 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1393 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1393 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1439 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1439 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1408 = _T_1540 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1408 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1408 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1408 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1511 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1511 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1493 = _T_1540 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1493 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1493 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1493 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module rockettile_dcache_data_arrays_0( // @[DescribedSRAM.scala:17:26] input [10:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [31:0] RW0_wdata, output [31:0] RW0_rdata, input [3:0] RW0_wmask ); rockettile_dcache_data_arrays_0_ext rockettile_dcache_data_arrays_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_87( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_139( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_43( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module FixedClockBroadcast_7( // @[ClockGroup.scala:104:9] input auto_anon_in_clock, // @[LazyModuleImp.scala:107:25] input auto_anon_in_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_reset // @[LazyModuleImp.scala:107:25] ); assign auto_anon_out_6_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_6_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_5_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_5_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_4_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_4_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_3_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_3_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_2_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_2_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_1_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_1_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign auto_anon_out_0_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9] assign auto_anon_out_0_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File execution-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Execution Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // The issue window schedules micro-ops onto a specific execution pipeline // A given execution pipeline may contain multiple functional units; one or more // read ports, and one or more writeports. package boom.v4.exu import scala.collection.mutable.{ArrayBuffer} import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.{BP, SFenceReq, CSR} import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile import freechips.rocketchip.util._ import boom.v4.common._ import boom.v4.ifu.FTQInfo import boom.v4.util._ class Wakeup(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val bypassable = Bool() val speculative_mask = UInt(aluWidth.W) val rebusy = Bool() } class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = Bits(dataWidth.W) val predicated = Bool() // Was this predicated off? val fflags = Valid(UInt(tile.FPConstants.FLAGS_SZ.W)) } class MemGen(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) } class CSRResp(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = UInt(xLen.W) val addr = UInt(CSR.ADDRSZ.W) } abstract class ExecutionUnit(name: String)(implicit p: Parameters) extends BoomMultiIOModule { val fu_types = ArrayBuffer[(Int, Bool, String)]() def get_all_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, _, _) => { r(code) := true.B } } r } def get_ready_fu_types(): Vec[Bool] = { val r = WireInit(VecInit(Seq.fill(FC_SZ) { false.B })) fu_types.map { case (code, ready, _) => { when (ready) { r(code) := true.B } } } r } val io_kill = IO(Input(Bool())) val io_brupdate = IO(Input(new BrUpdateInfo)) val io_status = IO(Input(new freechips.rocketchip.rocket.MStatus)) val io_ready_fu_types = IO(Output(Vec(FC_SZ, Bool()))) val io_fcsr_rm = IO(Input(UInt(tile.FPConstants.RM_SZ.W))) override def toString = { BoomCoreStringPrefix(s"===${name}ExeUnit") + fu_types.map { case (_, _, s) => BoomCoreStringPrefix(s" - ${s}") }.reduce(_+_) } val io_iss_uop = IO(Input(Valid(new MicroOp))) val arb_uop = Reg(Valid(new MicroOp)) arb_uop.valid := io_iss_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, io_iss_uop.bits) arb_uop.bits := UpdateBrMask(io_brupdate, io_iss_uop.bits) val rrd_uop = Reg(Valid(new MicroOp)) rrd_uop.valid := arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) rrd_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) val exe_uop = Reg(Valid(new MicroOp)) exe_uop.valid := rrd_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, rrd_uop.bits) exe_uop.bits := UpdateBrMask(io_brupdate, rrd_uop.bits) } trait HasIrfReadPorts { this: ExecutionUnit => def nReaders: Int val io_arb_irf_reqs = IO(Vec(nReaders, Decoupled(UInt(maxPregSz.W)))) val io_arb_rebusys = IO(Input (Vec(lsuWidth, Valid(new Wakeup)))) val io_rrd_irf_resps = IO(Input (Vec(nReaders , UInt(xLen.W)))) val io_rrd_irf_bypasses = IO(Input (Vec(coreWidth + lsuWidth, Valid(new ExeUnitResp(xLen))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_irf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_||_), Mux(hits.reduce(_||_), Mux1H(hits, io_rrd_irf_bypasses.map(_.bits.data)), rdata)) } def rebusied(prs: UInt): Bool = { io_arb_rebusys.map { r => r.valid && r.bits.rebusy && r.bits.uop.pdst === prs }.reduce(_||_) } io_arb_irf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FIX && !arb_uop.bits.iw_p1_bypass_hint io_arb_irf_reqs(0).bits := arb_uop.bits.prs1 if (nReaders == 2) { io_arb_irf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FIX && !arb_uop.bits.iw_p2_bypass_hint io_arb_irf_reqs(1).bits := arb_uop.bits.prs2 } val arb_rebusied_prs1 = arb_uop.bits.lrs1_rtype === RT_FIX && rebusied(arb_uop.bits.prs1) val arb_rebusied_prs2 = arb_uop.bits.lrs2_rtype === RT_FIX && rebusied(arb_uop.bits.prs2) && (nReaders == 2).B val arb_rebusied = arb_rebusied_prs1 || arb_rebusied_prs2 val exe_rs1_data = Reg(UInt(xLen.W)) val exe_rs2_data = Reg(UInt(xLen.W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_irf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FIX && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := Mux(rrd_uop.bits.lrs1_rtype === RT_ZERO, 0.U, rs1_data) if (nReaders == 2) { val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_irf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FIX && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := Mux(rrd_uop.bits.lrs2_rtype === RT_ZERO, 0.U, rs2_data) } else { exe_rs2_data := DontCare } } trait HasImmrfReadPort { this: ExecutionUnit => val io_arb_immrf_req = IO(Decoupled(UInt(immPregSz.W))) assert(io_arb_immrf_req.ready) val io_rrd_immrf_resp = IO(Input(UInt(xLen.W))) val io_rrd_immrf_wakeup = IO(Output(Valid(new Wakeup))) io_arb_immrf_req.valid := (arb_uop.valid && !arb_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_arb_immrf_req.bits := arb_uop.bits.pimm io_rrd_immrf_wakeup.valid := (rrd_uop.valid && !rrd_uop.bits.imm_sel.isOneOf(IS_N, IS_SH) ) io_rrd_immrf_wakeup.bits.speculative_mask := false.B io_rrd_immrf_wakeup.bits.rebusy := false.B io_rrd_immrf_wakeup.bits.bypassable := false.B io_rrd_immrf_wakeup.bits.uop := rrd_uop.bits val exe_imm_data = RegNext(Mux(rrd_uop.bits.imm_sel === IS_SH, Sext(rrd_uop.bits.pimm, xLen), Sext(ImmGen(io_rrd_immrf_resp, rrd_uop.bits.imm_sel), xLen) )) } trait HasPrfReadPort { this: ExecutionUnit => val io_arb_prf_req = IO(Decoupled(UInt(log2Ceil(ftqSz).W))) assert(io_arb_prf_req.ready) val io_rrd_prf_resp = IO(Input(Bool())) io_arb_prf_req.valid := arb_uop.valid io_arb_prf_req.bits := arb_uop.bits.ppred val exe_pred_data = Reg(Bool()) exe_pred_data := io_rrd_prf_resp } trait HasBrfReadPort { this: ExecutionUnit => val io_arb_brf_req = IO(Decoupled(UInt(brTagSz.W))) assert(io_arb_brf_req.ready) val io_rrd_brf_resp = IO(Input(new BrInfoBundle)) io_arb_brf_req.valid := (arb_uop.valid && arb_uop.bits.is_br) io_arb_brf_req.bits := arb_uop.bits.br_tag exe_uop.bits.ldq_idx := io_rrd_brf_resp.ldq_idx exe_uop.bits.stq_idx := io_rrd_brf_resp.stq_idx exe_uop.bits.rxq_idx := io_rrd_brf_resp.rxq_idx } trait HasFrfReadPorts { this: ExecutionUnit => val io_arb_frf_reqs = IO(Vec(3, Decoupled(UInt(maxPregSz.W)))) val io_rrd_frf_resps = IO(Input (Vec(3, UInt((xLen+1).W)))) val io_rrd_frf_bypasses = IO(Input(Vec(fpWidth, Valid(new ExeUnitResp(fLen+1))))) def rrd_bypass_hit(prs: UInt, rdata: UInt): (Bool, UInt) = { val hits = io_rrd_frf_bypasses map { b => b.valid && prs === b.bits.uop.pdst } (hits.reduce(_||_), Mux(hits.reduce(_||_), Mux1H(hits, io_rrd_frf_bypasses.map(_.bits.data)), rdata)) } io_arb_frf_reqs(0).valid := arb_uop.valid && arb_uop.bits.lrs1_rtype === RT_FLT && !arb_uop.bits.iw_p1_bypass_hint io_arb_frf_reqs(0).bits := arb_uop.bits.prs1 io_arb_frf_reqs(1).valid := arb_uop.valid && arb_uop.bits.lrs2_rtype === RT_FLT && !arb_uop.bits.iw_p2_bypass_hint io_arb_frf_reqs(1).bits := arb_uop.bits.prs2 io_arb_frf_reqs(2).valid := arb_uop.valid && arb_uop.bits.frs3_en && !arb_uop.bits.iw_p3_bypass_hint io_arb_frf_reqs(2).bits := arb_uop.bits.prs3 val exe_rs1_data = Reg(UInt((fLen+1).W)) val exe_rs2_data = Reg(UInt((fLen+1).W)) val exe_rs3_data = Reg(UInt((fLen+1).W)) val (rs1_hit, rs1_data) = rrd_bypass_hit(rrd_uop.bits.prs1, io_rrd_frf_resps(0)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FLT && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit)) exe_rs1_data := rs1_data val (rs2_hit, rs2_data) = rrd_bypass_hit(rrd_uop.bits.prs2, io_rrd_frf_resps(1)) assert(!(rrd_uop.valid && rrd_uop.bits.lrs2_rtype === RT_FLT && rrd_uop.bits.iw_p2_bypass_hint && !rs2_hit)) exe_rs2_data := rs2_data val (rs3_hit, rs3_data) = rrd_bypass_hit(rrd_uop.bits.prs3, io_rrd_frf_resps(2)) assert(!(rrd_uop.valid && rrd_uop.bits.iw_p3_bypass_hint && !rs3_hit)) exe_rs3_data := rs3_data } trait HasFtqReadPort { this: ExecutionUnit => val io_arb_ftq_reqs = IO(Vec(2, Decoupled(UInt(log2Ceil(ftqSz).W)))) val io_rrd_ftq_resps = IO(Vec(2, Input(new FTQInfo))) // Only allow one SFB branch through multiple pipes, to avoid unnecessary predicate wakeup logic io_arb_ftq_reqs(0).valid := arb_uop.valid && (arb_uop.bits.op1_sel === OP1_PC || arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(0).bits := arb_uop.bits.ftq_idx // Only JALR checks the next-pc io_arb_ftq_reqs(1).valid := arb_uop.valid && (arb_uop.bits.br_type === B_JR || arb_uop.bits.is_sfb_br) io_arb_ftq_reqs(1).bits := WrapInc(arb_uop.bits.ftq_idx, ftqSz) val exe_ftq_data = Reg(Vec(2, new FTQInfo)) exe_ftq_data := io_rrd_ftq_resps } class MemExeUnit( val hasAGen : Boolean = false, val hasDGen : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Mem") with HasIrfReadPorts with HasImmrfReadPort { def nReaders = 1 val io_squash_iss = IO(Output(Bool())) io_squash_iss := (io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) when (io_squash_iss || arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val io_agen = if (hasAGen) { val loads_saturating = exe_uop.valid && exe_uop.bits.uses_ldq && exe_uop.bits.fu_code(FC_AGEN) val saturating_loads_counter = RegInit(0.U(5.W)) when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U } .otherwise { saturating_loads_counter := 0.U } val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W)) val load_ready = !pause_mem fu_types += ((FC_AGEN, load_ready, "AGen")) val sum = (exe_rs1_data.asSInt + exe_imm_data.asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val agen = IO(Output(Valid(new MemGen))) if (enableAgenStage) { val agen_reg = Reg(Valid(new MemGen)) agen_reg.valid := ( exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits) ) agen_reg.bits.uop := UpdateBrMask(io_brupdate, exe_uop.bits) agen_reg.bits.data := Sext(effective_address, xLen) agen := agen_reg } else { agen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN) agen.bits.uop := exe_uop.bits agen.bits.data := Sext(effective_address, xLen) } Some(agen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN))) None } val io_dgen = if (hasDGen) { fu_types += ((FC_DGEN, true.B, "DGen")) val dgen = IO(Output(Valid(new MemGen))) dgen.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN) dgen.bits.data := exe_rs1_data dgen.bits.uop := exe_uop.bits Some(dgen) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DGEN))) None } io_ready_fu_types := get_ready_fu_types() } class UniqueExeUnit( val hasCSR : Boolean = false, val hasMul : Boolean = false, val hasDiv : Boolean = false, val hasIfpu : Boolean = false, val hasRocc : Boolean = false )(implicit p: Parameters) extends ExecutionUnit("Unq") with HasIrfReadPorts with HasImmrfReadPort with MemoryOpConstants { def nReaders = 2 val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) || (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready)) when (io_squash_iss || arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := DontCare exe_int_req.ftq_info := DontCare val io_mul_resp = if (hasMul) { fu_types += ((FC_MUL, true.B, "IMul")) val imul = Module(new PipelinedMulUnit(imulLatency, xLen)) imul.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_MUL) imul.io.req.bits := exe_int_req imul.io.brupdate := io_brupdate imul.io.kill := io_kill imul.io.resp.ready := true.B val resp = IO(Output(Valid(new ExeUnitResp(xLen)))) resp := imul.io.resp Some(resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_MUL))) None } val (io_csr_resp, io_sfence) = if (hasCSR) { fu_types += ((FC_CSR, true.B, "CSR")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_CSR) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val c = IO(Output(Valid(new CSRResp))) c.valid := RegNext(alu.io.resp.valid && exe_uop.bits.csr_cmd =/= CSR.N) c.bits.uop := RegNext(alu.io.resp.bits.uop) c.bits.data := RegNext(alu.io.resp.bits.data) c.bits.addr := RegNext(exe_imm_data) val s = IO(Valid(new SFenceReq)) s.valid := RegNext(exe_uop.valid && exe_uop.bits.is_sfence) s.bits.rs1 := RegNext(exe_uop.bits.pimm(0)) s.bits.rs2 := RegNext(exe_uop.bits.pimm(1)) s.bits.addr := RegNext(exe_rs1_data) s.bits.asid := RegNext(exe_rs2_data) s.bits.hv := RegNext(exe_uop.bits.mem_cmd === M_HFENCEV) s.bits.hg := RegNext(exe_uop.bits.mem_cmd === M_HFENCEG) (Some(c), Some(s)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_CSR))) assert(!(exe_uop.valid && exe_uop.bits.mem_cmd === M_SFENCE)) (None, None) } val (io_rocc_resp, io_rocc_core) = if (hasRocc) { require(hasCSR) val rocc_core = IO(new RoCCShimCoreIO) val rocc_resp = IO(Decoupled(new ExeUnitResp(xLen))) val rocc = Module(new RoCCShim) rocc.io.req.valid := exe_uop.valid && exe_uop.bits.is_rocc rocc.io.req.bits := exe_int_req rocc.io.brupdate := io_brupdate // We should assert on this somewhere rocc.io.status := io_status rocc.io.exception := io_kill rocc_core <> rocc.io.core rocc_resp <> rocc.io.resp (Some(rocc_resp), Some(rocc_core)) } else { assert(!(exe_uop.valid && exe_uop.bits.is_rocc)) (None, None) } val (io_ifpu_resp) = if (hasIfpu) { val ifpu_ready = Wire(Bool()) fu_types += ((FC_I2F, ifpu_ready, "IFPU")) val ifpu = Module(new IntToFPUnit(latency=intToFpLatency)) ifpu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_I2F) ifpu.io.req.bits := exe_int_req ifpu.io.req.bits.uop.fp_rm := exe_uop.bits.prs2(4,2) ifpu.io.req.bits.uop.fp_typ := exe_uop.bits.prs2(1,0) ifpu.io.fcsr_rm := io_fcsr_rm ifpu.io.brupdate := io_brupdate ifpu.io.kill := io_kill // buffer up results since we share write-port on integer regfile. val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = intToFpLatency + 6)) // TODO being overly conservative queue.io.enq <> ifpu.io.resp queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert (!(queue.io.enq.valid && !queue.io.enq.ready)) ifpu_ready := RegNext(queue.io.count < 2.U) val ifpu_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) ifpu_resp <> queue.io.deq (Some(ifpu_resp)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_I2F))) (None) } val (io_div_resp) = if (hasDiv) { val div_ready = Wire(Bool()) fu_types += ((FC_DIV, div_ready, "IDiv")) val div = Module(new DivUnit(xLen)) assert(!(div.io.req.valid && !div.io.req.ready)) div.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_DIV) div.io.req.bits := exe_int_req div.io.brupdate := io_brupdate div.io.kill := io_kill div_ready := (div.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_DIV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_DIV)) ) val div_resp = IO(Decoupled(new ExeUnitResp(xLen))) div_resp <> div.io.resp Some(div_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_DIV))) (None) } io_ready_fu_types := get_ready_fu_types() } class ALUExeUnit( val id: Int )(implicit p: Parameters) extends ExecutionUnit("Alu") with HasIrfReadPorts with HasPrfReadPort with HasImmrfReadPort with HasBrfReadPort with HasFtqReadPort { def nReaders = 2 val io_fast_wakeup = IO(Output(Valid(new Wakeup))) io_fast_wakeup.valid := ( io_iss_uop.valid && (io_iss_uop.bits.dst_rtype === RT_FIX) ) io_fast_wakeup.bits.uop := io_iss_uop.bits io_fast_wakeup.bits.speculative_mask := (1 << id).U io_fast_wakeup.bits.rebusy := false.B io_fast_wakeup.bits.bypassable := true.B val io_fast_pred_wakeup = IO(Output(Valid(new Wakeup))) io_fast_pred_wakeup.valid := rrd_uop.valid && rrd_uop.bits.is_sfb_br io_fast_pred_wakeup.bits.uop := rrd_uop.bits io_fast_pred_wakeup.bits.speculative_mask := 0.U io_fast_pred_wakeup.bits.rebusy := false.B io_fast_pred_wakeup.bits.bypassable := false.B val io_squash_iss = IO(Output(Bool())) io_squash_iss := ((io_arb_irf_reqs(0).valid && !io_arb_irf_reqs(0).ready) || (io_arb_irf_reqs(1).valid && !io_arb_irf_reqs(1).ready) || (io_arb_ftq_reqs(0).valid && !io_arb_ftq_reqs(0).ready) || (io_arb_ftq_reqs(1).valid && !io_arb_ftq_reqs(1).ready)) val io_child_rebusy = IO(Output(UInt(aluWidth.W))) io_child_rebusy := 0.U when (arb_rebusied && arb_uop.valid) { io_child_rebusy := (1 << id).U } // The arbiter didn't grant us a slot. Thus, we should replay the instruction in this slot, // But next time we read, it reads from the regfile, not the bypass paths, so disable the bypass hints when (io_squash_iss || arb_rebusied) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) && !arb_rebusied arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B rrd_uop.valid := false.B } val exe_int_req = Wire(new FuncUnitReq(xLen)) exe_int_req.uop := exe_uop.bits exe_int_req.rs1_data := exe_rs1_data exe_int_req.rs2_data := exe_rs2_data exe_int_req.rs3_data := DontCare exe_int_req.imm_data := exe_imm_data exe_int_req.pred_data := exe_pred_data exe_int_req.ftq_info := exe_ftq_data fu_types += ((FC_ALU, true.B, "ALU")) val alu = Module(new ALUUnit(dataWidth = xLen)) alu.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_ALU) alu.io.req.bits := exe_int_req alu.io.resp.ready := true.B alu.io.brupdate := io_brupdate alu.io.kill := io_kill val io_alu_resp = IO(Output(Valid(new ExeUnitResp(xLen)))) io_alu_resp.valid := alu.io.resp.valid io_alu_resp.bits := alu.io.resp.bits val io_brinfo = IO(Output(Valid(new BrResolutionInfo))) io_brinfo := alu.io.brinfo io_ready_fu_types := get_ready_fu_types() } class FPExeUnit(val hasFDiv: Boolean = false, val hasFpiu: Boolean = false)(implicit p: Parameters) extends ExecutionUnit("FP") with tile.HasFPUParameters with HasFrfReadPorts { val io_squash_iss = IO(Output(Bool())) io_squash_iss := ( (io_arb_frf_reqs(0).valid && !io_arb_frf_reqs(0).ready) || (io_arb_frf_reqs(1).valid && !io_arb_frf_reqs(1).ready) || (io_arb_frf_reqs(2).valid && !io_arb_frf_reqs(2).ready) ) when (io_squash_iss) { val will_replay = arb_uop.valid && !IsKilledByBranch(io_brupdate, io_kill, arb_uop.bits) arb_uop.valid := will_replay arb_uop.bits := UpdateBrMask(io_brupdate, arb_uop.bits) arb_uop.bits.iw_p1_bypass_hint := false.B arb_uop.bits.iw_p2_bypass_hint := false.B arb_uop.bits.iw_p3_bypass_hint := false.B rrd_uop.valid := false.B } val exe_fp_req = Wire(new FuncUnitReq(xLen+1)) exe_fp_req.uop := exe_uop.bits exe_fp_req.rs1_data := exe_rs1_data exe_fp_req.rs2_data := exe_rs2_data exe_fp_req.rs3_data := exe_rs3_data exe_fp_req.pred_data := DontCare exe_fp_req.imm_data := DontCare exe_fp_req.ftq_info := DontCare val fpu = Module(new FPUUnit) fu_types += ((FC_FPU, true.B, "FPU")) fpu.io.req.valid := exe_uop.valid && ( exe_uop.bits.fu_code(FC_FPU) || (if (hasFpiu) exe_uop.bits.fu_code(FC_F2I) else false.B) ) fpu.io.req.bits := exe_fp_req fpu.io.fcsr_rm := io_fcsr_rm fpu.io.brupdate := io_brupdate fpu.io.kill := io_kill fpu.io.resp.ready := true.B val io_wakeup = IO(Output(Valid(new Wakeup))) val fastWakeupLatency = dfmaLatency - 3 // Three stages WAKE-ISS-ARB require (fastWakeupLatency >= 0) val fast_wakeups = Wire(Vec(fastWakeupLatency + 1, Valid(new Wakeup))) fast_wakeups(0).valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FPU) fast_wakeups(0).bits.uop := exe_uop.bits fast_wakeups(0).bits.speculative_mask := 0.U fast_wakeups(0).bits.rebusy := false.B fast_wakeups(0).bits.bypassable := true.B for (i <- 0 until fastWakeupLatency) { fast_wakeups(i+1) := RegNext(UpdateBrMask(io_brupdate, io_kill, fast_wakeups(i))) } io_wakeup := fast_wakeups(fastWakeupLatency) val io_fpu_resp = IO(Output(Valid(new ExeUnitResp(xLen+1)))) io_fpu_resp.valid := fpu.io.resp.valid && !fpu.io.resp.bits.uop.fu_code(FC_F2I) io_fpu_resp.bits := fpu.io.resp.bits val io_fdiv_resp = if (hasFDiv) { val fdivsqrt_ready = Wire(Bool()) fu_types += ((FC_FDV, fdivsqrt_ready, "FDiv")) val fdivsqrt = Module(new FDivSqrtUnit2) assert(!(fdivsqrt.io.req.valid && !fdivsqrt.io.req.ready)) fdivsqrt.io.req.valid := exe_uop.valid && exe_uop.bits.fu_code(FC_FDV) fdivsqrt.io.req.bits := exe_fp_req fdivsqrt.io.brupdate := io_brupdate fdivsqrt.io.kill := io_kill fdivsqrt.io.fcsr_rm := io_fcsr_rm fdivsqrt_ready := (fdivsqrt.io.req.ready && !(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV)) && !(rrd_uop.valid && rrd_uop.bits.fu_code(FC_FDV)) && !(arb_uop.valid && arb_uop.bits.fu_code(FC_FDV)) ) val fdiv_resp = IO(Decoupled(new ExeUnitResp(xLen+1))) fdiv_resp <> fdivsqrt.io.resp Some(fdiv_resp) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_FDV))) None } val (io_fpiu_resp, io_dgen) = if (hasFpiu) { val fpiu_ready = Wire(Bool()) fu_types += ((FC_F2I, fpiu_ready, "Fpiu")) val queue = Module(new BranchKillableQueue(new ExeUnitResp(xLen+1), entries = dfmaLatency + 6)) // TODO being overly conservative fpiu_ready := RegNext(queue.io.count < 2.U) queue.io.enq.valid := ( fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code(FC_F2I) && !fpu.io.resp.bits.uop.uses_stq) // STA means store data gen for floating point queue.io.enq.bits := fpu.io.resp.bits queue.io.brupdate := io_brupdate queue.io.flush := io_kill assert(!(queue.io.enq.valid && !queue.io.enq.ready)) val fpiu_resp = IO(Decoupled(new ExeUnitResp(xLen))) fpiu_resp <> queue.io.deq val dgen = IO(Valid(new MemGen)) dgen.valid := RegNext(exe_uop.valid && exe_uop.bits.uses_stq && !IsKilledByBranch(io_brupdate, io_kill, exe_uop.bits)) dgen.bits.uop := RegNext(exe_uop.bits) dgen.bits.data := RegNext(ieee(exe_rs2_data)) (Some(fpiu_resp), Some(dgen)) } else { assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_F2I))) (None, None) } io_ready_fu_types := get_ready_fu_types }
module UniqueExeUnit( // @[execution-unit.scala:330:7] input clock, // @[execution-unit.scala:330:7] input reset, // @[execution-unit.scala:330:7] input io_kill, // @[execution-unit.scala:79:19] input [11:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:80:23] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iq_type_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_0, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_4, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_5, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_6, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_7, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_8, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fu_code_9, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[execution-unit.scala:80:23] input [11:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_br_type, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sfence, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_eret, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_rocc, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_mov, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_imm_rename, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_imm_sel, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_pimm, // @[execution-unit.scala:80:23] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_op1_sel, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_op2_sel, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wen, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_toint, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_fma, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_div, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_ctrl_vec, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:80:23] input [3:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:80:23] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:80:23] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:80:23] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fcn_dw, // @[execution-unit.scala:80:23] input [4:0] io_brupdate_b2_uop_fcn_op, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_fp_rm, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_uop_fp_typ, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:80:23] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:80:23] input io_brupdate_b2_mispredict, // @[execution-unit.scala:80:23] input io_brupdate_b2_taken, // @[execution-unit.scala:80:23] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:80:23] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:80:23] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:80:23] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:80:23] input io_status_debug, // @[execution-unit.scala:81:21] input io_status_cease, // @[execution-unit.scala:81:21] input io_status_wfi, // @[execution-unit.scala:81:21] input [1:0] io_status_dprv, // @[execution-unit.scala:81:21] input io_status_dv, // @[execution-unit.scala:81:21] input [1:0] io_status_prv, // @[execution-unit.scala:81:21] input io_status_v, // @[execution-unit.scala:81:21] input io_status_sd, // @[execution-unit.scala:81:21] input io_status_mpv, // @[execution-unit.scala:81:21] input io_status_gva, // @[execution-unit.scala:81:21] input io_status_tsr, // @[execution-unit.scala:81:21] input io_status_tw, // @[execution-unit.scala:81:21] input io_status_tvm, // @[execution-unit.scala:81:21] input io_status_mxr, // @[execution-unit.scala:81:21] input io_status_sum, // @[execution-unit.scala:81:21] input io_status_mprv, // @[execution-unit.scala:81:21] input [1:0] io_status_fs, // @[execution-unit.scala:81:21] input [1:0] io_status_mpp, // @[execution-unit.scala:81:21] input io_status_spp, // @[execution-unit.scala:81:21] input io_status_mpie, // @[execution-unit.scala:81:21] input io_status_spie, // @[execution-unit.scala:81:21] input io_status_mie, // @[execution-unit.scala:81:21] input io_status_sie, // @[execution-unit.scala:81:21] output io_ready_fu_types_4, // @[execution-unit.scala:82:29] output io_ready_fu_types_8, // @[execution-unit.scala:82:29] input [2:0] io_fcsr_rm, // @[execution-unit.scala:84:22] input io_iss_uop_valid, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_inst, // @[execution-unit.scala:90:22] input [31:0] io_iss_uop_bits_debug_inst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rvc, // @[execution-unit.scala:90:22] input [39:0] io_iss_uop_bits_debug_pc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iq_type_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_0, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_4, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_5, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_6, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_7, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_8, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fu_code_9, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_issued, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p1_speculative_child, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_iw_p2_speculative_child, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p1_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p2_bypass_hint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_iw_p3_bypass_hint, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dis_col_sel, // @[execution-unit.scala:90:22] input [11:0] io_iss_uop_bits_br_mask, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_tag, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_br_type, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfb, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_fencei, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sfence, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_amo, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_eret, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_sys_pc2epc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_rocc, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_mov, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ftq_idx, // @[execution-unit.scala:90:22] input io_iss_uop_bits_edge_inst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_pc_lob, // @[execution-unit.scala:90:22] input io_iss_uop_bits_taken, // @[execution-unit.scala:90:22] input io_iss_uop_bits_imm_rename, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_imm_sel, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_pimm, // @[execution-unit.scala:90:22] input [19:0] io_iss_uop_bits_imm_packed, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_op1_sel, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_op2_sel, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ldst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wen, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren1, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren2, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_ren3, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap12, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_swap23, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagIn, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_ctrl_typeTagOut, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fromint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_toint, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fastpipe, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_fma, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_div, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_sqrt, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_wflags, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_ctrl_vec, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_rob_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_ldq_idx, // @[execution-unit.scala:90:22] input [3:0] io_iss_uop_bits_stq_idx, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_rxq_idx, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_pdst, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs1, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs2, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_prs3, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_ppred, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs1_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs2_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_prs3_busy, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ppred_busy, // @[execution-unit.scala:90:22] input [6:0] io_iss_uop_bits_stale_pdst, // @[execution-unit.scala:90:22] input io_iss_uop_bits_exception, // @[execution-unit.scala:90:22] input [63:0] io_iss_uop_bits_exc_cause, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_mem_cmd, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_mem_size, // @[execution-unit.scala:90:22] input io_iss_uop_bits_mem_signed, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_ldq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_uses_stq, // @[execution-unit.scala:90:22] input io_iss_uop_bits_is_unique, // @[execution-unit.scala:90:22] input io_iss_uop_bits_flush_on_commit, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_csr_cmd, // @[execution-unit.scala:90:22] input io_iss_uop_bits_ldst_is_rs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_ldst, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs1, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs2, // @[execution-unit.scala:90:22] input [5:0] io_iss_uop_bits_lrs3, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_dst_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs1_rtype, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_lrs2_rtype, // @[execution-unit.scala:90:22] input io_iss_uop_bits_frs3_en, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fcn_dw, // @[execution-unit.scala:90:22] input [4:0] io_iss_uop_bits_fcn_op, // @[execution-unit.scala:90:22] input io_iss_uop_bits_fp_val, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_fp_rm, // @[execution-unit.scala:90:22] input [1:0] io_iss_uop_bits_fp_typ, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_pf_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ae_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_xcpt_ma_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_debug_if, // @[execution-unit.scala:90:22] input io_iss_uop_bits_bp_xcpt_if, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_fsrc, // @[execution-unit.scala:90:22] input [2:0] io_iss_uop_bits_debug_tsrc, // @[execution-unit.scala:90:22] input io_arb_irf_reqs_0_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_0_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_0_bits, // @[execution-unit.scala:106:27] input io_arb_irf_reqs_1_ready, // @[execution-unit.scala:106:27] output io_arb_irf_reqs_1_valid, // @[execution-unit.scala:106:27] output [6:0] io_arb_irf_reqs_1_bits, // @[execution-unit.scala:106:27] input io_arb_rebusys_0_valid, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_inst, // @[execution-unit.scala:107:27] input [31:0] io_arb_rebusys_0_bits_uop_debug_inst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rvc, // @[execution-unit.scala:107:27] input [39:0] io_arb_rebusys_0_bits_uop_debug_pc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iq_type_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_0, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_4, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_5, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_6, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_7, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_8, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fu_code_9, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dis_col_sel, // @[execution-unit.scala:107:27] input [11:0] io_arb_rebusys_0_bits_uop_br_mask, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_tag, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_br_type, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfb, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_fencei, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sfence, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_amo, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_eret, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_rocc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_mov, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ftq_idx, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_edge_inst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_pc_lob, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_taken, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_imm_rename, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_imm_sel, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_pimm, // @[execution-unit.scala:107:27] input [19:0] io_arb_rebusys_0_bits_uop_imm_packed, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_op1_sel, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_op2_sel, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_rob_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_ldq_idx, // @[execution-unit.scala:107:27] input [3:0] io_arb_rebusys_0_bits_uop_stq_idx, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_rxq_idx, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_pdst, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs1, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs2, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_prs3, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_ppred, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs1_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs2_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_prs3_busy, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ppred_busy, // @[execution-unit.scala:107:27] input [6:0] io_arb_rebusys_0_bits_uop_stale_pdst, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_exception, // @[execution-unit.scala:107:27] input [63:0] io_arb_rebusys_0_bits_uop_exc_cause, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_mem_cmd, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_mem_size, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_mem_signed, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_ldq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_uses_stq, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_is_unique, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_flush_on_commit, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_csr_cmd, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_ldst, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs1, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs2, // @[execution-unit.scala:107:27] input [5:0] io_arb_rebusys_0_bits_uop_lrs3, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_dst_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_frs3_en, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fcn_dw, // @[execution-unit.scala:107:27] input [4:0] io_arb_rebusys_0_bits_uop_fcn_op, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_fp_val, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_fp_rm, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_uop_fp_typ, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_debug_if, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_fsrc, // @[execution-unit.scala:107:27] input [2:0] io_arb_rebusys_0_bits_uop_debug_tsrc, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_bypassable, // @[execution-unit.scala:107:27] input [1:0] io_arb_rebusys_0_bits_speculative_mask, // @[execution-unit.scala:107:27] input io_arb_rebusys_0_bits_rebusy, // @[execution-unit.scala:107:27] input [63:0] io_rrd_irf_resps_0, // @[execution-unit.scala:108:31] input [63:0] io_rrd_irf_resps_1, // @[execution-unit.scala:108:31] input io_rrd_irf_bypasses_0_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_0_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_0_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_0_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_0_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_0_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_0_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_0_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_0_bits_fflags_valid, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_0_bits_fflags_bits, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_1_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_1_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_1_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_1_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_1_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_1_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_1_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_1_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_1_bits_predicated, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_valid, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_inst, // @[execution-unit.scala:109:31] input [31:0] io_rrd_irf_bypasses_2_bits_uop_debug_inst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rvc, // @[execution-unit.scala:109:31] input [39:0] io_rrd_irf_bypasses_2_bits_uop_debug_pc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iq_type_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_0, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_4, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_5, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_6, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_7, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_8, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fu_code_9, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31] input [11:0] io_rrd_irf_bypasses_2_bits_uop_br_mask, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_tag, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_type, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfb, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_fencei, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sfence, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_amo, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_eret, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_rocc, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_mov, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ftq_idx, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_edge_inst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_pc_lob, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_taken, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_imm_rename, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_imm_sel, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_pimm, // @[execution-unit.scala:109:31] input [19:0] io_rrd_irf_bypasses_2_bits_uop_imm_packed, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_op1_sel, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_op2_sel, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_rob_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_ldq_idx, // @[execution-unit.scala:109:31] input [3:0] io_rrd_irf_bypasses_2_bits_uop_stq_idx, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_rxq_idx, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_pdst, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs1, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs2, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs3, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_ppred, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs1_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs2_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_prs3_busy, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ppred_busy, // @[execution-unit.scala:109:31] input [6:0] io_rrd_irf_bypasses_2_bits_uop_stale_pdst, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_exception, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_uop_exc_cause, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_mem_cmd, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_mem_size, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_mem_signed, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_ldq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_uses_stq, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_is_unique, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_csr_cmd, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_ldst, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs1, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs2, // @[execution-unit.scala:109:31] input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs3, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_dst_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_frs3_en, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fcn_dw, // @[execution-unit.scala:109:31] input [4:0] io_rrd_irf_bypasses_2_bits_uop_fcn_op, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_fp_val, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_fp_rm, // @[execution-unit.scala:109:31] input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_typ, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31] input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31] input [63:0] io_rrd_irf_bypasses_2_bits_data, // @[execution-unit.scala:109:31] input io_rrd_irf_bypasses_2_bits_predicated, // @[execution-unit.scala:109:31] output io_arb_immrf_req_valid, // @[execution-unit.scala:151:31] output [4:0] io_arb_immrf_req_bits, // @[execution-unit.scala:151:31] input [63:0] io_rrd_immrf_resp, // @[execution-unit.scala:153:31] output io_rrd_immrf_wakeup_valid, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_inst, // @[execution-unit.scala:154:31] output [31:0] io_rrd_immrf_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:154:31] output [39:0] io_rrd_immrf_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:154:31] output [11:0] io_rrd_immrf_wakeup_bits_uop_br_mask, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_tag, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_br_type, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_amo, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_eret, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_mov, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_taken, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_pimm, // @[execution-unit.scala:154:31] output [19:0] io_rrd_immrf_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:154:31] output [3:0] io_rrd_immrf_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_pdst, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs1, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs2, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_prs3, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_ppred, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:154:31] output [6:0] io_rrd_immrf_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_exception, // @[execution-unit.scala:154:31] output [63:0] io_rrd_immrf_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_mem_size, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_is_unique, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_ldst, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs1, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs2, // @[execution-unit.scala:154:31] output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs3, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:154:31] output [4:0] io_rrd_immrf_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_fp_val, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:154:31] output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:154:31] output io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:154:31] output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:154:31] output io_squash_iss, // @[execution-unit.scala:343:25] output io_mul_resp_valid, // @[execution-unit.scala:375:18] output [31:0] io_mul_resp_bits_uop_inst, // @[execution-unit.scala:375:18] output [31:0] io_mul_resp_bits_uop_debug_inst, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_rvc, // @[execution-unit.scala:375:18] output [39:0] io_mul_resp_bits_uop_debug_pc, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iq_type_0, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iq_type_1, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iq_type_2, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iq_type_3, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_0, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_1, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_2, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_3, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_4, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_5, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_6, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_7, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_8, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fu_code_9, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_issued, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:375:18] output [11:0] io_mul_resp_bits_uop_br_mask, // @[execution-unit.scala:375:18] output [3:0] io_mul_resp_bits_uop_br_tag, // @[execution-unit.scala:375:18] output [3:0] io_mul_resp_bits_uop_br_type, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_sfb, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_fence, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_fencei, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_sfence, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_amo, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_eret, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_rocc, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_mov, // @[execution-unit.scala:375:18] output [4:0] io_mul_resp_bits_uop_ftq_idx, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_edge_inst, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_pc_lob, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_taken, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_imm_rename, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_imm_sel, // @[execution-unit.scala:375:18] output [4:0] io_mul_resp_bits_uop_pimm, // @[execution-unit.scala:375:18] output [19:0] io_mul_resp_bits_uop_imm_packed, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_op1_sel, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_op2_sel, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_rob_idx, // @[execution-unit.scala:375:18] output [3:0] io_mul_resp_bits_uop_ldq_idx, // @[execution-unit.scala:375:18] output [3:0] io_mul_resp_bits_uop_stq_idx, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_rxq_idx, // @[execution-unit.scala:375:18] output [6:0] io_mul_resp_bits_uop_pdst, // @[execution-unit.scala:375:18] output [6:0] io_mul_resp_bits_uop_prs1, // @[execution-unit.scala:375:18] output [6:0] io_mul_resp_bits_uop_prs2, // @[execution-unit.scala:375:18] output [6:0] io_mul_resp_bits_uop_prs3, // @[execution-unit.scala:375:18] output [4:0] io_mul_resp_bits_uop_ppred, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_prs1_busy, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_prs2_busy, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_prs3_busy, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_ppred_busy, // @[execution-unit.scala:375:18] output [6:0] io_mul_resp_bits_uop_stale_pdst, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_exception, // @[execution-unit.scala:375:18] output [63:0] io_mul_resp_bits_uop_exc_cause, // @[execution-unit.scala:375:18] output [4:0] io_mul_resp_bits_uop_mem_cmd, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_mem_size, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_mem_signed, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_uses_ldq, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_uses_stq, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_is_unique, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_csr_cmd, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_ldst, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_lrs1, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_lrs2, // @[execution-unit.scala:375:18] output [5:0] io_mul_resp_bits_uop_lrs3, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_dst_rtype, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_frs3_en, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fcn_dw, // @[execution-unit.scala:375:18] output [4:0] io_mul_resp_bits_uop_fcn_op, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_fp_val, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_fp_rm, // @[execution-unit.scala:375:18] output [1:0] io_mul_resp_bits_uop_fp_typ, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:375:18] output io_mul_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:375:18] output [2:0] io_mul_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:375:18] output [63:0] io_mul_resp_bits_data, // @[execution-unit.scala:375:18] output io_csr_resp_valid, // @[execution-unit.scala:392:15] output [31:0] io_csr_resp_bits_uop_inst, // @[execution-unit.scala:392:15] output [31:0] io_csr_resp_bits_uop_debug_inst, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_rvc, // @[execution-unit.scala:392:15] output [39:0] io_csr_resp_bits_uop_debug_pc, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iq_type_0, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iq_type_1, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iq_type_2, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iq_type_3, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_0, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_1, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_2, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_3, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_4, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_5, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_6, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_7, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_8, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fu_code_9, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_issued, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:392:15] output [11:0] io_csr_resp_bits_uop_br_mask, // @[execution-unit.scala:392:15] output [3:0] io_csr_resp_bits_uop_br_tag, // @[execution-unit.scala:392:15] output [3:0] io_csr_resp_bits_uop_br_type, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_sfb, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_fence, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_fencei, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_sfence, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_amo, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_eret, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_rocc, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_mov, // @[execution-unit.scala:392:15] output [4:0] io_csr_resp_bits_uop_ftq_idx, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_edge_inst, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_pc_lob, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_taken, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_imm_rename, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_imm_sel, // @[execution-unit.scala:392:15] output [4:0] io_csr_resp_bits_uop_pimm, // @[execution-unit.scala:392:15] output [19:0] io_csr_resp_bits_uop_imm_packed, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_op1_sel, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_op2_sel, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_rob_idx, // @[execution-unit.scala:392:15] output [3:0] io_csr_resp_bits_uop_ldq_idx, // @[execution-unit.scala:392:15] output [3:0] io_csr_resp_bits_uop_stq_idx, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_rxq_idx, // @[execution-unit.scala:392:15] output [6:0] io_csr_resp_bits_uop_pdst, // @[execution-unit.scala:392:15] output [6:0] io_csr_resp_bits_uop_prs1, // @[execution-unit.scala:392:15] output [6:0] io_csr_resp_bits_uop_prs2, // @[execution-unit.scala:392:15] output [6:0] io_csr_resp_bits_uop_prs3, // @[execution-unit.scala:392:15] output [4:0] io_csr_resp_bits_uop_ppred, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_prs1_busy, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_prs2_busy, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_prs3_busy, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_ppred_busy, // @[execution-unit.scala:392:15] output [6:0] io_csr_resp_bits_uop_stale_pdst, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_exception, // @[execution-unit.scala:392:15] output [63:0] io_csr_resp_bits_uop_exc_cause, // @[execution-unit.scala:392:15] output [4:0] io_csr_resp_bits_uop_mem_cmd, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_mem_size, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_mem_signed, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_uses_ldq, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_uses_stq, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_is_unique, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_csr_cmd, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_ldst, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_lrs1, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_lrs2, // @[execution-unit.scala:392:15] output [5:0] io_csr_resp_bits_uop_lrs3, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_dst_rtype, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_frs3_en, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fcn_dw, // @[execution-unit.scala:392:15] output [4:0] io_csr_resp_bits_uop_fcn_op, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_fp_val, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_fp_rm, // @[execution-unit.scala:392:15] output [1:0] io_csr_resp_bits_uop_fp_typ, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:392:15] output io_csr_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:392:15] output [2:0] io_csr_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:392:15] output [63:0] io_csr_resp_bits_data, // @[execution-unit.scala:392:15] output [11:0] io_csr_resp_bits_addr, // @[execution-unit.scala:392:15] output io_sfence_valid, // @[execution-unit.scala:398:15] output io_sfence_bits_rs1, // @[execution-unit.scala:398:15] output io_sfence_bits_rs2, // @[execution-unit.scala:398:15] output [38:0] io_sfence_bits_addr, // @[execution-unit.scala:398:15] output io_sfence_bits_asid, // @[execution-unit.scala:398:15] output io_sfence_bits_hv, // @[execution-unit.scala:398:15] output io_sfence_bits_hg, // @[execution-unit.scala:398:15] input io_ifpu_resp_ready, // @[execution-unit.scala:455:23] output io_ifpu_resp_valid, // @[execution-unit.scala:455:23] output [31:0] io_ifpu_resp_bits_uop_inst, // @[execution-unit.scala:455:23] output [31:0] io_ifpu_resp_bits_uop_debug_inst, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_rvc, // @[execution-unit.scala:455:23] output [39:0] io_ifpu_resp_bits_uop_debug_pc, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iq_type_0, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iq_type_1, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iq_type_2, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iq_type_3, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_0, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_1, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_2, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_3, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_4, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_5, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_6, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_7, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_8, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fu_code_9, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_issued, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:455:23] output [11:0] io_ifpu_resp_bits_uop_br_mask, // @[execution-unit.scala:455:23] output [3:0] io_ifpu_resp_bits_uop_br_tag, // @[execution-unit.scala:455:23] output [3:0] io_ifpu_resp_bits_uop_br_type, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_sfb, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_fence, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_fencei, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_sfence, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_amo, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_eret, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_rocc, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_mov, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_uop_ftq_idx, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_edge_inst, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_pc_lob, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_taken, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_imm_rename, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_imm_sel, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_uop_pimm, // @[execution-unit.scala:455:23] output [19:0] io_ifpu_resp_bits_uop_imm_packed, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_op1_sel, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_op2_sel, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_rob_idx, // @[execution-unit.scala:455:23] output [3:0] io_ifpu_resp_bits_uop_ldq_idx, // @[execution-unit.scala:455:23] output [3:0] io_ifpu_resp_bits_uop_stq_idx, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_rxq_idx, // @[execution-unit.scala:455:23] output [6:0] io_ifpu_resp_bits_uop_pdst, // @[execution-unit.scala:455:23] output [6:0] io_ifpu_resp_bits_uop_prs1, // @[execution-unit.scala:455:23] output [6:0] io_ifpu_resp_bits_uop_prs2, // @[execution-unit.scala:455:23] output [6:0] io_ifpu_resp_bits_uop_prs3, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_uop_ppred, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_prs1_busy, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_prs2_busy, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_prs3_busy, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_ppred_busy, // @[execution-unit.scala:455:23] output [6:0] io_ifpu_resp_bits_uop_stale_pdst, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_exception, // @[execution-unit.scala:455:23] output [63:0] io_ifpu_resp_bits_uop_exc_cause, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_uop_mem_cmd, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_mem_size, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_mem_signed, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_uses_ldq, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_uses_stq, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_is_unique, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_csr_cmd, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_ldst, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_lrs1, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_lrs2, // @[execution-unit.scala:455:23] output [5:0] io_ifpu_resp_bits_uop_lrs3, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_dst_rtype, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_frs3_en, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fcn_dw, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_uop_fcn_op, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_fp_val, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_fp_rm, // @[execution-unit.scala:455:23] output [1:0] io_ifpu_resp_bits_uop_fp_typ, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:455:23] output [2:0] io_ifpu_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:455:23] output [64:0] io_ifpu_resp_bits_data, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_predicated, // @[execution-unit.scala:455:23] output io_ifpu_resp_bits_fflags_valid, // @[execution-unit.scala:455:23] output [4:0] io_ifpu_resp_bits_fflags_bits, // @[execution-unit.scala:455:23] input io_div_resp_ready, // @[execution-unit.scala:480:22] output io_div_resp_valid, // @[execution-unit.scala:480:22] output [31:0] io_div_resp_bits_uop_inst, // @[execution-unit.scala:480:22] output [31:0] io_div_resp_bits_uop_debug_inst, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_rvc, // @[execution-unit.scala:480:22] output [39:0] io_div_resp_bits_uop_debug_pc, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iq_type_0, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iq_type_1, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iq_type_2, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iq_type_3, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_0, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_1, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_2, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_3, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_4, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_5, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_6, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_7, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_8, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fu_code_9, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_issued, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_dis_col_sel, // @[execution-unit.scala:480:22] output [11:0] io_div_resp_bits_uop_br_mask, // @[execution-unit.scala:480:22] output [3:0] io_div_resp_bits_uop_br_tag, // @[execution-unit.scala:480:22] output [3:0] io_div_resp_bits_uop_br_type, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_sfb, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_fence, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_fencei, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_sfence, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_amo, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_eret, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_rocc, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_mov, // @[execution-unit.scala:480:22] output [4:0] io_div_resp_bits_uop_ftq_idx, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_edge_inst, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_pc_lob, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_taken, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_imm_rename, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_imm_sel, // @[execution-unit.scala:480:22] output [4:0] io_div_resp_bits_uop_pimm, // @[execution-unit.scala:480:22] output [19:0] io_div_resp_bits_uop_imm_packed, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_op1_sel, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_op2_sel, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_div, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_rob_idx, // @[execution-unit.scala:480:22] output [3:0] io_div_resp_bits_uop_ldq_idx, // @[execution-unit.scala:480:22] output [3:0] io_div_resp_bits_uop_stq_idx, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_rxq_idx, // @[execution-unit.scala:480:22] output [6:0] io_div_resp_bits_uop_pdst, // @[execution-unit.scala:480:22] output [6:0] io_div_resp_bits_uop_prs1, // @[execution-unit.scala:480:22] output [6:0] io_div_resp_bits_uop_prs2, // @[execution-unit.scala:480:22] output [6:0] io_div_resp_bits_uop_prs3, // @[execution-unit.scala:480:22] output [4:0] io_div_resp_bits_uop_ppred, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_prs1_busy, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_prs2_busy, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_prs3_busy, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_ppred_busy, // @[execution-unit.scala:480:22] output [6:0] io_div_resp_bits_uop_stale_pdst, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_exception, // @[execution-unit.scala:480:22] output [63:0] io_div_resp_bits_uop_exc_cause, // @[execution-unit.scala:480:22] output [4:0] io_div_resp_bits_uop_mem_cmd, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_mem_size, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_mem_signed, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_uses_ldq, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_uses_stq, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_is_unique, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_flush_on_commit, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_csr_cmd, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_ldst, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_lrs1, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_lrs2, // @[execution-unit.scala:480:22] output [5:0] io_div_resp_bits_uop_lrs3, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_dst_rtype, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_lrs1_rtype, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_lrs2_rtype, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_frs3_en, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fcn_dw, // @[execution-unit.scala:480:22] output [4:0] io_div_resp_bits_uop_fcn_op, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_fp_val, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_fp_rm, // @[execution-unit.scala:480:22] output [1:0] io_div_resp_bits_uop_fp_typ, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_bp_debug_if, // @[execution-unit.scala:480:22] output io_div_resp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_debug_fsrc, // @[execution-unit.scala:480:22] output [2:0] io_div_resp_bits_uop_debug_tsrc, // @[execution-unit.scala:480:22] output [63:0] io_div_resp_bits_data // @[execution-unit.scala:480:22] ); reg s_bits_hg_REG; // @[execution-unit.scala:405:25] reg s_bits_hv_REG; // @[execution-unit.scala:404:25] reg s_bits_rs2_REG; // @[execution-unit.scala:401:26] reg s_bits_rs1_REG; // @[execution-unit.scala:400:26] reg s_valid_REG; // @[execution-unit.scala:399:26] reg [63:0] c_bits_data_REG; // @[execution-unit.scala:395:27] reg [2:0] c_bits_uop_REG_debug_tsrc; // @[execution-unit.scala:394:27] reg [2:0] c_bits_uop_REG_debug_fsrc; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_bp_xcpt_if; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_bp_debug_if; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_xcpt_ma_if; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_xcpt_ae_if; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_xcpt_pf_if; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_fp_typ; // @[execution-unit.scala:394:27] reg [2:0] c_bits_uop_REG_fp_rm; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_val; // @[execution-unit.scala:394:27] reg [4:0] c_bits_uop_REG_fcn_op; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fcn_dw; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_frs3_en; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_lrs2_rtype; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_lrs1_rtype; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_dst_rtype; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_lrs3; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_lrs2; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_lrs1; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_ldst; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_ldst_is_rs1; // @[execution-unit.scala:394:27] reg [2:0] c_bits_uop_REG_csr_cmd; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_flush_on_commit; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_unique; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_uses_stq; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_uses_ldq; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_mem_signed; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_mem_size; // @[execution-unit.scala:394:27] reg [4:0] c_bits_uop_REG_mem_cmd; // @[execution-unit.scala:394:27] reg [63:0] c_bits_uop_REG_exc_cause; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_exception; // @[execution-unit.scala:394:27] reg [6:0] c_bits_uop_REG_stale_pdst; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_ppred_busy; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_prs3_busy; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_prs2_busy; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_prs1_busy; // @[execution-unit.scala:394:27] reg [4:0] c_bits_uop_REG_ppred; // @[execution-unit.scala:394:27] reg [6:0] c_bits_uop_REG_prs3; // @[execution-unit.scala:394:27] reg [6:0] c_bits_uop_REG_prs2; // @[execution-unit.scala:394:27] reg [6:0] c_bits_uop_REG_prs1; // @[execution-unit.scala:394:27] reg [6:0] c_bits_uop_REG_pdst; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_rxq_idx; // @[execution-unit.scala:394:27] reg [3:0] c_bits_uop_REG_stq_idx; // @[execution-unit.scala:394:27] reg [3:0] c_bits_uop_REG_ldq_idx; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_rob_idx; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_vec; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_wflags; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_sqrt; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_div; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_fma; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_fastpipe; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_toint; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_fromint; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_fp_ctrl_typeTagOut; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_fp_ctrl_typeTagIn; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_swap23; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_swap12; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_ren3; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_ren2; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_ren1; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_wen; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fp_ctrl_ldst; // @[execution-unit.scala:394:27] reg [2:0] c_bits_uop_REG_op2_sel; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_op1_sel; // @[execution-unit.scala:394:27] reg [19:0] c_bits_uop_REG_imm_packed; // @[execution-unit.scala:394:27] reg [4:0] c_bits_uop_REG_pimm; // @[execution-unit.scala:394:27] reg [2:0] c_bits_uop_REG_imm_sel; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_imm_rename; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_taken; // @[execution-unit.scala:394:27] reg [5:0] c_bits_uop_REG_pc_lob; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_edge_inst; // @[execution-unit.scala:394:27] reg [4:0] c_bits_uop_REG_ftq_idx; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_mov; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_rocc; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_sys_pc2epc; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_eret; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_amo; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_sfence; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_fencei; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_fence; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_sfb; // @[execution-unit.scala:394:27] reg [3:0] c_bits_uop_REG_br_type; // @[execution-unit.scala:394:27] reg [3:0] c_bits_uop_REG_br_tag; // @[execution-unit.scala:394:27] reg [11:0] c_bits_uop_REG_br_mask; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_dis_col_sel; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_p3_bypass_hint; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_p2_bypass_hint; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_p1_bypass_hint; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_iw_p2_speculative_child; // @[execution-unit.scala:394:27] reg [1:0] c_bits_uop_REG_iw_p1_speculative_child; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_issued_partial_dgen; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_issued_partial_agen; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iw_issued; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_9; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_8; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_7; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_6; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_5; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_4; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_3; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_2; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_1; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_fu_code_0; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iq_type_3; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iq_type_2; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iq_type_1; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_iq_type_0; // @[execution-unit.scala:394:27] reg [39:0] c_bits_uop_REG_debug_pc; // @[execution-unit.scala:394:27] reg c_bits_uop_REG_is_rvc; // @[execution-unit.scala:394:27] reg [31:0] c_bits_uop_REG_debug_inst; // @[execution-unit.scala:394:27] reg [31:0] c_bits_uop_REG_inst; // @[execution-unit.scala:394:27] reg c_valid_REG; // @[execution-unit.scala:393:27] reg [2:0] rrd_uop_bits_debug_tsrc; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_debug_fsrc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_xcpt_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_bp_debug_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ma_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_ae_if; // @[execution-unit.scala:95:20] reg rrd_uop_bits_xcpt_pf_if; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_typ; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_fp_rm; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_val; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_fcn_op; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fcn_dw; // @[execution-unit.scala:95:20] reg rrd_uop_bits_frs3_en; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dst_rtype; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs3; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs2; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_lrs1; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_ldst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ldst_is_rs1; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_csr_cmd; // @[execution-unit.scala:95:20] reg rrd_uop_bits_flush_on_commit; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_unique; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_stq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_uses_ldq; // @[execution-unit.scala:95:20] reg rrd_uop_bits_mem_signed; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_mem_size; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_mem_cmd; // @[execution-unit.scala:95:20] reg [63:0] rrd_uop_bits_exc_cause; // @[execution-unit.scala:95:20] reg rrd_uop_bits_exception; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_stale_pdst; // @[execution-unit.scala:95:20] reg rrd_uop_bits_ppred_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs3_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs2_busy; // @[execution-unit.scala:95:20] reg rrd_uop_bits_prs1_busy; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ppred; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs3; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs2; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_prs1; // @[execution-unit.scala:95:20] reg [6:0] rrd_uop_bits_pdst; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_rxq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_stq_idx; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_ldq_idx; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_rob_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_div; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_op2_sel; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_op1_sel; // @[execution-unit.scala:95:20] reg [19:0] rrd_uop_bits_imm_packed; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_pimm; // @[execution-unit.scala:95:20] reg [2:0] rrd_uop_bits_imm_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_imm_rename; // @[execution-unit.scala:95:20] reg rrd_uop_bits_taken; // @[execution-unit.scala:95:20] reg [5:0] rrd_uop_bits_pc_lob; // @[execution-unit.scala:95:20] reg rrd_uop_bits_edge_inst; // @[execution-unit.scala:95:20] reg [4:0] rrd_uop_bits_ftq_idx; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_mov; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rocc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_eret; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_amo; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fencei; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_fence; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_sfb; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_type; // @[execution-unit.scala:95:20] reg [3:0] rrd_uop_bits_br_tag; // @[execution-unit.scala:95:20] reg [11:0] rrd_uop_bits_br_mask; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_dis_col_sel; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:95:20] reg [1:0] rrd_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iw_issued; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_9; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_8; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_7; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_6; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_5; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_4; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_fu_code_0; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_3; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_2; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_1; // @[execution-unit.scala:95:20] reg rrd_uop_bits_iq_type_0; // @[execution-unit.scala:95:20] reg [39:0] rrd_uop_bits_debug_pc; // @[execution-unit.scala:95:20] reg rrd_uop_bits_is_rvc; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_debug_inst; // @[execution-unit.scala:95:20] reg [31:0] rrd_uop_bits_inst; // @[execution-unit.scala:95:20] wire _io_div_resp_div_io_req_ready; // @[execution-unit.scala:467:21] wire _io_ifpu_resp_queue_io_enq_ready; // @[execution-unit.scala:447:23] wire [2:0] _io_ifpu_resp_queue_io_count; // @[execution-unit.scala:447:23] wire _io_ifpu_resp_ifpu_io_resp_valid; // @[execution-unit.scala:437:22] wire [31:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_inst; // @[execution-unit.scala:437:22] wire [31:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:437:22] wire [39:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iq_type_0; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iq_type_1; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iq_type_2; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iq_type_3; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_0; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_1; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_2; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_3; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_4; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_5; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_6; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_7; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_8; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fu_code_9; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_issued; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_dis_col_sel; // @[execution-unit.scala:437:22] wire [11:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_br_mask; // @[execution-unit.scala:437:22] wire [3:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_br_tag; // @[execution-unit.scala:437:22] wire [3:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_br_type; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_fence; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_sfence; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_amo; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_eret; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_rocc; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_mov; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_taken; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_imm_rename; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_imm_sel; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_pimm; // @[execution-unit.scala:437:22] wire [19:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_op1_sel; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_op2_sel; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_div; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:437:22] wire [3:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:437:22] wire [3:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:437:22] wire [6:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_pdst; // @[execution-unit.scala:437:22] wire [6:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_prs1; // @[execution-unit.scala:437:22] wire [6:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_prs2; // @[execution-unit.scala:437:22] wire [6:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_prs3; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_ppred; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:437:22] wire [6:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_exception; // @[execution-unit.scala:437:22] wire [63:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_mem_size; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_is_unique; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_csr_cmd; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_ldst; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_lrs1; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_lrs2; // @[execution-unit.scala:437:22] wire [5:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_lrs3; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fcn_dw; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_fcn_op; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_val; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_rm; // @[execution-unit.scala:437:22] wire [1:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_fp_typ; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:437:22] wire [2:0] _io_ifpu_resp_ifpu_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:437:22] wire [64:0] _io_ifpu_resp_ifpu_io_resp_bits_data; // @[execution-unit.scala:437:22] wire _io_ifpu_resp_ifpu_io_resp_bits_fflags_valid; // @[execution-unit.scala:437:22] wire [4:0] _io_ifpu_resp_ifpu_io_resp_bits_fflags_bits; // @[execution-unit.scala:437:22] wire _alu_io_resp_valid; // @[execution-unit.scala:385:21] wire [31:0] _alu_io_resp_bits_uop_inst; // @[execution-unit.scala:385:21] wire [31:0] _alu_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:385:21] wire [39:0] _alu_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iq_type_0; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iq_type_1; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iq_type_2; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iq_type_3; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_0; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_1; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_2; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_3; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_4; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_5; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_6; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_7; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_8; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fu_code_9; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_issued; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_dis_col_sel; // @[execution-unit.scala:385:21] wire [11:0] _alu_io_resp_bits_uop_br_mask; // @[execution-unit.scala:385:21] wire [3:0] _alu_io_resp_bits_uop_br_tag; // @[execution-unit.scala:385:21] wire [3:0] _alu_io_resp_bits_uop_br_type; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_fence; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_sfence; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_amo; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_eret; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_rocc; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_mov; // @[execution-unit.scala:385:21] wire [4:0] _alu_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_taken; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_imm_rename; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_imm_sel; // @[execution-unit.scala:385:21] wire [4:0] _alu_io_resp_bits_uop_pimm; // @[execution-unit.scala:385:21] wire [19:0] _alu_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_op1_sel; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_op2_sel; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_div; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:385:21] wire [3:0] _alu_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:385:21] wire [3:0] _alu_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:385:21] wire [6:0] _alu_io_resp_bits_uop_pdst; // @[execution-unit.scala:385:21] wire [6:0] _alu_io_resp_bits_uop_prs1; // @[execution-unit.scala:385:21] wire [6:0] _alu_io_resp_bits_uop_prs2; // @[execution-unit.scala:385:21] wire [6:0] _alu_io_resp_bits_uop_prs3; // @[execution-unit.scala:385:21] wire [4:0] _alu_io_resp_bits_uop_ppred; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:385:21] wire [6:0] _alu_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_exception; // @[execution-unit.scala:385:21] wire [63:0] _alu_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:385:21] wire [4:0] _alu_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_mem_size; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_is_unique; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_csr_cmd; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_ldst; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_lrs1; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_lrs2; // @[execution-unit.scala:385:21] wire [5:0] _alu_io_resp_bits_uop_lrs3; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fcn_dw; // @[execution-unit.scala:385:21] wire [4:0] _alu_io_resp_bits_uop_fcn_op; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_fp_val; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_fp_rm; // @[execution-unit.scala:385:21] wire [1:0] _alu_io_resp_bits_uop_fp_typ; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:385:21] wire _alu_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:385:21] wire [2:0] _alu_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:385:21] wire [63:0] _alu_io_resp_bits_data; // @[execution-unit.scala:385:21] wire _io_mul_resp_imul_io_resp_valid; // @[execution-unit.scala:368:22] wire [31:0] _io_mul_resp_imul_io_resp_bits_uop_inst; // @[execution-unit.scala:368:22] wire [31:0] _io_mul_resp_imul_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:368:22] wire [39:0] _io_mul_resp_imul_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iq_type_0; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iq_type_1; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iq_type_2; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iq_type_3; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_0; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_1; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_2; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_3; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_4; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_5; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_6; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_7; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_8; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fu_code_9; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_issued; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_issued_partial_agen; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_issued_partial_dgen; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_iw_p1_speculative_child; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_iw_p2_speculative_child; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_p1_bypass_hint; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_p2_bypass_hint; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_iw_p3_bypass_hint; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_dis_col_sel; // @[execution-unit.scala:368:22] wire [11:0] _io_mul_resp_imul_io_resp_bits_uop_br_mask; // @[execution-unit.scala:368:22] wire [3:0] _io_mul_resp_imul_io_resp_bits_uop_br_tag; // @[execution-unit.scala:368:22] wire [3:0] _io_mul_resp_imul_io_resp_bits_uop_br_type; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_fence; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_sfence; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_amo; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_eret; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_rocc; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_mov; // @[execution-unit.scala:368:22] wire [4:0] _io_mul_resp_imul_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_taken; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_imm_rename; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_imm_sel; // @[execution-unit.scala:368:22] wire [4:0] _io_mul_resp_imul_io_resp_bits_uop_pimm; // @[execution-unit.scala:368:22] wire [19:0] _io_mul_resp_imul_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_op1_sel; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_op2_sel; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_ldst; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_wen; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_ren1; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_ren2; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_ren3; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_swap12; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_swap23; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_fromint; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_toint; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_fastpipe; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_fma; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_div; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_sqrt; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_wflags; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_ctrl_vec; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:368:22] wire [3:0] _io_mul_resp_imul_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:368:22] wire [3:0] _io_mul_resp_imul_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:368:22] wire [6:0] _io_mul_resp_imul_io_resp_bits_uop_pdst; // @[execution-unit.scala:368:22] wire [6:0] _io_mul_resp_imul_io_resp_bits_uop_prs1; // @[execution-unit.scala:368:22] wire [6:0] _io_mul_resp_imul_io_resp_bits_uop_prs2; // @[execution-unit.scala:368:22] wire [6:0] _io_mul_resp_imul_io_resp_bits_uop_prs3; // @[execution-unit.scala:368:22] wire [4:0] _io_mul_resp_imul_io_resp_bits_uop_ppred; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:368:22] wire [6:0] _io_mul_resp_imul_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_exception; // @[execution-unit.scala:368:22] wire [63:0] _io_mul_resp_imul_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:368:22] wire [4:0] _io_mul_resp_imul_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_mem_size; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_is_unique; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_csr_cmd; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_ldst; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_lrs1; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_lrs2; // @[execution-unit.scala:368:22] wire [5:0] _io_mul_resp_imul_io_resp_bits_uop_lrs3; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fcn_dw; // @[execution-unit.scala:368:22] wire [4:0] _io_mul_resp_imul_io_resp_bits_uop_fcn_op; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_fp_val; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_fp_rm; // @[execution-unit.scala:368:22] wire [1:0] _io_mul_resp_imul_io_resp_bits_uop_fp_typ; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:368:22] wire _io_mul_resp_imul_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:368:22] wire [2:0] _io_mul_resp_imul_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:368:22] wire [63:0] _io_mul_resp_imul_io_resp_bits_data; // @[execution-unit.scala:368:22] wire io_arb_irf_reqs_0_ready_0 = io_arb_irf_reqs_0_ready; // @[execution-unit.scala:330:7] wire io_arb_irf_reqs_1_ready_0 = io_arb_irf_reqs_1_ready; // @[execution-unit.scala:330:7] wire io_ifpu_resp_ready_0 = io_ifpu_resp_ready; // @[execution-unit.scala:330:7] wire io_div_resp_ready_0 = io_div_resp_ready; // @[execution-unit.scala:330:7] wire [31:0] arb_uop_bits_out_inst = io_iss_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_debug_inst = io_iss_uop_bits_debug_inst; // @[util.scala:104:23] wire arb_uop_bits_out_is_rvc = io_iss_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_debug_pc = io_iss_uop_bits_debug_pc; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_0 = io_iss_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_1 = io_iss_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_2 = io_iss_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_iq_type_3 = io_iss_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_0 = io_iss_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_1 = io_iss_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_2 = io_iss_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_3 = io_iss_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_4 = io_iss_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_5 = io_iss_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_6 = io_iss_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_7 = io_iss_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_8 = io_iss_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_fu_code_9 = io_iss_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued = io_iss_uop_bits_iw_issued; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p1_speculative_child = io_iss_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_iw_p2_speculative_child = io_iss_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p1_bypass_hint = io_iss_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p2_bypass_hint = io_iss_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_iw_p3_bypass_hint = io_iss_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dis_col_sel = io_iss_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_tag = io_iss_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_br_type = io_iss_uop_bits_br_type; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfb = io_iss_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_is_fence = io_iss_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_is_fencei = io_iss_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_is_sfence = io_iss_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_is_amo = io_iss_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_is_eret = io_iss_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_is_sys_pc2epc = io_iss_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_is_rocc = io_iss_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_is_mov = io_iss_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ftq_idx = io_iss_uop_bits_ftq_idx; // @[util.scala:104:23] wire arb_uop_bits_out_edge_inst = io_iss_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_pc_lob = io_iss_uop_bits_pc_lob; // @[util.scala:104:23] wire arb_uop_bits_out_taken = io_iss_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_imm_rename = io_iss_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_imm_sel = io_iss_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_pimm = io_iss_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_imm_packed = io_iss_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_op1_sel = io_iss_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_op2_sel = io_iss_uop_bits_op2_sel; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ldst = io_iss_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wen = io_iss_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren1 = io_iss_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren2 = io_iss_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_ren3 = io_iss_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap12 = io_iss_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_swap23 = io_iss_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagIn = io_iss_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagOut = io_iss_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fromint = io_iss_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_toint = io_iss_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fastpipe = io_iss_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_fma = io_iss_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_div = io_iss_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_sqrt = io_iss_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_wflags = io_iss_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_fp_ctrl_vec = io_iss_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_rob_idx = io_iss_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_ldq_idx = io_iss_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_stq_idx = io_iss_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_rxq_idx = io_iss_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_pdst = io_iss_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs1 = io_iss_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs2 = io_iss_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_prs3 = io_iss_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_ppred = io_iss_uop_bits_ppred; // @[util.scala:104:23] wire arb_uop_bits_out_prs1_busy = io_iss_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs2_busy = io_iss_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_prs3_busy = io_iss_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_ppred_busy = io_iss_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_stale_pdst = io_iss_uop_bits_stale_pdst; // @[util.scala:104:23] wire arb_uop_bits_out_exception = io_iss_uop_bits_exception; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_exc_cause = io_iss_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_mem_cmd = io_iss_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_mem_size = io_iss_uop_bits_mem_size; // @[util.scala:104:23] wire arb_uop_bits_out_mem_signed = io_iss_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_uses_ldq = io_iss_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_uses_stq = io_iss_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_is_unique = io_iss_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_flush_on_commit = io_iss_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_csr_cmd = io_iss_uop_bits_csr_cmd; // @[util.scala:104:23] wire arb_uop_bits_out_ldst_is_rs1 = io_iss_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_ldst = io_iss_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs1 = io_iss_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs2 = io_iss_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_lrs3 = io_iss_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_dst_rtype = io_iss_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs1_rtype = io_iss_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_lrs2_rtype = io_iss_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire arb_uop_bits_out_frs3_en = io_iss_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_fcn_dw = io_iss_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_fcn_op = io_iss_uop_bits_fcn_op; // @[util.scala:104:23] wire arb_uop_bits_out_fp_val = io_iss_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_fp_rm = io_iss_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_fp_typ = io_iss_uop_bits_fp_typ; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_pf_if = io_iss_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ae_if = io_iss_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_xcpt_ma_if = io_iss_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_debug_if = io_iss_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_bp_xcpt_if = io_iss_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_fsrc = io_iss_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_debug_tsrc = io_iss_uop_bits_debug_tsrc; // @[util.scala:104:23] wire _io_ifpu_resp_T_3 = reset; // @[execution-unit.scala:452:12] wire _io_div_resp_T_3 = reset; // @[execution-unit.scala:468:11] wire io_div_resp_bits_predicated = 1'h0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:330:7] wire arb_uop_bits_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire arb_uop_bits_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire exe_int_req_ftq_info_0_valid = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_is_call = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_entry_start_bank = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_valid = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_is_call = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_entry_start_bank = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[execution-unit.scala:357:25] wire exe_int_req_pred_data = 1'h0; // @[execution-unit.scala:357:25] wire _r_WIRE_0 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_1 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_2 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_3 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_4 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_5 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_6 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_7 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_8 = 1'h0; // @[execution-unit.scala:74:29] wire _r_WIRE_9 = 1'h0; // @[execution-unit.scala:74:29] wire r_0 = 1'h0; // @[execution-unit.scala:74:21] wire r_1 = 1'h0; // @[execution-unit.scala:74:21] wire r_2 = 1'h0; // @[execution-unit.scala:74:21] wire r_6 = 1'h0; // @[execution-unit.scala:74:21] wire r_7 = 1'h0; // @[execution-unit.scala:74:21] wire r_9 = 1'h0; // @[execution-unit.scala:74:21] wire [1:0] exe_int_req_ftq_info_0_entry_cfi_idx_bits = 2'h0; // @[execution-unit.scala:357:25] wire [1:0] exe_int_req_ftq_info_1_entry_cfi_idx_bits = 2'h0; // @[execution-unit.scala:357:25] wire io_arb_immrf_req_ready = 1'h1; // @[execution-unit.scala:330:7] wire r_3 = 1'h1; // @[execution-unit.scala:74:21] wire r_5 = 1'h1; // @[execution-unit.scala:74:21] wire [4:0] io_div_resp_bits_fflags_bits = 5'h0; // @[execution-unit.scala:330:7] wire [4:0] exe_int_req_ftq_info_0_entry_ras_idx = 5'h0; // @[execution-unit.scala:357:25] wire [4:0] exe_int_req_ftq_info_0_ghist_ras_idx = 5'h0; // @[execution-unit.scala:357:25] wire [4:0] exe_int_req_ftq_info_1_entry_ras_idx = 5'h0; // @[execution-unit.scala:357:25] wire [4:0] exe_int_req_ftq_info_1_ghist_ras_idx = 5'h0; // @[execution-unit.scala:357:25] wire [39:0] exe_int_req_ftq_info_0_entry_ras_top = 40'h0; // @[execution-unit.scala:357:25] wire [39:0] exe_int_req_ftq_info_0_pc = 40'h0; // @[execution-unit.scala:357:25] wire [39:0] exe_int_req_ftq_info_1_entry_ras_top = 40'h0; // @[execution-unit.scala:357:25] wire [39:0] exe_int_req_ftq_info_1_pc = 40'h0; // @[execution-unit.scala:357:25] wire [63:0] exe_int_req_rs3_data = 64'h0; // @[execution-unit.scala:357:25] wire [63:0] exe_int_req_ftq_info_0_ghist_old_history = 64'h0; // @[execution-unit.scala:357:25] wire [63:0] exe_int_req_ftq_info_1_ghist_old_history = 64'h0; // @[execution-unit.scala:357:25] wire [3:0] exe_int_req_ftq_info_0_entry_br_mask = 4'h0; // @[execution-unit.scala:357:25] wire [3:0] exe_int_req_ftq_info_1_entry_br_mask = 4'h0; // @[execution-unit.scala:357:25] wire [2:0] exe_int_req_ftq_info_0_entry_cfi_type = 3'h0; // @[execution-unit.scala:357:25] wire [2:0] exe_int_req_ftq_info_1_entry_cfi_type = 3'h0; // @[execution-unit.scala:357:25] wire _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83] wire _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85] wire _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44] wire r_4; // @[execution-unit.scala:74:21] wire r_8; // @[execution-unit.scala:74:21] wire io_arb_irf_reqs_0_valid_0; // @[execution-unit.scala:330:7] wire [6:0] io_arb_irf_reqs_0_bits_0; // @[execution-unit.scala:330:7] wire io_arb_irf_reqs_1_valid_0; // @[execution-unit.scala:330:7] wire [6:0] io_arb_irf_reqs_1_bits_0; // @[execution-unit.scala:330:7] wire io_arb_immrf_req_valid_0; // @[execution-unit.scala:330:7] wire [4:0] io_arb_immrf_req_bits_0; // @[execution-unit.scala:330:7] wire _io_rrd_immrf_wakeup_valid_T_4; // @[execution-unit.scala:162:47] wire _io_squash_iss_T_4; // @[execution-unit.scala:344:77] wire io_ifpu_resp_bits_uop_iq_type_0_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iq_type_1_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iq_type_2_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iq_type_3_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_0_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_1_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_2_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_3_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_4_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_5_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_6_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_7_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_8_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fu_code_9_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_ldst_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_wen_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_ren1_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_ren2_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_ren3_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_swap12_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_swap23_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_fromint_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_toint_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_fastpipe_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_fma_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_div_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_sqrt_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_wflags_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_ctrl_vec_0; // @[execution-unit.scala:330:7] wire [31:0] io_ifpu_resp_bits_uop_inst_0; // @[execution-unit.scala:330:7] wire [31:0] io_ifpu_resp_bits_uop_debug_inst_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_rvc_0; // @[execution-unit.scala:330:7] wire [39:0] io_ifpu_resp_bits_uop_debug_pc_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_issued_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_issued_partial_agen_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_issued_partial_dgen_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_iw_p1_speculative_child_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_iw_p2_speculative_child_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_p1_bypass_hint_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_p2_bypass_hint_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_iw_p3_bypass_hint_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_dis_col_sel_0; // @[execution-unit.scala:330:7] wire [11:0] io_ifpu_resp_bits_uop_br_mask_0; // @[execution-unit.scala:330:7] wire [3:0] io_ifpu_resp_bits_uop_br_tag_0; // @[execution-unit.scala:330:7] wire [3:0] io_ifpu_resp_bits_uop_br_type_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_sfb_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_fence_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_fencei_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_sfence_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_amo_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_eret_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_rocc_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_mov_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_uop_ftq_idx_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_edge_inst_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_pc_lob_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_taken_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_imm_rename_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_imm_sel_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_uop_pimm_0; // @[execution-unit.scala:330:7] wire [19:0] io_ifpu_resp_bits_uop_imm_packed_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_op1_sel_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_op2_sel_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_rob_idx_0; // @[execution-unit.scala:330:7] wire [3:0] io_ifpu_resp_bits_uop_ldq_idx_0; // @[execution-unit.scala:330:7] wire [3:0] io_ifpu_resp_bits_uop_stq_idx_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_rxq_idx_0; // @[execution-unit.scala:330:7] wire [6:0] io_ifpu_resp_bits_uop_pdst_0; // @[execution-unit.scala:330:7] wire [6:0] io_ifpu_resp_bits_uop_prs1_0; // @[execution-unit.scala:330:7] wire [6:0] io_ifpu_resp_bits_uop_prs2_0; // @[execution-unit.scala:330:7] wire [6:0] io_ifpu_resp_bits_uop_prs3_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_uop_ppred_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_prs1_busy_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_prs2_busy_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_prs3_busy_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_ppred_busy_0; // @[execution-unit.scala:330:7] wire [6:0] io_ifpu_resp_bits_uop_stale_pdst_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_exception_0; // @[execution-unit.scala:330:7] wire [63:0] io_ifpu_resp_bits_uop_exc_cause_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_uop_mem_cmd_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_mem_size_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_mem_signed_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_uses_ldq_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_uses_stq_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_is_unique_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_csr_cmd_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_ldst_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_lrs1_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_lrs2_0; // @[execution-unit.scala:330:7] wire [5:0] io_ifpu_resp_bits_uop_lrs3_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_dst_rtype_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_frs3_en_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fcn_dw_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_uop_fcn_op_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_fp_val_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_fp_rm_0; // @[execution-unit.scala:330:7] wire [1:0] io_ifpu_resp_bits_uop_fp_typ_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:330:7] wire [2:0] io_ifpu_resp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_fflags_valid_0; // @[execution-unit.scala:330:7] wire [4:0] io_ifpu_resp_bits_fflags_bits_0; // @[execution-unit.scala:330:7] wire [64:0] io_ifpu_resp_bits_data_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_bits_predicated_0; // @[execution-unit.scala:330:7] wire io_ifpu_resp_valid_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iq_type_0_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iq_type_1_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iq_type_2_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iq_type_3_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_0_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_1_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_2_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_3_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_4_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_5_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_6_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_7_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_8_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fu_code_9_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_ldst_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_wen_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_ren1_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_ren2_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_ren3_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_swap12_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_swap23_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_fromint_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_toint_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_fastpipe_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_fma_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_div_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_sqrt_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_wflags_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_ctrl_vec_0; // @[execution-unit.scala:330:7] wire [31:0] io_div_resp_bits_uop_inst_0; // @[execution-unit.scala:330:7] wire [31:0] io_div_resp_bits_uop_debug_inst_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_rvc_0; // @[execution-unit.scala:330:7] wire [39:0] io_div_resp_bits_uop_debug_pc_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_issued_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_issued_partial_agen_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_issued_partial_dgen_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_iw_p1_speculative_child_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_iw_p2_speculative_child_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_p1_bypass_hint_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_p2_bypass_hint_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_iw_p3_bypass_hint_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_dis_col_sel_0; // @[execution-unit.scala:330:7] wire [11:0] io_div_resp_bits_uop_br_mask_0; // @[execution-unit.scala:330:7] wire [3:0] io_div_resp_bits_uop_br_tag_0; // @[execution-unit.scala:330:7] wire [3:0] io_div_resp_bits_uop_br_type_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_sfb_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_fence_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_fencei_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_sfence_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_amo_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_eret_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_rocc_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_mov_0; // @[execution-unit.scala:330:7] wire [4:0] io_div_resp_bits_uop_ftq_idx_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_edge_inst_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_pc_lob_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_taken_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_imm_rename_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_imm_sel_0; // @[execution-unit.scala:330:7] wire [4:0] io_div_resp_bits_uop_pimm_0; // @[execution-unit.scala:330:7] wire [19:0] io_div_resp_bits_uop_imm_packed_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_op1_sel_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_op2_sel_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_rob_idx_0; // @[execution-unit.scala:330:7] wire [3:0] io_div_resp_bits_uop_ldq_idx_0; // @[execution-unit.scala:330:7] wire [3:0] io_div_resp_bits_uop_stq_idx_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_rxq_idx_0; // @[execution-unit.scala:330:7] wire [6:0] io_div_resp_bits_uop_pdst_0; // @[execution-unit.scala:330:7] wire [6:0] io_div_resp_bits_uop_prs1_0; // @[execution-unit.scala:330:7] wire [6:0] io_div_resp_bits_uop_prs2_0; // @[execution-unit.scala:330:7] wire [6:0] io_div_resp_bits_uop_prs3_0; // @[execution-unit.scala:330:7] wire [4:0] io_div_resp_bits_uop_ppred_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_prs1_busy_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_prs2_busy_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_prs3_busy_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_ppred_busy_0; // @[execution-unit.scala:330:7] wire [6:0] io_div_resp_bits_uop_stale_pdst_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_exception_0; // @[execution-unit.scala:330:7] wire [63:0] io_div_resp_bits_uop_exc_cause_0; // @[execution-unit.scala:330:7] wire [4:0] io_div_resp_bits_uop_mem_cmd_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_mem_size_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_mem_signed_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_uses_ldq_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_uses_stq_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_is_unique_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_csr_cmd_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_ldst_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_lrs1_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_lrs2_0; // @[execution-unit.scala:330:7] wire [5:0] io_div_resp_bits_uop_lrs3_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_dst_rtype_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_frs3_en_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fcn_dw_0; // @[execution-unit.scala:330:7] wire [4:0] io_div_resp_bits_uop_fcn_op_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_fp_val_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_fp_rm_0; // @[execution-unit.scala:330:7] wire [1:0] io_div_resp_bits_uop_fp_typ_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:330:7] wire io_div_resp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:330:7] wire [2:0] io_div_resp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:330:7] wire [63:0] io_div_resp_bits_data_0; // @[execution-unit.scala:330:7] wire io_div_resp_valid_0; // @[execution-unit.scala:330:7] reg arb_uop_valid; // @[execution-unit.scala:92:20] reg [31:0] arb_uop_bits_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_inst = arb_uop_bits_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_inst = arb_uop_bits_inst; // @[util.scala:104:23] reg [31:0] arb_uop_bits_debug_inst; // @[execution-unit.scala:92:20] wire [31:0] rrd_uop_bits_out_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] wire [31:0] arb_uop_bits_out_1_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23] reg arb_uop_bits_is_rvc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23] reg [39:0] arb_uop_bits_debug_pc; // @[execution-unit.scala:92:20] wire [39:0] rrd_uop_bits_out_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] wire [39:0] arb_uop_bits_out_1_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23] reg arb_uop_bits_iq_type_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23] reg arb_uop_bits_iq_type_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23] reg arb_uop_bits_iq_type_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23] reg arb_uop_bits_iq_type_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_0; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23] reg arb_uop_bits_fu_code_1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23] reg arb_uop_bits_fu_code_2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23] reg arb_uop_bits_fu_code_3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23] reg arb_uop_bits_fu_code_4; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23] reg arb_uop_bits_fu_code_5; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23] reg arb_uop_bits_fu_code_6; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23] reg arb_uop_bits_fu_code_7; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23] reg arb_uop_bits_fu_code_8; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23] reg arb_uop_bits_fu_code_9; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] wire arb_uop_bits_out_1_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23] reg arb_uop_bits_iw_issued; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg arb_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] arb_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg arb_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire arb_uop_bits_out_1_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dis_col_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] arb_uop_bits_br_mask; // @[execution-unit.scala:92:20] reg [3:0] arb_uop_bits_br_tag; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23] reg [3:0] arb_uop_bits_br_type; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_br_type = arb_uop_bits_br_type; // @[util.scala:104:23] reg arb_uop_bits_is_sfb; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23] reg arb_uop_bits_is_fence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23] reg arb_uop_bits_is_fencei; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23] reg arb_uop_bits_is_sfence; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23] reg arb_uop_bits_is_amo; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23] reg arb_uop_bits_is_eret; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23] reg arb_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] reg arb_uop_bits_is_rocc; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23] reg arb_uop_bits_is_mov; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23] reg arb_uop_bits_edge_inst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] wire arb_uop_bits_out_1_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_pc_lob; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23] reg arb_uop_bits_taken; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_taken = arb_uop_bits_taken; // @[util.scala:104:23] wire arb_uop_bits_out_1_taken = arb_uop_bits_taken; // @[util.scala:104:23] reg arb_uop_bits_imm_rename; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] wire arb_uop_bits_out_1_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23] reg [2:0] arb_uop_bits_imm_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23] reg [4:0] arb_uop_bits_pimm; // @[execution-unit.scala:92:20] assign io_arb_immrf_req_bits_0 = arb_uop_bits_pimm; // @[execution-unit.scala:92:20, :330:7] wire [4:0] rrd_uop_bits_out_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_pimm = arb_uop_bits_pimm; // @[util.scala:104:23] reg [19:0] arb_uop_bits_imm_packed; // @[execution-unit.scala:92:20] wire [19:0] rrd_uop_bits_out_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] wire [19:0] arb_uop_bits_out_1_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23] reg [1:0] arb_uop_bits_op1_sel; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23] reg [2:0] arb_uop_bits_op2_sel; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_div; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg arb_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] arb_uop_bits_rob_idx; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_ldq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] arb_uop_bits_stq_idx; // @[execution-unit.scala:92:20] wire [3:0] rrd_uop_bits_out_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] wire [3:0] arb_uop_bits_out_1_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23] reg [1:0] arb_uop_bits_rxq_idx; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] arb_uop_bits_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_pdst = arb_uop_bits_pdst; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs1; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_0_bits_0 = arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :330:7] wire [6:0] rrd_uop_bits_out_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs2; // @[execution-unit.scala:92:20] assign io_arb_irf_reqs_1_bits_0 = arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :330:7] wire [6:0] rrd_uop_bits_out_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23] reg [6:0] arb_uop_bits_prs3; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23] reg [4:0] arb_uop_bits_ppred; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_ppred = arb_uop_bits_ppred; // @[util.scala:104:23] reg arb_uop_bits_prs1_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23] reg arb_uop_bits_prs2_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23] reg arb_uop_bits_prs3_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23] reg arb_uop_bits_ppred_busy; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] wire arb_uop_bits_out_1_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] arb_uop_bits_stale_pdst; // @[execution-unit.scala:92:20] wire [6:0] rrd_uop_bits_out_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] arb_uop_bits_out_1_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23] reg arb_uop_bits_exception; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_exception = arb_uop_bits_exception; // @[util.scala:104:23] wire arb_uop_bits_out_1_exception = arb_uop_bits_exception; // @[util.scala:104:23] reg [63:0] arb_uop_bits_exc_cause; // @[execution-unit.scala:92:20] wire [63:0] rrd_uop_bits_out_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] wire [63:0] arb_uop_bits_out_1_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23] reg [4:0] arb_uop_bits_mem_cmd; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] arb_uop_bits_mem_size; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23] reg arb_uop_bits_mem_signed; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] wire arb_uop_bits_out_1_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23] reg arb_uop_bits_uses_ldq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23] reg arb_uop_bits_uses_stq; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] wire arb_uop_bits_out_1_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23] reg arb_uop_bits_is_unique; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] wire arb_uop_bits_out_1_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23] reg arb_uop_bits_flush_on_commit; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] wire arb_uop_bits_out_1_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] arb_uop_bits_csr_cmd; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23] reg arb_uop_bits_ldst_is_rs1; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire arb_uop_bits_out_1_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_ldst; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_ldst = arb_uop_bits_ldst; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs1; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs2; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23] reg [5:0] arb_uop_bits_lrs3; // @[execution-unit.scala:92:20] wire [5:0] rrd_uop_bits_out_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] wire [5:0] arb_uop_bits_out_1_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23] reg [1:0] arb_uop_bits_dst_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs1_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] arb_uop_bits_lrs2_rtype; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23] reg arb_uop_bits_frs3_en; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] wire arb_uop_bits_out_1_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23] reg arb_uop_bits_fcn_dw; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] wire arb_uop_bits_out_1_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] arb_uop_bits_fcn_op; // @[execution-unit.scala:92:20] wire [4:0] rrd_uop_bits_out_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] wire [4:0] arb_uop_bits_out_1_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23] reg arb_uop_bits_fp_val; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] wire arb_uop_bits_out_1_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23] reg [2:0] arb_uop_bits_fp_rm; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23] reg [1:0] arb_uop_bits_fp_typ; // @[execution-unit.scala:92:20] wire [1:0] rrd_uop_bits_out_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] wire [1:0] arb_uop_bits_out_1_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23] reg arb_uop_bits_xcpt_pf_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ae_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23] reg arb_uop_bits_xcpt_ma_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23] reg arb_uop_bits_bp_debug_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23] reg arb_uop_bits_bp_xcpt_if; // @[execution-unit.scala:92:20] wire rrd_uop_bits_out_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire arb_uop_bits_out_1_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_fsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] arb_uop_bits_debug_tsrc; // @[execution-unit.scala:92:20] wire [2:0] rrd_uop_bits_out_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] arb_uop_bits_out_1_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _arb_uop_valid_T = io_brupdate_b1_mispredict_mask & io_iss_uop_bits_br_mask; // @[util.scala:126:51] wire _arb_uop_valid_T_1 = |_arb_uop_valid_T; // @[util.scala:126:{51,59}] wire _arb_uop_valid_T_2 = _arb_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59] wire _arb_uop_valid_T_3 = ~_arb_uop_valid_T_2; // @[util.scala:61:61] wire _arb_uop_valid_T_4 = io_iss_uop_valid & _arb_uop_valid_T_3; // @[execution-unit.scala:93:{37,40}] wire [11:0] _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] arb_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _arb_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _arb_uop_bits_out_br_mask_T_1 = io_iss_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign arb_uop_bits_out_br_mask = _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg rrd_uop_valid; // @[execution-unit.scala:95:20] wire [31:0] exe_uop_bits_out_inst = rrd_uop_bits_inst; // @[util.scala:104:23] wire [31:0] exe_uop_bits_out_debug_inst = rrd_uop_bits_debug_inst; // @[util.scala:104:23] wire exe_uop_bits_out_is_rvc = rrd_uop_bits_is_rvc; // @[util.scala:104:23] wire [39:0] exe_uop_bits_out_debug_pc = rrd_uop_bits_debug_pc; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_0 = rrd_uop_bits_iq_type_0; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_1 = rrd_uop_bits_iq_type_1; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_2 = rrd_uop_bits_iq_type_2; // @[util.scala:104:23] wire exe_uop_bits_out_iq_type_3 = rrd_uop_bits_iq_type_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_0 = rrd_uop_bits_fu_code_0; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_1 = rrd_uop_bits_fu_code_1; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_2 = rrd_uop_bits_fu_code_2; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_3 = rrd_uop_bits_fu_code_3; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_4 = rrd_uop_bits_fu_code_4; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_5 = rrd_uop_bits_fu_code_5; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_6 = rrd_uop_bits_fu_code_6; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_7 = rrd_uop_bits_fu_code_7; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_8 = rrd_uop_bits_fu_code_8; // @[util.scala:104:23] wire exe_uop_bits_out_fu_code_9 = rrd_uop_bits_fu_code_9; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued = rrd_uop_bits_iw_issued; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_agen = rrd_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire exe_uop_bits_out_iw_issued_partial_dgen = rrd_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p1_speculative_child = rrd_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_iw_p2_speculative_child = rrd_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p1_bypass_hint = rrd_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p2_bypass_hint = rrd_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire exe_uop_bits_out_iw_p3_bypass_hint = rrd_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dis_col_sel = rrd_uop_bits_dis_col_sel; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_tag = rrd_uop_bits_br_tag; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_br_type = rrd_uop_bits_br_type; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfb = rrd_uop_bits_is_sfb; // @[util.scala:104:23] wire exe_uop_bits_out_is_fence = rrd_uop_bits_is_fence; // @[util.scala:104:23] wire exe_uop_bits_out_is_fencei = rrd_uop_bits_is_fencei; // @[util.scala:104:23] wire exe_uop_bits_out_is_sfence = rrd_uop_bits_is_sfence; // @[util.scala:104:23] wire exe_uop_bits_out_is_amo = rrd_uop_bits_is_amo; // @[util.scala:104:23] wire exe_uop_bits_out_is_eret = rrd_uop_bits_is_eret; // @[util.scala:104:23] wire exe_uop_bits_out_is_sys_pc2epc = rrd_uop_bits_is_sys_pc2epc; // @[util.scala:104:23] wire exe_uop_bits_out_is_rocc = rrd_uop_bits_is_rocc; // @[util.scala:104:23] wire exe_uop_bits_out_is_mov = rrd_uop_bits_is_mov; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ftq_idx = rrd_uop_bits_ftq_idx; // @[util.scala:104:23] wire exe_uop_bits_out_edge_inst = rrd_uop_bits_edge_inst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_pc_lob = rrd_uop_bits_pc_lob; // @[util.scala:104:23] wire exe_uop_bits_out_taken = rrd_uop_bits_taken; // @[util.scala:104:23] wire exe_uop_bits_out_imm_rename = rrd_uop_bits_imm_rename; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_imm_sel = rrd_uop_bits_imm_sel; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_pimm = rrd_uop_bits_pimm; // @[util.scala:104:23] wire [19:0] exe_uop_bits_out_imm_packed = rrd_uop_bits_imm_packed; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_op1_sel = rrd_uop_bits_op1_sel; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_op2_sel = rrd_uop_bits_op2_sel; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ldst = rrd_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wen = rrd_uop_bits_fp_ctrl_wen; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren1 = rrd_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren2 = rrd_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_ren3 = rrd_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap12 = rrd_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_swap23 = rrd_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagIn = rrd_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagOut = rrd_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fromint = rrd_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_toint = rrd_uop_bits_fp_ctrl_toint; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fastpipe = rrd_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_fma = rrd_uop_bits_fp_ctrl_fma; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_div = rrd_uop_bits_fp_ctrl_div; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_sqrt = rrd_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_wflags = rrd_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire exe_uop_bits_out_fp_ctrl_vec = rrd_uop_bits_fp_ctrl_vec; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_rob_idx = rrd_uop_bits_rob_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_ldq_idx = rrd_uop_bits_ldq_idx; // @[util.scala:104:23] wire [3:0] exe_uop_bits_out_stq_idx = rrd_uop_bits_stq_idx; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_rxq_idx = rrd_uop_bits_rxq_idx; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_pdst = rrd_uop_bits_pdst; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs1 = rrd_uop_bits_prs1; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs2 = rrd_uop_bits_prs2; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_prs3 = rrd_uop_bits_prs3; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_ppred = rrd_uop_bits_ppred; // @[util.scala:104:23] wire exe_uop_bits_out_prs1_busy = rrd_uop_bits_prs1_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs2_busy = rrd_uop_bits_prs2_busy; // @[util.scala:104:23] wire exe_uop_bits_out_prs3_busy = rrd_uop_bits_prs3_busy; // @[util.scala:104:23] wire exe_uop_bits_out_ppred_busy = rrd_uop_bits_ppred_busy; // @[util.scala:104:23] wire [6:0] exe_uop_bits_out_stale_pdst = rrd_uop_bits_stale_pdst; // @[util.scala:104:23] wire exe_uop_bits_out_exception = rrd_uop_bits_exception; // @[util.scala:104:23] wire [63:0] exe_uop_bits_out_exc_cause = rrd_uop_bits_exc_cause; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_mem_cmd = rrd_uop_bits_mem_cmd; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_mem_size = rrd_uop_bits_mem_size; // @[util.scala:104:23] wire exe_uop_bits_out_mem_signed = rrd_uop_bits_mem_signed; // @[util.scala:104:23] wire exe_uop_bits_out_uses_ldq = rrd_uop_bits_uses_ldq; // @[util.scala:104:23] wire exe_uop_bits_out_uses_stq = rrd_uop_bits_uses_stq; // @[util.scala:104:23] wire exe_uop_bits_out_is_unique = rrd_uop_bits_is_unique; // @[util.scala:104:23] wire exe_uop_bits_out_flush_on_commit = rrd_uop_bits_flush_on_commit; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_csr_cmd = rrd_uop_bits_csr_cmd; // @[util.scala:104:23] wire exe_uop_bits_out_ldst_is_rs1 = rrd_uop_bits_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_ldst = rrd_uop_bits_ldst; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs1 = rrd_uop_bits_lrs1; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs2 = rrd_uop_bits_lrs2; // @[util.scala:104:23] wire [5:0] exe_uop_bits_out_lrs3 = rrd_uop_bits_lrs3; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_dst_rtype = rrd_uop_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs1_rtype = rrd_uop_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_lrs2_rtype = rrd_uop_bits_lrs2_rtype; // @[util.scala:104:23] wire exe_uop_bits_out_frs3_en = rrd_uop_bits_frs3_en; // @[util.scala:104:23] wire exe_uop_bits_out_fcn_dw = rrd_uop_bits_fcn_dw; // @[util.scala:104:23] wire [4:0] exe_uop_bits_out_fcn_op = rrd_uop_bits_fcn_op; // @[util.scala:104:23] wire exe_uop_bits_out_fp_val = rrd_uop_bits_fp_val; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_fp_rm = rrd_uop_bits_fp_rm; // @[util.scala:104:23] wire [1:0] exe_uop_bits_out_fp_typ = rrd_uop_bits_fp_typ; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_pf_if = rrd_uop_bits_xcpt_pf_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ae_if = rrd_uop_bits_xcpt_ae_if; // @[util.scala:104:23] wire exe_uop_bits_out_xcpt_ma_if = rrd_uop_bits_xcpt_ma_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_debug_if = rrd_uop_bits_bp_debug_if; // @[util.scala:104:23] wire exe_uop_bits_out_bp_xcpt_if = rrd_uop_bits_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_fsrc = rrd_uop_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] exe_uop_bits_out_debug_tsrc = rrd_uop_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _GEN = io_brupdate_b1_mispredict_mask & arb_uop_bits_br_mask; // @[util.scala:126:51] wire [11:0] _rrd_uop_valid_T; // @[util.scala:126:51] assign _rrd_uop_valid_T = _GEN; // @[util.scala:126:51] wire [11:0] _will_replay_T; // @[util.scala:126:51] assign _will_replay_T = _GEN; // @[util.scala:126:51] wire _rrd_uop_valid_T_1 = |_rrd_uop_valid_T; // @[util.scala:126:{51,59}] wire _rrd_uop_valid_T_2 = _rrd_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59] wire _rrd_uop_valid_T_3 = ~_rrd_uop_valid_T_2; // @[util.scala:61:61] wire _rrd_uop_valid_T_4 = arb_uop_valid & _rrd_uop_valid_T_3; // @[execution-unit.scala:92:20, :96:{34,37}] wire [11:0] _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] rrd_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _rrd_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _rrd_uop_bits_out_br_mask_T_1 = arb_uop_bits_br_mask & _rrd_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign rrd_uop_bits_out_br_mask = _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg exe_uop_valid; // @[execution-unit.scala:98:20] reg [31:0] exe_uop_bits_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_inst = exe_uop_bits_inst; // @[execution-unit.scala:98:20, :357:25] reg [31:0] exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20] wire [31:0] exe_int_req_uop_debug_inst = exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rvc = exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20, :357:25] reg [39:0] exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20] wire [39:0] exe_int_req_uop_debug_pc = exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_0 = exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_1 = exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_2 = exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iq_type_3 = exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_0 = exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_1 = exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_2 = exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_3 = exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_4 = exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_5 = exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_6 = exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_7 = exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_8 = exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fu_code_9 = exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued = exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_agen = exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_issued_partial_dgen = exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p1_speculative_child = exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_iw_p2_speculative_child = exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p1_bypass_hint = exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p2_bypass_hint = exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_iw_p3_bypass_hint = exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dis_col_sel = exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20, :357:25] reg [11:0] exe_uop_bits_br_mask; // @[execution-unit.scala:98:20] wire [11:0] exe_int_req_uop_br_mask = exe_uop_bits_br_mask; // @[execution-unit.scala:98:20, :357:25] reg [3:0] exe_uop_bits_br_tag; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_tag = exe_uop_bits_br_tag; // @[execution-unit.scala:98:20, :357:25] reg [3:0] exe_uop_bits_br_type; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_br_type = exe_uop_bits_br_type; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfb = exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_fence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fence = exe_uop_bits_is_fence; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_fencei = exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sfence = exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_amo; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_amo = exe_uop_bits_is_amo; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_eret; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_eret = exe_uop_bits_is_eret; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_sys_pc2epc = exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_rocc = exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_mov; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_mov = exe_uop_bits_is_mov; // @[execution-unit.scala:98:20, :357:25] reg [4:0] exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ftq_idx = exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_edge_inst = exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_pc_lob = exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_taken; // @[execution-unit.scala:98:20] wire exe_int_req_uop_taken = exe_uop_bits_taken; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20] wire exe_int_req_uop_imm_rename = exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_imm_sel = exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20, :357:25] reg [4:0] exe_uop_bits_pimm; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_pimm = exe_uop_bits_pimm; // @[execution-unit.scala:98:20, :357:25] reg [19:0] exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20] wire [19:0] exe_int_req_uop_imm_packed = exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_op1_sel = exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_op2_sel = exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ldst = exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wen = exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren1 = exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren2 = exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_ren3 = exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap12 = exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_swap23 = exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagIn = exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_ctrl_typeTagOut = exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fromint = exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_toint = exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fastpipe = exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_fma = exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_div = exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_sqrt = exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_wflags = exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_ctrl_vec = exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_rob_idx = exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20, :357:25] reg [3:0] exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_ldq_idx = exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20, :357:25] reg [3:0] exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20] wire [3:0] exe_int_req_uop_stq_idx = exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_rxq_idx = exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20, :357:25] reg [6:0] exe_uop_bits_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_pdst = exe_uop_bits_pdst; // @[execution-unit.scala:98:20, :357:25] reg [6:0] exe_uop_bits_prs1; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs1 = exe_uop_bits_prs1; // @[execution-unit.scala:98:20, :357:25] reg [6:0] exe_uop_bits_prs2; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs2 = exe_uop_bits_prs2; // @[execution-unit.scala:98:20, :357:25] reg [6:0] exe_uop_bits_prs3; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_prs3 = exe_uop_bits_prs3; // @[execution-unit.scala:98:20, :357:25] reg [4:0] exe_uop_bits_ppred; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_ppred = exe_uop_bits_ppred; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs1_busy = exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs2_busy = exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_prs3_busy = exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ppred_busy = exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20, :357:25] reg [6:0] exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20] wire [6:0] exe_int_req_uop_stale_pdst = exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_exception; // @[execution-unit.scala:98:20] wire exe_int_req_uop_exception = exe_uop_bits_exception; // @[execution-unit.scala:98:20, :357:25] reg [63:0] exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20] wire [63:0] exe_int_req_uop_exc_cause = exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20, :357:25] reg [4:0] exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_mem_cmd = exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_mem_size; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_mem_size = exe_uop_bits_mem_size; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20] wire exe_int_req_uop_mem_signed = exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_ldq = exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20] wire exe_int_req_uop_uses_stq = exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_is_unique; // @[execution-unit.scala:98:20] wire exe_int_req_uop_is_unique = exe_uop_bits_is_unique; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20] wire exe_int_req_uop_flush_on_commit = exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_csr_cmd = exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20] wire exe_int_req_uop_ldst_is_rs1 = exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_ldst; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_ldst = exe_uop_bits_ldst; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_lrs1; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs1 = exe_uop_bits_lrs1; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_lrs2; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs2 = exe_uop_bits_lrs2; // @[execution-unit.scala:98:20, :357:25] reg [5:0] exe_uop_bits_lrs3; // @[execution-unit.scala:98:20] wire [5:0] exe_int_req_uop_lrs3 = exe_uop_bits_lrs3; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_dst_rtype = exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs1_rtype = exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_lrs2_rtype = exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20] wire exe_int_req_uop_frs3_en = exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fcn_dw = exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20, :357:25] reg [4:0] exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20] wire [4:0] exe_int_req_uop_fcn_op = exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_fp_val; // @[execution-unit.scala:98:20] wire exe_int_req_uop_fp_val = exe_uop_bits_fp_val; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_fp_rm = exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20, :357:25] reg [1:0] exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20] wire [1:0] exe_int_req_uop_fp_typ = exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_pf_if = exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ae_if = exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_xcpt_ma_if = exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_debug_if = exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20, :357:25] reg exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20] wire exe_int_req_uop_bp_xcpt_if = exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_fsrc = exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20, :357:25] reg [2:0] exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20] wire [2:0] exe_int_req_uop_debug_tsrc = exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20, :357:25] wire [11:0] _exe_uop_valid_T = io_brupdate_b1_mispredict_mask & rrd_uop_bits_br_mask; // @[util.scala:126:51] wire _exe_uop_valid_T_1 = |_exe_uop_valid_T; // @[util.scala:126:{51,59}] wire _exe_uop_valid_T_2 = _exe_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59] wire _exe_uop_valid_T_3 = ~_exe_uop_valid_T_2; // @[util.scala:61:61] wire _exe_uop_valid_T_4 = rrd_uop_valid & _exe_uop_valid_T_3; // @[execution-unit.scala:95:20, :99:{34,37}] wire [11:0] _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] exe_uop_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _exe_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _exe_uop_bits_out_br_mask_T_1 = rrd_uop_bits_br_mask & _exe_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign exe_uop_bits_out_br_mask = _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _GEN_0 = arb_uop_bits_lrs1_rtype == 2'h0; // @[execution-unit.scala:92:20, :121:72] wire _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:121:72] assign _io_arb_irf_reqs_0_valid_T = _GEN_0; // @[execution-unit.scala:121:72] wire _arb_rebusied_prs1_T; // @[execution-unit.scala:128:51] assign _arb_rebusied_prs1_T = _GEN_0; // @[execution-unit.scala:121:72, :128:51] wire _io_arb_irf_reqs_0_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:92:20, :121:{45,72}] wire _io_arb_irf_reqs_0_valid_T_2 = ~arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20, :121:86] assign _io_arb_irf_reqs_0_valid_T_3 = _io_arb_irf_reqs_0_valid_T_1 & _io_arb_irf_reqs_0_valid_T_2; // @[execution-unit.scala:121:{45,83,86}] assign io_arb_irf_reqs_0_valid_0 = _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83, :330:7] wire _GEN_1 = arb_uop_bits_lrs2_rtype == 2'h0; // @[execution-unit.scala:92:20, :125:74] wire _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:125:74] assign _io_arb_irf_reqs_1_valid_T = _GEN_1; // @[execution-unit.scala:125:74] wire _arb_rebusied_prs2_T; // @[execution-unit.scala:129:51] assign _arb_rebusied_prs2_T = _GEN_1; // @[execution-unit.scala:125:74, :129:51] wire _io_arb_irf_reqs_1_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_1_valid_T; // @[execution-unit.scala:92:20, :125:{47,74}] wire _io_arb_irf_reqs_1_valid_T_2 = ~arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20, :125:88] assign _io_arb_irf_reqs_1_valid_T_3 = _io_arb_irf_reqs_1_valid_T_1 & _io_arb_irf_reqs_1_valid_T_2; // @[execution-unit.scala:125:{47,85,88}] assign io_arb_irf_reqs_1_valid_0 = _io_arb_irf_reqs_1_valid_T_3; // @[execution-unit.scala:125:85, :330:7] wire _GEN_2 = io_arb_rebusys_0_valid & io_arb_rebusys_0_bits_rebusy; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs1_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs2_T_1; // @[execution-unit.scala:118:39] assign _arb_rebusied_prs2_T_1 = _GEN_2; // @[execution-unit.scala:118:39] wire _arb_rebusied_prs1_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs1_T_3 = _arb_rebusied_prs1_T_1 & _arb_rebusied_prs1_T_2; // @[execution-unit.scala:118:{39,56,75}] wire arb_rebusied_prs1 = _arb_rebusied_prs1_T & _arb_rebusied_prs1_T_3; // @[execution-unit.scala:118:56, :128:{51,62}] wire _arb_rebusied_prs2_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :118:75] wire _arb_rebusied_prs2_T_3 = _arb_rebusied_prs2_T_1 & _arb_rebusied_prs2_T_2; // @[execution-unit.scala:118:{39,56,75}] wire _arb_rebusied_prs2_T_4 = _arb_rebusied_prs2_T & _arb_rebusied_prs2_T_3; // @[execution-unit.scala:118:56, :129:{51,62}] wire arb_rebusied_prs2 = _arb_rebusied_prs2_T_4; // @[execution-unit.scala:129:{62,93}] wire arb_rebusied = arb_rebusied_prs1 | arb_rebusied_prs2; // @[execution-unit.scala:128:62, :129:93, :130:45] reg [63:0] exe_rs1_data; // @[execution-unit.scala:133:25] wire [63:0] exe_int_req_rs1_data = exe_rs1_data; // @[execution-unit.scala:133:25, :357:25] reg [63:0] exe_rs2_data; // @[execution-unit.scala:134:25] wire [63:0] exe_int_req_rs2_data = exe_rs2_data; // @[execution-unit.scala:134:25, :357:25] wire _hits_T = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0 = io_rrd_irf_bypasses_0_valid & _hits_T; // @[execution-unit.scala:113:{55,62}] wire _hits_T_1 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1 = io_rrd_irf_bypasses_1_valid & _hits_T_1; // @[execution-unit.scala:113:{55,62}] wire _hits_T_2 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2 = io_rrd_irf_bypasses_2_valid & _hits_T_2; // @[execution-unit.scala:113:{55,62}] wire _T_1 = hits_0 | hits_1; // @[execution-unit.scala:113:55, :114:19] wire rs1_hit = _T_1 | hits_2; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs1_data = _T_1 | hits_2 ? (hits_0 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) | (hits_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) | (hits_2 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_0; // @[Mux.scala:30:73] wire _exe_rs1_data_T = &rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20, :137:47] wire [63:0] _exe_rs1_data_T_1 = _exe_rs1_data_T ? 64'h0 : rs1_data; // @[execution-unit.scala:114:28, :137:{22,47}] wire _hits_T_3 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_0_1 = io_rrd_irf_bypasses_0_valid & _hits_T_3; // @[execution-unit.scala:113:{55,62}] wire _hits_T_4 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_1_1 = io_rrd_irf_bypasses_1_valid & _hits_T_4; // @[execution-unit.scala:113:{55,62}] wire _hits_T_5 = rrd_uop_bits_prs2 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62] wire hits_2_1 = io_rrd_irf_bypasses_2_valid & _hits_T_5; // @[execution-unit.scala:113:{55,62}] wire _T_18 = hits_0_1 | hits_1_1; // @[execution-unit.scala:113:55, :114:19] wire rs2_hit = _T_18 | hits_2_1; // @[execution-unit.scala:113:55, :114:19] wire [63:0] rs2_data = _T_18 | hits_2_1 ? (hits_0_1 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) | (hits_1_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) | (hits_2_1 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_1; // @[Mux.scala:30:73] wire _exe_rs2_data_T = &rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20, :142:49] wire [63:0] _exe_rs2_data_T_1 = _exe_rs2_data_T ? 64'h0 : rs2_data; // @[execution-unit.scala:114:28, :142:{24,49}] wire _io_arb_immrf_req_valid_T = arb_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47] wire _io_arb_immrf_req_valid_T_1 = arb_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47] wire _io_arb_immrf_req_valid_T_2 = _io_arb_immrf_req_valid_T | _io_arb_immrf_req_valid_T_1; // @[package.scala:16:47, :81:59] wire _io_arb_immrf_req_valid_T_3 = ~_io_arb_immrf_req_valid_T_2; // @[package.scala:81:59] assign _io_arb_immrf_req_valid_T_4 = arb_uop_valid & _io_arb_immrf_req_valid_T_3; // @[execution-unit.scala:92:20, :157:44, :158:5] assign io_arb_immrf_req_valid_0 = _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44, :330:7] wire _GEN_3 = rrd_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47] wire _io_rrd_immrf_wakeup_valid_T; // @[package.scala:16:47] assign _io_rrd_immrf_wakeup_valid_T = _GEN_3; // @[package.scala:16:47] wire _exe_imm_data_ip_T; // @[util.scala:282:23] assign _exe_imm_data_ip_T = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = rrd_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47] wire _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47] assign _io_rrd_immrf_wakeup_valid_T_1 = _GEN_4; // @[package.scala:16:47] wire _exe_imm_data_T; // @[execution-unit.scala:170:55] assign _exe_imm_data_T = _GEN_4; // @[package.scala:16:47] wire _io_rrd_immrf_wakeup_valid_T_2 = _io_rrd_immrf_wakeup_valid_T | _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47, :81:59] wire _io_rrd_immrf_wakeup_valid_T_3 = ~_io_rrd_immrf_wakeup_valid_T_2; // @[package.scala:81:59] assign _io_rrd_immrf_wakeup_valid_T_4 = rrd_uop_valid & _io_rrd_immrf_wakeup_valid_T_3; // @[execution-unit.scala:95:20, :162:47, :163:5] wire _exe_imm_data_T_1 = rrd_uop_bits_pimm[4]; // @[util.scala:269:46] wire [58:0] _exe_imm_data_T_2 = {59{_exe_imm_data_T_1}}; // @[util.scala:269:{25,46}] wire [63:0] _exe_imm_data_T_3 = {_exe_imm_data_T_2, rrd_uop_bits_pimm}; // @[util.scala:269:{20,25}] wire [63:0] exe_imm_data_ip = _exe_imm_data_ip_T ? 64'h0 : io_rrd_immrf_resp; // @[util.scala:282:{17,23}] wire _exe_imm_data_sign_T = exe_imm_data_ip[19]; // @[util.scala:282:17, :284:18] wire exe_imm_data_sign = _exe_imm_data_sign_T; // @[util.scala:284:{18,37}] wire exe_imm_data_hi_hi_hi = exe_imm_data_sign; // @[util.scala:284:37, :294:15] wire _GEN_5 = rrd_uop_bits_imm_sel == 3'h3; // @[util.scala:285:27] wire _exe_imm_data_i30_20_T; // @[util.scala:285:27] assign _exe_imm_data_i30_20_T = _GEN_5; // @[util.scala:285:27] wire _exe_imm_data_i19_12_T; // @[util.scala:286:27] assign _exe_imm_data_i19_12_T = _GEN_5; // @[util.scala:285:27, :286:27] wire _exe_imm_data_i11_T; // @[util.scala:287:27] assign _exe_imm_data_i11_T = _GEN_5; // @[util.scala:285:27, :287:27] wire _exe_imm_data_i10_5_T; // @[util.scala:289:27] assign _exe_imm_data_i10_5_T = _GEN_5; // @[util.scala:285:27, :289:27] wire _exe_imm_data_i4_1_T; // @[util.scala:290:27] assign _exe_imm_data_i4_1_T = _GEN_5; // @[util.scala:285:27, :290:27] wire [10:0] _exe_imm_data_i30_20_T_1 = exe_imm_data_ip[18:8]; // @[util.scala:282:17, :285:39] wire [10:0] _exe_imm_data_i30_20_T_2 = _exe_imm_data_i30_20_T_1; // @[util.scala:285:{39,46}] wire [10:0] exe_imm_data_i30_20 = _exe_imm_data_i30_20_T ? _exe_imm_data_i30_20_T_2 : {11{exe_imm_data_sign}}; // @[util.scala:284:37, :285:{21,27,46}] wire [10:0] exe_imm_data_hi_hi_lo = exe_imm_data_i30_20; // @[util.scala:285:21, :294:15] wire _GEN_6 = rrd_uop_bits_imm_sel == 3'h4; // @[util.scala:286:44] wire _exe_imm_data_i19_12_T_1; // @[util.scala:286:44] assign _exe_imm_data_i19_12_T_1 = _GEN_6; // @[util.scala:286:44] wire _exe_imm_data_i11_T_1; // @[util.scala:288:27] assign _exe_imm_data_i11_T_1 = _GEN_6; // @[util.scala:286:44, :288:27] wire _exe_imm_data_i19_12_T_2 = _exe_imm_data_i19_12_T | _exe_imm_data_i19_12_T_1; // @[util.scala:286:{27,36,44}] wire [7:0] _exe_imm_data_i19_12_T_3 = exe_imm_data_ip[7:0]; // @[util.scala:282:17, :286:56] wire [7:0] _exe_imm_data_i19_12_T_4 = _exe_imm_data_i19_12_T_3; // @[util.scala:286:{56,62}] wire [7:0] exe_imm_data_i19_12 = _exe_imm_data_i19_12_T_2 ? _exe_imm_data_i19_12_T_4 : {8{exe_imm_data_sign}}; // @[util.scala:284:37, :286:{21,36,62}] wire [7:0] exe_imm_data_hi_lo_hi = exe_imm_data_i19_12; // @[util.scala:286:21, :294:15] wire _exe_imm_data_i11_T_2 = rrd_uop_bits_imm_sel == 3'h2; // @[util.scala:288:44] wire _exe_imm_data_i11_T_3 = _exe_imm_data_i11_T_1 | _exe_imm_data_i11_T_2; // @[util.scala:288:{27,36,44}] wire _exe_imm_data_i11_T_4 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56] wire _exe_imm_data_i0_T_3 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56, :291:56] wire _exe_imm_data_i11_T_5 = _exe_imm_data_i11_T_4; // @[util.scala:288:{56,60}] wire _exe_imm_data_i11_T_6 = _exe_imm_data_i11_T_3 ? _exe_imm_data_i11_T_5 : exe_imm_data_sign; // @[util.scala:284:37, :288:{21,36,60}] wire exe_imm_data_i11 = ~_exe_imm_data_i11_T & _exe_imm_data_i11_T_6; // @[util.scala:287:{21,27}, :288:21] wire exe_imm_data_hi_lo_lo = exe_imm_data_i11; // @[util.scala:287:21, :294:15] wire [4:0] _exe_imm_data_i10_5_T_1 = exe_imm_data_ip[18:14]; // @[util.scala:282:17, :289:44] wire [4:0] _exe_imm_data_i10_5_T_2 = _exe_imm_data_i10_5_T_1; // @[util.scala:289:{44,52}] wire [4:0] exe_imm_data_i10_5 = _exe_imm_data_i10_5_T ? 5'h0 : _exe_imm_data_i10_5_T_2; // @[util.scala:289:{21,27,52}] wire [4:0] exe_imm_data_lo_hi_hi = exe_imm_data_i10_5; // @[util.scala:289:21, :294:15] wire [4:0] _exe_imm_data_i4_1_T_1 = exe_imm_data_ip[13:9]; // @[util.scala:282:17, :290:44] wire [4:0] _exe_imm_data_i4_1_T_2 = _exe_imm_data_i4_1_T_1; // @[util.scala:290:{44,51}] wire [4:0] exe_imm_data_i4_1 = _exe_imm_data_i4_1_T ? 5'h0 : _exe_imm_data_i4_1_T_2; // @[util.scala:290:{21,27,51}] wire [4:0] exe_imm_data_lo_hi_lo = exe_imm_data_i4_1; // @[util.scala:290:21, :294:15] wire _exe_imm_data_i0_T = rrd_uop_bits_imm_sel == 3'h1; // @[util.scala:291:27] wire _exe_imm_data_i0_T_1 = rrd_uop_bits_imm_sel == 3'h0; // @[util.scala:291:44] wire _exe_imm_data_i0_T_2 = _exe_imm_data_i0_T | _exe_imm_data_i0_T_1; // @[util.scala:291:{27,36,44}] wire _exe_imm_data_i0_T_4 = _exe_imm_data_i0_T_3; // @[util.scala:291:{56,60}] wire exe_imm_data_i0 = _exe_imm_data_i0_T_2 & _exe_imm_data_i0_T_4; // @[util.scala:291:{21,36,60}] wire exe_imm_data_lo_lo = exe_imm_data_i0; // @[util.scala:291:21, :294:15] wire [9:0] exe_imm_data_lo_hi = {exe_imm_data_lo_hi_hi, exe_imm_data_lo_hi_lo}; // @[util.scala:294:15] wire [10:0] exe_imm_data_lo = {exe_imm_data_lo_hi, exe_imm_data_lo_lo}; // @[util.scala:294:15] wire [8:0] exe_imm_data_hi_lo = {exe_imm_data_hi_lo_hi, exe_imm_data_hi_lo_lo}; // @[util.scala:294:15] wire [11:0] exe_imm_data_hi_hi = {exe_imm_data_hi_hi_hi, exe_imm_data_hi_hi_lo}; // @[util.scala:294:15] wire [20:0] exe_imm_data_hi = {exe_imm_data_hi_hi, exe_imm_data_hi_lo}; // @[util.scala:294:15] wire [31:0] _exe_imm_data_T_4 = {exe_imm_data_hi, exe_imm_data_lo}; // @[util.scala:294:15] wire _exe_imm_data_T_5 = _exe_imm_data_T_4[31]; // @[util.scala:269:46, :294:15] wire [31:0] _exe_imm_data_T_6 = {32{_exe_imm_data_T_5}}; // @[util.scala:269:{25,46}] wire [63:0] _exe_imm_data_T_7 = {_exe_imm_data_T_6, _exe_imm_data_T_4}; // @[util.scala:269:{20,25}, :294:15] wire [63:0] _exe_imm_data_T_8 = _exe_imm_data_T ? _exe_imm_data_T_3 : _exe_imm_data_T_7; // @[util.scala:269:20] reg [63:0] exe_imm_data; // @[execution-unit.scala:170:29] wire [63:0] exe_int_req_imm_data = exe_imm_data; // @[execution-unit.scala:170:29, :357:25] wire _io_squash_iss_T = ~io_arb_irf_reqs_0_ready_0; // @[execution-unit.scala:330:7, :344:50] wire _io_squash_iss_T_1 = io_arb_irf_reqs_0_valid_0 & _io_squash_iss_T; // @[execution-unit.scala:330:7, :344:{47,50}] wire _io_squash_iss_T_2 = ~io_arb_irf_reqs_1_ready_0; // @[execution-unit.scala:330:7, :345:50] wire _io_squash_iss_T_3 = io_arb_irf_reqs_1_valid_0 & _io_squash_iss_T_2; // @[execution-unit.scala:330:7, :345:{47,50}] assign _io_squash_iss_T_4 = _io_squash_iss_T_1 | _io_squash_iss_T_3; // @[execution-unit.scala:344:{47,77}, :345:47] wire _will_replay_T_1 = |_will_replay_T; // @[util.scala:126:{51,59}] wire _will_replay_T_2 = _will_replay_T_1 | io_kill; // @[util.scala:61:61, :126:59] wire _will_replay_T_3 = ~_will_replay_T_2; // @[util.scala:61:61] wire _will_replay_T_4 = arb_uop_valid & _will_replay_T_3; // @[execution-unit.scala:92:20, :348:{37,40}] wire _will_replay_T_5 = ~arb_rebusied; // @[execution-unit.scala:130:45, :348:97] wire will_replay = _will_replay_T_4 & _will_replay_T_5; // @[execution-unit.scala:348:{37,94,97}] wire [11:0] _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] arb_uop_bits_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _arb_uop_bits_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27] assign _arb_uop_bits_out_br_mask_T_3 = arb_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign arb_uop_bits_out_1_br_mask = _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _io_mul_resp_imul_io_req_valid_T = exe_uop_valid & exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20, :369:41] wire _alu_io_req_valid_T = exe_uop_valid & exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20, :386:39] wire _c_valid_T = |exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20, :393:70] wire _c_valid_T_1 = _alu_io_resp_valid & _c_valid_T; // @[execution-unit.scala:385:21, :393:{46,70}] reg [63:0] c_bits_addr_REG; // @[execution-unit.scala:396:27] wire _s_valid_T = exe_uop_valid & exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20, :399:41] wire _s_bits_rs1_T = exe_uop_bits_pimm[0]; // @[execution-unit.scala:98:20, :400:44] wire _s_bits_rs2_T = exe_uop_bits_pimm[1]; // @[execution-unit.scala:98:20, :401:44] reg [63:0] s_bits_addr_REG; // @[execution-unit.scala:402:27] reg [63:0] s_bits_asid_REG; // @[execution-unit.scala:403:27] wire _s_bits_hv_T = exe_uop_bits_mem_cmd == 5'h15; // @[execution-unit.scala:98:20, :404:47] wire _s_bits_hg_T = exe_uop_bits_mem_cmd == 5'h16; // @[execution-unit.scala:98:20, :405:47] wire io_ifpu_resp_ifpu_ready; // @[execution-unit.scala:434:26] assign r_8 = io_ifpu_resp_ifpu_ready; // @[execution-unit.scala:74:21, :434:26] wire _io_ifpu_resp_ifpu_io_req_valid_T = exe_uop_valid & exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20, :438:41] wire [2:0] _io_ifpu_resp_ifpu_io_req_bits_uop_fp_rm_T = exe_uop_bits_prs2[4:2]; // @[execution-unit.scala:98:20, :440:53] wire [1:0] _io_ifpu_resp_ifpu_io_req_bits_uop_fp_typ_T = exe_uop_bits_prs2[1:0]; // @[execution-unit.scala:98:20, :441:53] wire _io_ifpu_resp_T = ~_io_ifpu_resp_queue_io_enq_ready; // @[execution-unit.scala:447:23, :452:37] wire _io_ifpu_resp_T_1 = _io_ifpu_resp_ifpu_io_resp_valid & _io_ifpu_resp_T; // @[execution-unit.scala:437:22, :452:{34,37}] wire _io_ifpu_resp_T_2 = ~_io_ifpu_resp_T_1; // @[execution-unit.scala:452:{13,34}] wire _io_ifpu_resp_T_4 = ~_io_ifpu_resp_T_3; // @[execution-unit.scala:452:12] wire _io_ifpu_resp_T_5 = ~_io_ifpu_resp_T_2; // @[execution-unit.scala:452:{12,13}] wire _io_ifpu_resp_ifpu_ready_T = _io_ifpu_resp_queue_io_count < 3'h2; // @[execution-unit.scala:447:23, :453:42] reg io_ifpu_resp_ifpu_ready_REG; // @[execution-unit.scala:453:26] assign io_ifpu_resp_ifpu_ready = io_ifpu_resp_ifpu_ready_REG; // @[execution-unit.scala:434:26, :453:26] wire _io_div_resp_div_ready_T_8; // @[execution-unit.scala:476:56] wire io_div_resp_div_ready; // @[execution-unit.scala:464:25] assign r_4 = io_div_resp_div_ready; // @[execution-unit.scala:74:21, :464:25] wire _io_div_resp_T = ~_io_div_resp_div_io_req_ready; // @[execution-unit.scala:467:21, :468:34] wire _io_div_resp_div_io_req_valid_T; // @[execution-unit.scala:469:39] wire _io_div_resp_T_1 = _io_div_resp_div_io_req_valid_T & _io_div_resp_T; // @[execution-unit.scala:468:{31,34}, :469:39] wire _io_div_resp_T_2 = ~_io_div_resp_T_1; // @[execution-unit.scala:468:{12,31}] wire _io_div_resp_T_4 = ~_io_div_resp_T_3; // @[execution-unit.scala:468:11] wire _io_div_resp_T_5 = ~_io_div_resp_T_2; // @[execution-unit.scala:468:{11,12}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File INToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val signedIn = Input(Bool()) val in = Input(Bits(intWidth.W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in); val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( intAsRawFloat.expWidth, intWidth, expWidth, sigWidth, flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows )) roundAnyRawFNToRecFN.io.invalidExc := false.B roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := intAsRawFloat roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File rawFloatFromIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object rawFloatFromIN { def apply(signedIn: Bool, in: Bits): RawFloat = { val expWidth = log2Up(in.getWidth) + 1 //*** CHANGE THIS; CAN BE VERY LARGE: val extIntWidth = 1<<(expWidth - 1) val sign = signedIn && in(in.getWidth - 1) val absIn = Mux(sign, -in.asUInt, in.asUInt) val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) val adjustedNormDist = countLeadingZeros(extAbsIn) val sig = (extAbsIn<<adjustedNormDist)( extIntWidth - 1, extIntWidth - in.getWidth) val out = Wire(new RawFloat(expWidth, in.getWidth)) out.isNaN := false.B out.isInf := false.B out.isZero := ! sig(in.getWidth - 1) out.sign := sign out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext out.sig := sig out } }
module INToRecFN_i1_e8_s24_13(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_13 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_53( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_53 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File lsu.scala: //****************************************************************************** // Copyright (c) 2012 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Out-of-Order Load/Store Unit //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ). // // Stores are sent to memory at (well, after) commit, loads are executed // optimstically ASAP. If a misspeculation was discovered, the pipeline is // cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match, // the Load can receive its data by forwarding data out of the Store Queue. // // Currently, loads are sent to memory immediately, and in parallel do an // associative search of the STQ, on entering the LSU. If a hit on the STQ // search, the memory request is killed on the next cycle, and if the STQ entry // is valid, the store data is forwarded to the load (delayed to match the // load-use delay to delay with the write-port structural hazard). If the store // data is not present, or it's only a partial match (SB->LH), the load is put // to sleep in the LDQ. // // Memory ordering violations are detected by stores at their addr-gen time by // associatively searching the LDQ for newer loads that have been issued to // memory. // // The store queue contains both speculated and committed stores. // // Only one port to memory... loads and stores have to fight for it, West Side // Story style. // // TODO: // - Add predicting structure for ordering failures // - currently won't STD forward if DMEM is busy // - ability to turn off things if VM is disabled // - reconsider port count of the wakeup, retry stuff package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.Str import boom.v3.common._ import boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp} import boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask} class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p) { // The "resp" of the maddrcalc is really a "req" to the LSU val req = Flipped(new ValidIO(new FuncUnitResp(xLen))) // Send load data to regfiles val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen)) val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen? } class BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = UInt(coreMaxAddrBits.W) val data = Bits(coreDataBits.W) val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ } class BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val data = Bits(coreDataBits.W) val is_hella = Bool() } class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { // In LSU's dmem stage, send the request val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq))) // In LSU's LCAM search stage, kill if order fail (or forwarding possible) val s1_kill = Output(Vec(memWidth, Bool())) // Get a request any cycle val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp))) // In our response stage, if we get a nack, we need to reexecute val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq))) val brupdate = Output(new BrUpdateInfo) val exception = Output(Bool()) val rob_pnr_idx = Output(UInt(robAddrSz.W)) val rob_head_idx = Output(UInt(robAddrSz.W)) val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle))) // Clears prefetching MSHRs val force_order = Output(Bool()) val ordered = Input(Bool()) val perf = Input(new Bundle { val acquire = Bool() val release = Bool() }) } class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p) { val exe = Vec(memWidth, new LSUExeIO) val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp))) val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W))) val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W))) val ldq_full = Output(Vec(coreWidth, Bool())) val stq_full = Output(Vec(coreWidth, Bool())) val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen))) val commit = Input(new CommitSignals) val commit_load_at_rob_head = Input(Bool()) // Stores clear busy bit when stdata is received // memWidth for int, 1 for fp (to avoid back-pressure fpstdat) val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W)))) // Speculatively safe load (barring memory ordering failure) val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W)))) // Tell the DCache to clear prefetches/speculating misses val fence_dmem = Input(Bool()) // Speculatively tell the IQs that we'll get load data back next cycle val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W)))) // Tell the IQs that the load we speculated last cycle was misspeculated val ld_miss = Output(Bool()) val brupdate = Input(new BrUpdateInfo) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val exception = Input(Bool()) val fencei_rdy = Output(Bool()) val lxcpt = Output(Valid(new Exception)) val tsc_reg = Input(UInt()) val perf = Output(new Bundle { val acquire = Bool() val release = Bool() val tlbMiss = Bool() }) } class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val ptw = new rocket.TLBPTWIO val core = new LSUCoreIO val dmem = new LSUDMemIO val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO) } class LDQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute val executed = Bool() // load sent to memory, reset by NACKs val succeeded = Bool() val order_fail = Bool() val observed = Bool() val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us val forward_std_val = Bool() val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from? val debug_wb_data = UInt(xLen.W) } class STQEntry(implicit p: Parameters) extends BoomBundle()(p) with HasBoomUOP { val addr = Valid(UInt(coreMaxAddrBits.W)) val addr_is_virtual = Bool() // Virtual address, we got a TLB miss val data = Valid(UInt(xLen.W)) val committed = Bool() // committed by ROB val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore val debug_wb_data = UInt(xLen.W) } class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p) with rocket.HasL1HellaCacheParameters { val io = IO(new LSUIO) io.hellacache := DontCare val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry))) val stq = Reg(Vec(numStqEntries, Valid(new STQEntry))) val ldq_head = Reg(UInt(ldqAddrSz.W)) val ldq_tail = Reg(UInt(ldqAddrSz.W)) val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory) val stq_tail = Reg(UInt(stqAddrSz.W)) val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute // If we got a mispredict, the tail will be misaligned for 1 extra cycle assert (io.core.brupdate.b2.mispredict || stq(stq_execute_head).valid || stq_head === stq_execute_head || stq_tail === stq_execute_head, "stq_execute_head got off track.") val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7) // s1 : do TLB, if success and not killed, fire request go to h_s2 // store s1_data to register // if tlb miss, go to s2_nack // if don't get TLB, go to s2_nack // store tlb xcpt // s2 : If kill, go to dead // If tlb xcpt, send tlb xcpt, go to dead // s2_nack : send nack, go to dead // wait : wait for response, if nack, go to replay // replay : refire request, use already translated address // dead : wait for response, ignore it val hella_state = RegInit(h_ready) val hella_req = Reg(new rocket.HellaCacheReq) val hella_data = Reg(new rocket.HellaCacheWriteData) val hella_paddr = Reg(UInt(paddrBits.W)) val hella_xcpt = Reg(new rocket.HellaCacheExceptions) val dtlb = Module(new NBDTLB( instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays))) io.ptw <> dtlb.io.ptw io.core.perf.tlbMiss := io.ptw.req.fire io.core.perf.acquire := io.dmem.perf.acquire io.core.perf.release := io.dmem.perf.release val clear_store = WireInit(false.B) val live_store_mask = RegInit(0.U(numStqEntries.W)) var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head), live_store_mask) def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) //------------------------------------------------------------- //------------------------------------------------------------- // Enqueue new entries //------------------------------------------------------------- //------------------------------------------------------------- // This is a newer store than existing loads, so clear the bit in all the store dependency masks for (i <- 0 until numLdqEntries) { when (clear_store) { ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head) } } // Decode stage var ld_enq_idx = ldq_tail var st_enq_idx = stq_tail val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U var ldq_full = Bool() var stq_full = Bool() for (w <- 0 until coreWidth) { ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head io.core.ldq_full(w) := ldq_full io.core.dis_ldq_idx(w) := ld_enq_idx stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head io.core.stq_full(w) := stq_full io.core.dis_stq_idx(w) := st_enq_idx val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception when (dis_ld_val) { ldq(ld_enq_idx).valid := true.B ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask ldq(ld_enq_idx).bits.addr.valid := false.B ldq(ld_enq_idx).bits.executed := false.B ldq(ld_enq_idx).bits.succeeded := false.B ldq(ld_enq_idx).bits.order_fail := false.B ldq(ld_enq_idx).bits.observed := false.B ldq(ld_enq_idx).bits.forward_std_val := false.B assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, "[lsu] mismatch enq load tag.") assert (!ldq(ld_enq_idx).valid, "[lsu] Enqueuing uop is overwriting ldq entries") } .elsewhen (dis_st_val) { stq(st_enq_idx).valid := true.B stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits stq(st_enq_idx).bits.addr.valid := false.B stq(st_enq_idx).bits.data.valid := false.B stq(st_enq_idx).bits.committed := false.B stq(st_enq_idx).bits.succeeded := false.B assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, "[lsu] mismatch enq store tag.") assert (!stq(st_enq_idx).valid, "[lsu] Enqueuing uop is overwriting stq entries") } ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries), ld_enq_idx) next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx), next_live_store_mask) st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries), st_enq_idx) assert(!(dis_ld_val && dis_st_val), "A UOP is trying to go into both the LDQ and the STQ") } ldq_tail := ld_enq_idx stq_tail := st_enq_idx io.dmem.force_order := io.core.fence_dmem io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered //------------------------------------------------------------- //------------------------------------------------------------- // Execute stage (access TLB, send requests to Memory) //------------------------------------------------------------- //------------------------------------------------------------- // We can only report 1 exception per cycle. // Just be sure to report the youngest one val mem_xcpt_valid = Wire(Bool()) val mem_xcpt_cause = Wire(UInt()) val mem_xcpt_uop = Wire(new MicroOp) val mem_xcpt_vaddr = Wire(UInt()) //--------------------------------------- // Can-fire logic and wakeup/retry select // // First we determine what operations are waiting to execute. // These are the "can_fire"/"will_fire" signals val will_fire_load_incoming = Wire(Vec(memWidth, Bool())) val will_fire_stad_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sta_incoming = Wire(Vec(memWidth, Bool())) val will_fire_std_incoming = Wire(Vec(memWidth, Bool())) val will_fire_sfence = Wire(Vec(memWidth, Bool())) val will_fire_hella_incoming = Wire(Vec(memWidth, Bool())) val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool())) val will_fire_release = Wire(Vec(memWidth, Bool())) val will_fire_load_retry = Wire(Vec(memWidth, Bool())) val will_fire_sta_retry = Wire(Vec(memWidth, Bool())) val will_fire_store_commit = Wire(Vec(memWidth, Bool())) val will_fire_load_wakeup = Wire(Vec(memWidth, Bool())) val exe_req = WireInit(VecInit(io.core.exe.map(_.req))) // Sfence goes through all pipes for (i <- 0 until memWidth) { when (io.core.exe(i).req.bits.sfence.valid) { exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req }) } } // ------------------------------- // Assorted signals for scheduling // Don't wakeup a load if we just sent it last cycle or two cycles ago // The block_load_mask may be wrong, but the executing_load mask must be accurate val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) val p1_block_load_mask = RegNext(block_load_mask) val p2_block_load_mask = RegNext(p1_block_load_mask) // Prioritize emptying the store queue when it is almost full val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head || WrapInc(st_enq_idx, numStqEntries) === stq_head) // The store at the commit head needs the DCache to appear ordered // Delay firing load wakeups and retries now val store_needs_order = WireInit(false.B) val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx) val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i))) val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx) val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i))) val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && e.addr_is_virtual && !block }), ldq_head)) val ldq_retry_e = ldq(ldq_retry_idx) val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => { val e = stq(i).bits e.addr.valid && e.addr_is_virtual }), stq_commit_head)) val stq_retry_e = stq(stq_retry_idx) val stq_commit_e = stq(stq_execute_head) val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> { val e = ldq(i).bits val block = block_load_mask(i) || p1_block_load_mask(i) e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block }), ldq_head)) val ldq_wakeup_e = ldq(ldq_wakeup_idx) // ----------------------- // Determine what can fire // Can we fire a incoming load val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load) // Can we fire an incoming store addrgen + store datagen val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store addrgen val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta && !exe_req(w).bits.uop.ctrl.is_std) // Can we fire an incoming store datagen val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std && !exe_req(w).bits.uop.ctrl.is_sta) // Can we fire an incoming sfence val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid) // Can we fire a request from dcache to release a line // This needs to go through LDQ search to mark loads as dangerous val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid) io.dmem.release.ready := will_fire_release.reduce(_||_) // Can we retry a load that missed in the TLB val can_fire_load_retry = widthMap(w => ( ldq_retry_e.valid && ldq_retry_e.bits.addr.valid && ldq_retry_e.bits.addr_is_virtual && !p1_block_load_mask(ldq_retry_idx) && !p2_block_load_mask(ldq_retry_idx) && RegNext(dtlb.io.miss_rdy) && !store_needs_order && (w == memWidth-1).B && // TODO: Is this best scheduling? !ldq_retry_e.bits.order_fail)) // Can we retry a store addrgen that missed in the TLB // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this val can_fire_sta_retry = widthMap(w => ( stq_retry_e.valid && stq_retry_e.bits.addr.valid && stq_retry_e.bits.addr_is_virtual && (w == memWidth-1).B && RegNext(dtlb.io.miss_rdy) && !(widthMap(i => (i != w).B && can_fire_std_incoming(i) && stq_incoming_idx(i) === stq_retry_idx).reduce(_||_)) )) // Can we commit a store val can_fire_store_commit = widthMap(w => ( stq_commit_e.valid && !stq_commit_e.bits.uop.is_fence && !mem_xcpt_valid && !stq_commit_e.bits.uop.exception && (w == 0).B && (stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo && stq_commit_e.bits.addr.valid && !stq_commit_e.bits.addr_is_virtual && stq_commit_e.bits.data.valid)))) // Can we wakeup a load that was nack'd val block_load_wakeup = WireInit(false.B) val can_fire_load_wakeup = widthMap(w => ( ldq_wakeup_e.valid && ldq_wakeup_e.bits.addr.valid && !ldq_wakeup_e.bits.succeeded && !ldq_wakeup_e.bits.addr_is_virtual && !ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.order_fail && !p1_block_load_mask(ldq_wakeup_idx) && !p2_block_load_mask(ldq_wakeup_idx) && !store_needs_order && !block_load_wakeup && (w == memWidth-1).B && (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head && ldq_head === ldq_wakeup_idx && ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U)))) // Can we fire an incoming hellacache request val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller // Can we fire a hellacache request that the dcache nack'd val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller //--------------------------------------------------------- // Controller logic. Arbitrate which request actually fires val exe_tlb_valid = Wire(Vec(memWidth, Bool())) for (w <- 0 until memWidth) { var tlb_avail = true.B var dc_avail = true.B var lcam_avail = true.B var rob_avail = true.B def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = { val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) && !(uses_lcam.B && !lcam_avail) && !(uses_dc.B && !dc_avail) && !(uses_rob.B && !rob_avail) tlb_avail = tlb_avail && !(will_fire && uses_tlb.B) lcam_avail = lcam_avail && !(will_fire && uses_lcam.B) dc_avail = dc_avail && !(will_fire && uses_dc.B) rob_avail = rob_avail && !(will_fire && uses_rob.B) dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals will_fire } // The order of these statements is the priority // Some restrictions // - Incoming ops must get precedence, can't backpresure memaddrgen // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation) // Notes on performance // - Prioritize releases, this speeds up cache line writebacks and refills // - Store commits are lowest priority, since they don't "block" younger instructions unless stq fills up will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1 will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w)))) when (will_fire_load_wakeup(w)) { block_load_mask(ldq_wakeup_idx) := true.B } .elsewhen (will_fire_load_incoming(w)) { block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B } .elsewhen (will_fire_load_retry(w)) { block_load_mask(ldq_retry_idx) := true.B } exe_tlb_valid(w) := !tlb_avail } assert((memWidth == 1).B || (!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) && !will_fire_hella_incoming.reduce(_&&_) && !will_fire_hella_wakeup.reduce(_&&_) && !will_fire_load_retry.reduce(_&&_) && !will_fire_sta_retry.reduce(_&&_) && !will_fire_store_commit.reduce(_&&_) && !will_fire_load_wakeup.reduce(_&&_)), "Some operations is proceeding down multiple pipes") require(memWidth <= 2) //-------------------------------------------- // TLB Access assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE), "SFENCE through hella interface not supported") val exe_tlb_uop = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) , exe_req(w).bits.uop, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop, Mux(will_fire_hella_incoming(w) , NullMicroOp, NullMicroOp))))) val exe_tlb_vaddr = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) , exe_req(w).bits.addr, Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr, Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits, Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits, Mux(will_fire_hella_incoming(w) , hella_req.addr, 0.U)))))) val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq))) for (w <- 0 until memWidth) { when (will_fire_sfence(w)) { exe_sfence := exe_req(w).bits.sfence } } val exe_size = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size, Mux(will_fire_hella_incoming(w) , hella_req.size, 0.U))) val exe_cmd = widthMap(w => Mux(will_fire_load_incoming (w) || will_fire_stad_incoming (w) || will_fire_sta_incoming (w) || will_fire_sfence (w) || will_fire_load_retry (w) || will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd, Mux(will_fire_hella_incoming(w) , hella_req.cmd, 0.U))) val exe_passthr= widthMap(w => Mux(will_fire_hella_incoming(w) , hella_req.phys, false.B)) val exe_kill = widthMap(w => Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill, false.B)) for (w <- 0 until memWidth) { dtlb.io.req(w).valid := exe_tlb_valid(w) dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w) dtlb.io.req(w).bits.size := exe_size(w) dtlb.io.req(w).bits.cmd := exe_cmd(w) dtlb.io.req(w).bits.passthrough := exe_passthr(w) dtlb.io.req(w).bits.v := io.ptw.status.v dtlb.io.req(w).bits.prv := io.ptw.status.prv } dtlb.io.kill := exe_kill.reduce(_||_) dtlb.io.sfence := exe_sfence // exceptions val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq) val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq) val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq) val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq) // TODO check for xcpt_if and verify that never happens on non-speculative instructions. val mem_xcpt_valids = RegNext(widthMap(w => (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w)))) val mem_xcpt_causes = RegNext(widthMap(w => Mux(ma_ld(w), rocket.Causes.misaligned_load.U, Mux(ma_st(w), rocket.Causes.misaligned_store.U, Mux(pf_ld(w), rocket.Causes.load_page_fault.U, Mux(pf_st(w), rocket.Causes.store_page_fault.U, Mux(ae_ld(w), rocket.Causes.load_access.U, rocket.Causes.store_access.U))))))) val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr) for (w <- 0 until memWidth) { assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), "Fence is pretending to talk to the TLB") assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid && !(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)), "A uop that's not a load or store-address is throwing a memory exception.") } mem_xcpt_valid := mem_xcpt_valids.reduce(_||_) mem_xcpt_cause := mem_xcpt_causes(0) mem_xcpt_uop := mem_xcpt_uops(0) mem_xcpt_vaddr := mem_xcpt_vaddrs(0) var xcpt_found = mem_xcpt_valids(0) var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx for (w <- 1 until memWidth) { val is_older = WireInit(false.B) when (mem_xcpt_valids(w) && (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) { is_older := true.B mem_xcpt_cause := mem_xcpt_causes(w) mem_xcpt_uop := mem_xcpt_uops(w) mem_xcpt_vaddr := mem_xcpt_vaddrs(w) } xcpt_found = xcpt_found || mem_xcpt_valids(w) oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx) } val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready)) val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits), exe_tlb_vaddr(w)(corePgIdxBits-1,0))) val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable)) for (w <- 0 until memWidth) { assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, "[lsu] paddrs should match.") when (mem_xcpt_valids(w)) { assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_load_retry(w) || will_fire_sta_retry(w))) // Technically only faulting AMOs need this assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq) when (mem_xcpt_uops(w).uses_ldq) { ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B } .otherwise { stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B } } } //------------------------------ // Issue Someting to Memory // // A memory op can come from many different places // The address either was freshly translated, or we are // reading a physical address from the LDQ,STQ, or the HellaCache adapter // defaults io.dmem.brupdate := io.core.brupdate io.dmem.exception := io.core.exception io.dmem.rob_head_idx := io.core.rob_head_idx io.dmem.rob_pnr_idx := io.core.rob_pnr_idx val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq))) io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_) io.dmem.req.bits := dmem_req val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire) val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) for (w <- 0 until memWidth) { dmem_req(w).valid := false.B dmem_req(w).bits.uop := NullMicroOp dmem_req(w).bits.addr := 0.U dmem_req(w).bits.data := 0.U dmem_req(w).bits.is_hella := false.B io.dmem.s1_kill(w) := false.B when (will_fire_load_incoming(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w) assert(!ldq_incoming_e(w).bits.executed) } .elsewhen (will_fire_load_retry(w)) { dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.uop := exe_tlb_uop(w) s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w) assert(!ldq_retry_e.bits.executed) } .elsewhen (will_fire_store_commit(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( stq_commit_e.bits.uop.mem_size, 0.U, stq_commit_e.bits.data.bits, coreDataBytes)).data dmem_req(w).bits.uop := stq_commit_e.bits.uop stq_execute_head := Mux(dmem_req_fire(w), WrapInc(stq_execute_head, numStqEntries), stq_execute_head) stq(stq_execute_head).bits.succeeded := false.B } .elsewhen (will_fire_load_wakeup(w)) { dmem_req(w).valid := true.B dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w) assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual) } .elsewhen (will_fire_hella_incoming(w)) { assert(hella_state === h_s1) dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys) dmem_req(w).bits.addr := exe_tlb_paddr(w) dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, io.hellacache.s1_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B hella_paddr := exe_tlb_paddr(w) } .elsewhen (will_fire_hella_wakeup(w)) { assert(hella_state === h_replay) dmem_req(w).valid := true.B dmem_req(w).bits.addr := hella_paddr dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen( hella_req.size, 0.U, hella_data.data, coreDataBytes)).data dmem_req(w).bits.uop.mem_cmd := hella_req.cmd dmem_req(w).bits.uop.mem_size := hella_req.size dmem_req(w).bits.uop.mem_signed := hella_req.signed dmem_req(w).bits.is_hella := true.B } //------------------------------------------------------------- // Write Addr into the LAQ/SAQ when (will_fire_load_incoming(w) || will_fire_load_retry(w)) { val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx) ldq(ldq_idx).bits.addr.valid := true.B ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w) ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w) assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid), "[lsu] Incoming load is overwriting a valid address") } when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w)) { val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), stq_retry_idx) stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing! stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w)) stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w) assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid), "[lsu] Incoming store is overwriting a valid address") } //------------------------------------------------------------- // Write data into the STQ if (w == 0) io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w) val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire) { val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), stq_incoming_idx(w), io.core.fp_stdata.bits.uop.stq_idx) stq(sidx).bits.data.valid := true.B stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w), exe_req(w).bits.data, io.core.fp_stdata.bits.data) assert(!(stq(sidx).bits.data.valid), "[lsu] Incoming store is overwriting a valid data entry") } } val will_fire_stdf_incoming = io.core.fp_stdata.fire require (xLen >= fLen) // for correct SDQ size //------------------------------------------------------------- //------------------------------------------------------------- // Cache Access Cycle (Mem) //------------------------------------------------------------- //------------------------------------------------------------- // Note the DCache may not have accepted our request val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop)) val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop) val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w))) val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w))) val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w))) val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w))) val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed) val fired_sfence = RegNext(will_fire_sfence) val fired_release = RegNext(will_fire_release) val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop))) val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop))) val fired_store_commit = RegNext(will_fire_store_commit) val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop))) val fired_hella_incoming = RegNext(will_fire_hella_incoming) val fired_hella_wakeup = RegNext(will_fire_hella_wakeup) val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop))) val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w)))) val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w)))) val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e)) val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e)) val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e)) val mem_ldq_e = widthMap(w => Mux(fired_load_incoming(w), mem_ldq_incoming_e(w), Mux(fired_load_retry (w), mem_ldq_retry_e, Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry)))))) val mem_stq_e = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_stq_incoming_e(w), Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry))))) val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop)) val mem_tlb_miss = RegNext(exe_tlb_miss) val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable) val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr)) // Task 1: Clr ROB busy bit val clr_bsy_valid = RegInit(widthMap(w => false.B)) val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W))) val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W))) for (w <- 0 until memWidth) { clr_bsy_valid (w) := false.B clr_bsy_rob_idx (w) := 0.U clr_bsy_brmask (w) := 0.U when (fired_stad_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sta_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.data.valid && !mem_tlb_miss(w) && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_std_incoming(w)) { clr_bsy_valid (w) := mem_stq_incoming_e(w).valid && mem_stq_incoming_e(w).bits.addr.valid && !mem_stq_incoming_e(w).bits.addr_is_virtual && !mem_stq_incoming_e(w).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop) } .elsewhen (fired_sfence(w)) { clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w)) } .elsewhen (fired_sta_retry(w)) { clr_bsy_valid (w) := mem_stq_retry_e.valid && mem_stq_retry_e.bits.data.valid && !mem_tlb_miss(w) && !mem_stq_retry_e.bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop) clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop) } io.core.clr_bsy(w).valid := clr_bsy_valid(w) && !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w) } val stdf_clr_bsy_valid = RegInit(false.B) val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W)) val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W)) stdf_clr_bsy_valid := false.B stdf_clr_bsy_rob_idx := 0.U stdf_clr_bsy_brmask := 0.U when (fired_stdf_incoming) { val s_idx = mem_stdf_uop.stq_idx stdf_clr_bsy_valid := stq(s_idx).valid && stq(s_idx).bits.addr.valid && !stq(s_idx).bits.addr_is_virtual && !stq(s_idx).bits.uop.is_amo && !IsKilledByBranch(io.core.brupdate, mem_stdf_uop) stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop) } io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid && !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) && !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception)) io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx // Task 2: Do LD-LD. ST-LD searches for ordering failures // Do LD-ST search for forwarding opportunities // We have the opportunity to kill a request we sent last cycle. Use it wisely! // We translated a store last cycle val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w)) // We translated a load last cycle val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) || fired_load_wakeup(w)) // We are making a local line visible to other harts val do_release_search = widthMap(w => fired_release(w)) // Store addrs don't go to memory yet, get it from the TLB response // Load wakeups don't go through TLB, get it through memory // Load incoming and load retries go through both val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w), RegNext(exe_tlb_paddr(w)), Mux(fired_release(w), RegNext(io.dmem.release.bits.address), mem_paddr(w)))) val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop, Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp))) val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size)) val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask) val lcam_is_release = widthMap(w => fired_release(w)) val lcam_ldq_idx = widthMap(w => Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx, Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx), Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U)))) val lcam_stq_idx = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming (w), mem_incoming_uop(w).stq_idx, Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U))) val can_forward = WireInit(widthMap(w => Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w), !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable))) // Mask of stores which we conflict on address with val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) // Mask of stores which we can forward from val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B)))) val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception) val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage val s1_executing_loads = RegNext(s0_executing_loads) val s1_set_execute = WireInit(s1_executing_loads) val mem_forward_valid = Wire(Vec(memWidth, Bool())) val mem_forward_ldq_idx = lcam_ldq_idx val mem_forward_ld_addr = lcam_addr val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W))) val wb_forward_valid = RegNext(mem_forward_valid) val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx) val wb_forward_ld_addr = RegNext(mem_forward_ld_addr) val wb_forward_stq_idx = RegNext(mem_forward_stq_idx) for (i <- 0 until numLdqEntries) { val l_valid = ldq(i).valid val l_bits = ldq(i).bits val l_addr = ldq(i).bits.addr.bits val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size) val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U) val l_is_forwarding = l_forwarders.reduce(_||_) val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx) val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits) val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3)) val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask) val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR) // Searcher is a store for (w <- 0 until memWidth) { when (do_release_search(w) && l_valid && l_bits.addr.valid && block_addr_matches(w)) { // This load has been observed, so if a younger load to the same address has not // executed yet, this load must be squashed ldq(i).bits.observed := true.B } .elsewhen (do_st_search(w) && l_valid && l_bits.addr.valid && (l_bits.executed || l_bits.succeeded || l_is_forwarding) && !l_bits.addr_is_virtual && l_bits.st_dep_mask(lcam_stq_idx(w)) && dword_addr_matches(w) && mask_overlap(w)) { val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx) // We are older than this load, which overlapped us. when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (do_ld_search(w) && l_valid && l_bits.addr.valid && !l_bits.addr_is_virtual && dword_addr_matches(w) && mask_overlap(w)) { val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head) when (searcher_is_older) { when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) && !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us ldq(i).bits.order_fail := true.B failed_loads(i) := true.B } } .elsewhen (lcam_ldq_idx(w) =/= i.U) { // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response // we need to kill ourselves, and prevent forwarding val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i)) when (!(l_bits.executed || l_bits.succeeded) || older_nacked) { s1_set_execute(lcam_ldq_idx(w)) := false.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) can_forward(w) := false.B } } } } } for (i <- 0 until numStqEntries) { val s_addr = stq(i).bits.addr.bits val s_uop = stq(i).bits.uop val dword_addr_matches = widthMap(w => ( stq(i).bits.addr.valid && !stq(i).bits.addr_is_virtual && (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3)))) val write_mask = GenByteMask(s_addr, s_uop.mem_size) for (w <- 0 until memWidth) { when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) { when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w)) { ldst_addr_matches(w)(i) := true.B ldst_forward_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w)) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } .elsewhen (s_uop.is_fence || s_uop.is_amo) { ldst_addr_matches(w)(i) := true.B io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w)) s1_set_execute(lcam_ldq_idx(w)) := false.B } } } } // Set execute bit in LDQ for (i <- 0 until numLdqEntries) { when (s1_set_execute(i)) { ldq(i).bits.executed := true.B } } // Find the youngest store which the load is dependent on val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) } for (w <- 0 until memWidth) { forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx } val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx) // Forward if st-ld forwarding is possible from the writemask and loadmask mem_forward_valid := widthMap(w => (ldst_forward_matches(w)(forwarding_idx(w)) && !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) && !io.core.exception && !RegNext(io.core.exception))) mem_forward_stq_idx := forwarding_idx // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits // On a 2W machine, load wakeups and store commits occupy separate pipelines, // so only add this logic for 1-w LSU if (memWidth == 1) { // Wakeups may repeatedly find a st->ld addr conflict and fail to forward, // repeated wakeups may block the store from ever committing // Disallow load wakeups 1 cycle after this happens to allow the stores to drain when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) { block_load_wakeup := true.B } // If stores remain blocked for 15 cycles, block load wakeups to get a store through val store_blocked_counter = Reg(UInt(4.W)) when (will_fire_store_commit(0) || !can_fire_store_commit(0)) { store_blocked_counter := 0.U } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) { store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U) } when (store_blocked_counter === 15.U) { block_load_wakeup := true.B } } // Task 3: Clr unsafe bit in ROB for succesful translations // Delay this a cycle to avoid going ahead of the exception broadcast // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups for (w <- 0 until memWidth) { io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx) } // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load // TODO encapsulate this in an age-based priority-encoder // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head) // ++ failed_loads)).asUInt) val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt val l_idx = PriorityEncoder(temp_bits) // one exception port, but multiple causes! // - 1) the incoming store-address finds a faulting load (it is by definition younger) // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent. val r_xcpt_valid = RegInit(false.B) val r_xcpt = Reg(new Exception) val ld_xcpt_valid = failed_loads.reduce(_|_) val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) && !io.core.exception && !IsKilledByBranch(io.core.brupdate, xcpt_uop) r_xcpt.uop := xcpt_uop r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop) r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING) r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead? io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop) io.core.lxcpt.bits := r_xcpt // Task 4: Speculatively wakeup loads 1 cycle before they come back for (w <- 0 until memWidth) { io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B && fired_load_incoming(w) && !mem_incoming_uop(w).fp_val && mem_incoming_uop(w).pdst =/= 0.U io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst } //------------------------------------------------------------- //------------------------------------------------------------- // Writeback Cycle (St->Ld Forwarding Path) //------------------------------------------------------------- //------------------------------------------------------------- // Handle Memory Responses and nacks //---------------------------------- for (w <- 0 until memWidth) { io.core.exe(w).iresp.valid := false.B io.core.exe(w).iresp.bits := DontCare io.core.exe(w).fresp.valid := false.B io.core.exe(w).fresp.bits := DontCare } val dmem_resp_fired = WireInit(widthMap(w => false.B)) for (w <- 0 until memWidth) { // Handle nacks when (io.dmem.nack(w).valid) { // We have to re-execute this! when (io.dmem.nack(w).bits.is_hella) { assert(hella_state === h_wait || hella_state === h_dead) } .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq) { assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed) ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B } .otherwise { assert(io.dmem.nack(w).bits.uop.uses_stq) when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) { stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx } } } // Handle the response when (io.dmem.resp(w).valid) { when (io.dmem.resp(w).bits.uop.uses_ldq) { assert(!io.dmem.resp(w).bits.is_hella) val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop io.core.exe(w).iresp.valid := send_iresp io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data io.core.exe(w).fresp.valid := send_fresp io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data assert(send_iresp ^ send_fresp) dmem_resp_fired(w) := true.B ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.resp(w).bits.uop.uses_stq) { assert(!io.dmem.resp(w).bits.is_hella) stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B when (io.dmem.resp(w).bits.uop.is_amo) { dmem_resp_fired(w) := true.B io.core.exe(w).iresp.valid := true.B io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data } } } when (dmem_resp_fired(w) && wb_forward_valid(w)) { // Twiddle thumbs. Can't forward because dcache response takes precedence } .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w)) { val f_idx = wb_forward_ldq_idx(w) val forward_uop = ldq(f_idx).bits.uop val stq_e = stq(wb_forward_stq_idx(w)) val data_ready = stq_e.bits.data.valid val live = !IsKilledByBranch(io.core.brupdate, forward_uop) val storegen = new freechips.rocketchip.rocket.StoreGen( stq_e.bits.uop.mem_size, stq_e.bits.addr.bits, stq_e.bits.data.bits, coreDataBytes) val loadgen = new freechips.rocketchip.rocket.LoadGen( forward_uop.mem_size, forward_uop.mem_signed, wb_forward_ld_addr(w), storegen.data, false.B, coreDataBytes) io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live io.core.exe(w).iresp.bits.uop := forward_uop io.core.exe(w).fresp.bits.uop := forward_uop io.core.exe(w).iresp.bits.data := loadgen.data io.core.exe(w).fresp.bits.data := loadgen.data when (data_ready && live) { ldq(f_idx).bits.succeeded := data_ready ldq(f_idx).bits.forward_std_val := true.B ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w) ldq(f_idx).bits.debug_wb_data := loadgen.data } } } // Initially assume the speculative load wakeup failed io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_)) val spec_ld_succeed = widthMap(w => !RegNext(io.core.spec_ld_wakeup(w).valid) || (io.core.exe(w).iresp.valid && io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx) ) ).reduce(_&&_) when (spec_ld_succeed) { io.core.ld_miss := false.B } //------------------------------------------------------------- // Kill speculated entries on branch mispredict //------------------------------------------------------------- //------------------------------------------------------------- // Kill stores val st_brkilled_mask = Wire(Vec(numStqEntries, Bool())) for (i <- 0 until numStqEntries) { st_brkilled_mask(i) := false.B when (stq(i).valid) { stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop)) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_brkilled_mask(i) := true.B } } assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed), "Branch is trying to clear a committed store.") } // Kill loads for (i <- 0 until numLdqEntries) { when (ldq(i).valid) { ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask) when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop)) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B } } } //------------------------------------------------------------- when (io.core.brupdate.b2.mispredict && !io.core.exception) { stq_tail := io.core.brupdate.b2.uop.stq_idx ldq_tail := io.core.brupdate.b2.uop.ldq_idx } //------------------------------------------------------------- //------------------------------------------------------------- // dequeue old entries on commit //------------------------------------------------------------- //------------------------------------------------------------- var temp_stq_commit_head = stq_commit_head var temp_ldq_head = ldq_head for (w <- 0 until coreWidth) { val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head) when (commit_store) { stq(idx).bits.committed := true.B } .elsewhen (commit_load) { assert (ldq(idx).valid, "[lsu] trying to commit an un-allocated load entry.") assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded , "[lsu] trying to commit an un-executed load entry.") ldq(idx).valid := false.B ldq(idx).bits.addr.valid := false.B ldq(idx).bits.executed := false.B ldq(idx).bits.succeeded := false.B ldq(idx).bits.order_fail := false.B ldq(idx).bits.forward_std_val := false.B } if (MEMTRACE_PRINTF) { when (commit_store || commit_load) { val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop) val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits) val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U) val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data) printf("MT %x %x %x %x %x %x %x\n", io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata) } } temp_stq_commit_head = Mux(commit_store, WrapInc(temp_stq_commit_head, numStqEntries), temp_stq_commit_head) temp_ldq_head = Mux(commit_load, WrapInc(temp_ldq_head, numLdqEntries), temp_ldq_head) } stq_commit_head := temp_stq_commit_head ldq_head := temp_ldq_head // store has been committed AND successfully sent data to memory when (stq(stq_head).valid && stq(stq_head).bits.committed) { when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) { io.dmem.force_order := true.B store_needs_order := true.B } clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered, stq(stq_head).bits.succeeded) } when (clear_store) { stq(stq_head).valid := false.B stq(stq_head).bits.addr.valid := false.B stq(stq_head).bits.data.valid := false.B stq(stq_head).bits.succeeded := false.B stq(stq_head).bits.committed := false.B stq_head := WrapInc(stq_head, numStqEntries) when (stq(stq_head).bits.uop.is_fence) { stq_execute_head := WrapInc(stq_execute_head, numStqEntries) } } // ----------------------- // Hellacache interface // We need to time things like a HellaCache would io.hellacache.req.ready := false.B io.hellacache.s2_nack := false.B io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions) io.hellacache.resp.valid := false.B io.hellacache.store_pending := stq.map(_.valid).reduce(_||_) when (hella_state === h_ready) { io.hellacache.req.ready := true.B when (io.hellacache.req.fire) { hella_req := io.hellacache.req.bits hella_state := h_s1 } } .elsewhen (hella_state === h_s1) { can_fire_hella_incoming(memWidth-1) := true.B hella_data := io.hellacache.s1_data hella_xcpt := dtlb.io.resp(memWidth-1) when (io.hellacache.s1_kill) { when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_dead } .otherwise { hella_state := h_ready } } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_s2 } .otherwise { hella_state := h_s2_nack } } .elsewhen (hella_state === h_s2_nack) { io.hellacache.s2_nack := true.B hella_state := h_ready } .elsewhen (hella_state === h_s2) { io.hellacache.s2_xcpt := hella_xcpt when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) { hella_state := h_dead } .otherwise { hella_state := h_wait } } .elsewhen (hella_state === h_wait) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready io.hellacache.resp.valid := true.B io.hellacache.resp.bits.addr := hella_req.addr io.hellacache.resp.bits.tag := hella_req.tag io.hellacache.resp.bits.cmd := hella_req.cmd io.hellacache.resp.bits.signed := hella_req.signed io.hellacache.resp.bits.size := hella_req.size io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) { hella_state := h_replay } } } .elsewhen (hella_state === h_replay) { can_fire_hella_wakeup(memWidth-1) := true.B when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) { hella_state := h_wait } } .elsewhen (hella_state === h_dead) { for (w <- 0 until memWidth) { when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) { hella_state := h_ready } } } //------------------------------------------------------------- // Exception / Reset // for the live_store_mask, need to kill stores that haven't been committed val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B))) when (reset.asBool || io.core.exception) { ldq_head := 0.U ldq_tail := 0.U when (reset.asBool) { stq_head := 0.U stq_tail := 0.U stq_commit_head := 0.U stq_execute_head := 0.U for (i <- 0 until numStqEntries) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B stq(i).bits.uop := NullMicroOp } } .otherwise // exception { stq_tail := stq_commit_head for (i <- 0 until numStqEntries) { when (!stq(i).bits.committed && !stq(i).bits.succeeded) { stq(i).valid := false.B stq(i).bits.addr.valid := false.B stq(i).bits.data.valid := false.B st_exc_killed_mask(i) := true.B } } } for (i <- 0 until numLdqEntries) { ldq(i).valid := false.B ldq(i).bits.addr.valid := false.B ldq(i).bits.executed := false.B } } //------------------------------------------------------------- // Live Store Mask // track a bit-array of stores that are alive // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries) // TODO is this the most efficient way to compute the live store mask? live_store_mask := next_live_store_mask & ~(st_brkilled_mask.asUInt) & ~(st_exc_killed_mask.asUInt) } /** * Object to take an address and generate an 8-bit mask of which bytes within a * double-word. */ object GenByteMask { def apply(addr: UInt, size: UInt): UInt = { val mask = Wire(UInt(8.W)) mask := MuxCase(255.U(8.W), Array( (size === 0.U) -> (1.U(8.W) << addr(2,0)), (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)), (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)), (size === 3.U) -> 255.U(8.W))) mask } } /** * ... */ class ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p) { val io = IO(new Bundle { val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match // between the load and the SAQ val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get "age" val forwarding_val = Output(Bool()) val forwarding_idx = Output(UInt(stqAddrSz.W)) }) // generating mask that zeroes out anything younger than tail val age_mask = Wire(Vec(num_entries, Bool())) for (i <- 0 until num_entries) { age_mask(i) := true.B when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >= { age_mask(i) := false.B } } // Priority encoder with moving tail: double length val matches = Wire(UInt((2*num_entries).W)) matches := Cat(io.addr_matches & age_mask.asUInt, io.addr_matches) val found_match = Wire(Bool()) found_match := false.B io.forwarding_idx := 0.U // look for youngest, approach from the oldest side, let the last one found stick for (i <- 0 until (2*num_entries)) { when (matches(i)) { found_match := true.B io.forwarding_idx := (i % num_entries).U } } io.forwarding_val := found_match } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }
module LSU_1( // @[lsu.scala:201:7] input clock, // @[lsu.scala:201:7] input reset, // @[lsu.scala:201:7] input io_ptw_req_ready, // @[lsu.scala:204:14] output io_ptw_req_valid, // @[lsu.scala:204:14] output io_ptw_req_bits_valid, // @[lsu.scala:204:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:204:14] input io_ptw_resp_valid, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:204:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:204:14] input io_ptw_resp_bits_pf, // @[lsu.scala:204:14] input io_ptw_resp_bits_gf, // @[lsu.scala:204:14] input io_ptw_resp_bits_hr, // @[lsu.scala:204:14] input io_ptw_resp_bits_hw, // @[lsu.scala:204:14] input io_ptw_resp_bits_hx, // @[lsu.scala:204:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:204:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:204:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:204:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:204:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:204:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:204:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:204:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:204:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:204:14] input io_ptw_status_debug, // @[lsu.scala:204:14] input io_ptw_status_cease, // @[lsu.scala:204:14] input io_ptw_status_wfi, // @[lsu.scala:204:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:204:14] input io_ptw_status_dv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:204:14] input io_ptw_status_v, // @[lsu.scala:204:14] input io_ptw_status_sd, // @[lsu.scala:204:14] input io_ptw_status_mpv, // @[lsu.scala:204:14] input io_ptw_status_gva, // @[lsu.scala:204:14] input io_ptw_status_tsr, // @[lsu.scala:204:14] input io_ptw_status_tw, // @[lsu.scala:204:14] input io_ptw_status_tvm, // @[lsu.scala:204:14] input io_ptw_status_mxr, // @[lsu.scala:204:14] input io_ptw_status_sum, // @[lsu.scala:204:14] input io_ptw_status_mprv, // @[lsu.scala:204:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:204:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:204:14] input io_ptw_status_spp, // @[lsu.scala:204:14] input io_ptw_status_mpie, // @[lsu.scala:204:14] input io_ptw_status_spie, // @[lsu.scala:204:14] input io_ptw_status_mie, // @[lsu.scala:204:14] input io_ptw_status_sie, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:204:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:204:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:204:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:204:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:204:14] input io_core_exe_0_req_valid, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_exe_0_req_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_exe_0_req_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_exe_0_req_bits_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_exe_0_req_bits_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_exe_0_req_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_exe_0_req_bits_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_exe_0_req_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_exe_0_req_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_exe_0_req_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_exe_0_req_bits_data, // @[lsu.scala:204:14] input [39:0] io_core_exe_0_req_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_mxcpt_valid, // @[lsu.scala:204:14] input [24:0] io_core_exe_0_req_bits_mxcpt_bits, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_valid, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs1, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_rs2, // @[lsu.scala:204:14] input [38:0] io_core_exe_0_req_bits_sfence_bits_addr, // @[lsu.scala:204:14] input io_core_exe_0_req_bits_sfence_bits_asid, // @[lsu.scala:204:14] output io_core_exe_0_iresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_iresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_iresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_iresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [15:0] io_core_exe_0_iresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_iresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_iresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_iresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_pdst, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_prs1, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_prs2, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_prs3, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_iresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_iresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_iresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_iresp_bits_data, // @[lsu.scala:204:14] output io_core_exe_0_fresp_valid, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_exe_0_fresp_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_exe_0_fresp_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_exe_0_fresp_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sfb, // @[lsu.scala:204:14] output [15:0] io_core_exe_0_fresp_bits_uop_br_mask, // @[lsu.scala:204:14] output [3:0] io_core_exe_0_fresp_bits_uop_br_tag, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_exe_0_fresp_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_exe_0_fresp_bits_uop_csr_addr, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_rob_idx, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_pdst, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_prs1, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_prs2, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_prs3, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [6:0] io_core_exe_0_fresp_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_exe_0_fresp_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_exe_0_fresp_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_exe_0_fresp_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [64:0] io_core_exe_0_fresp_bits_data, // @[lsu.scala:204:14] input io_core_dis_uops_0_valid, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_uopc, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_dis_uops_0_bits_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_load, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_iw_state, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_br, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jalr, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_jal, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:204:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_dis_uops_0_bits_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:204:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_fp_single, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:204:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:204:14] input io_core_dis_uops_1_valid, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_uopc, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_1_bits_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_dis_uops_1_bits_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_1_bits_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_1_bits_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_1_bits_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_1_bits_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_1_bits_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ctrl_is_load, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_iw_state, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_br, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_jalr, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_jal, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_taken, // @[lsu.scala:204:14] input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_dis_uops_1_bits_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_exception, // @[lsu.scala:204:14] input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_fp_single, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:204:14] input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:204:14] input io_core_dis_uops_2_valid, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_uopc, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_2_bits_inst, // @[lsu.scala:204:14] input [31:0] io_core_dis_uops_2_bits_debug_inst, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_dis_uops_2_bits_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_2_bits_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_dis_uops_2_bits_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_2_bits_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_2_bits_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_2_bits_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_2_bits_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_dis_uops_2_bits_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ctrl_is_load, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_iw_state, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_br, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_jalr, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_jal, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_dis_uops_2_bits_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_dis_uops_2_bits_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_2_bits_ftq_idx, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_2_bits_pc_lob, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_taken, // @[lsu.scala:204:14] input [19:0] io_core_dis_uops_2_bits_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_dis_uops_2_bits_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_2_bits_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_2_bits_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_pdst, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_prs1, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_prs2, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_prs3, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_prs1_busy, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_prs2_busy, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_prs3_busy, // @[lsu.scala:204:14] input [6:0] io_core_dis_uops_2_bits_stale_pdst, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_exception, // @[lsu.scala:204:14] input [63:0] io_core_dis_uops_2_bits_exc_cause, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_dis_uops_2_bits_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_mem_size, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_mem_signed, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_fence, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_fencei, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_amo, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_uses_ldq, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_uses_stq, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_is_unique, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_flush_on_commit, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_2_bits_ldst, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_2_bits_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_2_bits_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_dis_uops_2_bits_lrs3, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_lrs2_rtype, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_frs3_en, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_fp_val, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_fp_single, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_bp_debug_if, // @[lsu.scala:204:14] input io_core_dis_uops_2_bits_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_dis_uops_2_bits_debug_tsrc, // @[lsu.scala:204:14] output [4:0] io_core_dis_ldq_idx_0, // @[lsu.scala:204:14] output [4:0] io_core_dis_ldq_idx_1, // @[lsu.scala:204:14] output [4:0] io_core_dis_ldq_idx_2, // @[lsu.scala:204:14] output [4:0] io_core_dis_stq_idx_0, // @[lsu.scala:204:14] output [4:0] io_core_dis_stq_idx_1, // @[lsu.scala:204:14] output [4:0] io_core_dis_stq_idx_2, // @[lsu.scala:204:14] output io_core_ldq_full_0, // @[lsu.scala:204:14] output io_core_ldq_full_1, // @[lsu.scala:204:14] output io_core_ldq_full_2, // @[lsu.scala:204:14] output io_core_stq_full_0, // @[lsu.scala:204:14] output io_core_stq_full_1, // @[lsu.scala:204:14] output io_core_stq_full_2, // @[lsu.scala:204:14] output io_core_fp_stdata_ready, // @[lsu.scala:204:14] input io_core_fp_stdata_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_fp_stdata_bits_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_data, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_predicated, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_valid, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_br, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_jal, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fence, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_amo, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_is_unique, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_val, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_fp_single, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [4:0] io_core_fp_stdata_bits_fflags_bits_flags, // @[lsu.scala:204:14] input io_core_commit_valids_0, // @[lsu.scala:204:14] input io_core_commit_valids_1, // @[lsu.scala:204:14] input io_core_commit_valids_2, // @[lsu.scala:204:14] input io_core_commit_arch_valids_0, // @[lsu.scala:204:14] input io_core_commit_arch_valids_1, // @[lsu.scala:204:14] input io_core_commit_arch_valids_2, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_uopc, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_commit_uops_0_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_0_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_load, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_commit_uops_0_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_iw_state, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_br, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jalr, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_jal, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:204:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:204:14] input io_core_commit_uops_0_taken, // @[lsu.scala:204:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_commit_uops_0_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:204:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:204:14] input io_core_commit_uops_0_exception, // @[lsu.scala:204:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:204:14] input io_core_commit_uops_0_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:204:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:204:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:204:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:204:14] input io_core_commit_uops_0_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:204:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:204:14] input io_core_commit_uops_0_fp_single, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:204:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_uopc, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_1_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_commit_uops_1_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_1_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_1_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_1_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_commit_uops_1_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_1_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_commit_uops_1_ctrl_is_load, // @[lsu.scala:204:14] input io_core_commit_uops_1_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_commit_uops_1_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_iw_state, // @[lsu.scala:204:14] input io_core_commit_uops_1_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_1_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_br, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_jalr, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_jal, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:204:14] input io_core_commit_uops_1_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:204:14] input io_core_commit_uops_1_taken, // @[lsu.scala:204:14] input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_commit_uops_1_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:204:14] input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:204:14] input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:204:14] input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:204:14] input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:204:14] input io_core_commit_uops_1_exception, // @[lsu.scala:204:14] input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:204:14] input io_core_commit_uops_1_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:204:14] input io_core_commit_uops_1_mem_signed, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_fence, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_fencei, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_amo, // @[lsu.scala:204:14] input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:204:14] input io_core_commit_uops_1_uses_stq, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_commit_uops_1_is_unique, // @[lsu.scala:204:14] input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:204:14] input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:204:14] input io_core_commit_uops_1_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:204:14] input io_core_commit_uops_1_frs3_en, // @[lsu.scala:204:14] input io_core_commit_uops_1_fp_val, // @[lsu.scala:204:14] input io_core_commit_uops_1_fp_single, // @[lsu.scala:204:14] input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:204:14] input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_uopc, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_2_inst, // @[lsu.scala:204:14] input [31:0] io_core_commit_uops_2_debug_inst, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_commit_uops_2_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_2_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_commit_uops_2_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_2_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_2_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_2_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_commit_uops_2_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_commit_uops_2_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_commit_uops_2_ctrl_is_load, // @[lsu.scala:204:14] input io_core_commit_uops_2_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_commit_uops_2_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_iw_state, // @[lsu.scala:204:14] input io_core_commit_uops_2_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_2_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_br, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_jalr, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_jal, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_commit_uops_2_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_commit_uops_2_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_ftq_idx, // @[lsu.scala:204:14] input io_core_commit_uops_2_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_2_pc_lob, // @[lsu.scala:204:14] input io_core_commit_uops_2_taken, // @[lsu.scala:204:14] input [19:0] io_core_commit_uops_2_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_commit_uops_2_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_pdst, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_prs1, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_prs2, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_prs3, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_ppred, // @[lsu.scala:204:14] input io_core_commit_uops_2_prs1_busy, // @[lsu.scala:204:14] input io_core_commit_uops_2_prs2_busy, // @[lsu.scala:204:14] input io_core_commit_uops_2_prs3_busy, // @[lsu.scala:204:14] input io_core_commit_uops_2_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_commit_uops_2_stale_pdst, // @[lsu.scala:204:14] input io_core_commit_uops_2_exception, // @[lsu.scala:204:14] input [63:0] io_core_commit_uops_2_exc_cause, // @[lsu.scala:204:14] input io_core_commit_uops_2_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_commit_uops_2_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_mem_size, // @[lsu.scala:204:14] input io_core_commit_uops_2_mem_signed, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_fence, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_fencei, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_amo, // @[lsu.scala:204:14] input io_core_commit_uops_2_uses_ldq, // @[lsu.scala:204:14] input io_core_commit_uops_2_uses_stq, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_commit_uops_2_is_unique, // @[lsu.scala:204:14] input io_core_commit_uops_2_flush_on_commit, // @[lsu.scala:204:14] input io_core_commit_uops_2_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_2_ldst, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_2_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_2_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_commit_uops_2_lrs3, // @[lsu.scala:204:14] input io_core_commit_uops_2_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_lrs2_rtype, // @[lsu.scala:204:14] input io_core_commit_uops_2_frs3_en, // @[lsu.scala:204:14] input io_core_commit_uops_2_fp_val, // @[lsu.scala:204:14] input io_core_commit_uops_2_fp_single, // @[lsu.scala:204:14] input io_core_commit_uops_2_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_commit_uops_2_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_commit_uops_2_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_commit_uops_2_bp_debug_if, // @[lsu.scala:204:14] input io_core_commit_uops_2_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_commit_uops_2_debug_tsrc, // @[lsu.scala:204:14] input io_core_commit_fflags_valid, // @[lsu.scala:204:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:204:14] input [31:0] io_core_commit_debug_insts_0, // @[lsu.scala:204:14] input [31:0] io_core_commit_debug_insts_1, // @[lsu.scala:204:14] input [31:0] io_core_commit_debug_insts_2, // @[lsu.scala:204:14] input io_core_commit_rbk_valids_0, // @[lsu.scala:204:14] input io_core_commit_rbk_valids_1, // @[lsu.scala:204:14] input io_core_commit_rbk_valids_2, // @[lsu.scala:204:14] input io_core_commit_rollback, // @[lsu.scala:204:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:204:14] input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:204:14] input [63:0] io_core_commit_debug_wdata_2, // @[lsu.scala:204:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:204:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:204:14] output [6:0] io_core_clr_bsy_0_bits, // @[lsu.scala:204:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:204:14] output [6:0] io_core_clr_bsy_1_bits, // @[lsu.scala:204:14] output [6:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:204:14] input io_core_fence_dmem, // @[lsu.scala:204:14] output io_core_spec_ld_wakeup_0_valid, // @[lsu.scala:204:14] output [6:0] io_core_spec_ld_wakeup_0_bits, // @[lsu.scala:204:14] output io_core_ld_miss, // @[lsu.scala:204:14] input [15:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] input [15:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:204:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_core_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:204:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_core_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:204:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] input io_core_brupdate_b2_valid, // @[lsu.scala:204:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:204:14] input io_core_brupdate_b2_taken, // @[lsu.scala:204:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:204:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:204:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:204:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:204:14] input [6:0] io_core_rob_pnr_idx, // @[lsu.scala:204:14] input [6:0] io_core_rob_head_idx, // @[lsu.scala:204:14] input io_core_exception, // @[lsu.scala:204:14] output io_core_fencei_rdy, // @[lsu.scala:204:14] output io_core_lxcpt_valid, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_core_lxcpt_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_iw_state, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_br, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_jal, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:204:14] output [15:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:204:14] output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_core_lxcpt_bits_uop_csr_addr, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_fp_single, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:204:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:204:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:204:14] output io_core_perf_acquire, // @[lsu.scala:204:14] output io_core_perf_release, // @[lsu.scala:204:14] output io_core_perf_tlbMiss, // @[lsu.scala:204:14] input io_dmem_req_ready, // @[lsu.scala:204:14] output io_dmem_req_valid, // @[lsu.scala:204:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_req_bits_0_bits_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_br, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:204:14] output [15:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:204:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:204:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:204:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:204:14] output io_dmem_s1_kill_0, // @[lsu.scala:204:14] input io_dmem_resp_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_resp_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_resp_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:204:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:204:14] input io_dmem_nack_0_valid, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_uopc, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:204:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_iq_type, // @[lsu.scala:204:14] input [9:0] io_dmem_nack_0_bits_uop_fu_code, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] input [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_load, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_sta, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ctrl_is_std, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_iw_state, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p1_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_iw_p2_poisoned, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_br, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jalr, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_jal, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:204:14] input [15:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:204:14] input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:204:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:204:14] input [11:0] io_dmem_nack_0_bits_uop_csr_addr, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:204:14] input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bypassable, // @[lsu.scala:204:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:204:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_ldst_val, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_fp_single, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:204:14] input [1:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:204:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:204:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:204:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:204:14] output [15:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:204:14] output [15:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_uopc, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:204:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_iq_type, // @[lsu.scala:204:14] output [9:0] io_dmem_brupdate_b2_uop_fu_code, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_fcn_dw, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_load, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_sta, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ctrl_is_std, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_iw_state, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p1_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_iw_p2_poisoned, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_br, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jalr, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_jal, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:204:14] output [15:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:204:14] output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:204:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:204:14] output [11:0] io_dmem_brupdate_b2_uop_csr_addr, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:204:14] output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:204:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bypassable, // @[lsu.scala:204:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:204:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_ldst_val, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_fp_single, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_valid, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:204:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:204:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:204:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:204:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:204:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:204:14] output io_dmem_exception, // @[lsu.scala:204:14] output [6:0] io_dmem_rob_pnr_idx, // @[lsu.scala:204:14] output [6:0] io_dmem_rob_head_idx, // @[lsu.scala:204:14] output io_dmem_release_ready, // @[lsu.scala:204:14] input io_dmem_release_valid, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:204:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:204:14] input [2:0] io_dmem_release_bits_source, // @[lsu.scala:204:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:204:14] input [127:0] io_dmem_release_bits_data, // @[lsu.scala:204:14] output io_dmem_force_order, // @[lsu.scala:204:14] input io_dmem_ordered, // @[lsu.scala:204:14] input io_dmem_perf_acquire, // @[lsu.scala:204:14] input io_dmem_perf_release, // @[lsu.scala:204:14] output io_hellacache_req_ready, // @[lsu.scala:204:14] input io_hellacache_req_valid, // @[lsu.scala:204:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:204:14] input io_hellacache_req_bits_dv, // @[lsu.scala:204:14] input io_hellacache_s1_kill, // @[lsu.scala:204:14] output io_hellacache_s2_nack, // @[lsu.scala:204:14] output io_hellacache_resp_valid, // @[lsu.scala:204:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:204:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:204:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:204:14] output io_hellacache_store_pending // @[lsu.scala:204:14] ); wire failed_loads_22; // @[lsu.scala:1054:34] wire failed_loads_21; // @[lsu.scala:1054:34] wire failed_loads_20; // @[lsu.scala:1054:34] wire failed_loads_19; // @[lsu.scala:1054:34] wire failed_loads_18; // @[lsu.scala:1054:34] wire failed_loads_17; // @[lsu.scala:1054:34] wire failed_loads_16; // @[lsu.scala:1054:34] wire failed_loads_15; // @[lsu.scala:1054:34] wire failed_loads_14; // @[lsu.scala:1054:34] wire failed_loads_13; // @[lsu.scala:1054:34] wire failed_loads_12; // @[lsu.scala:1054:34] wire failed_loads_11; // @[lsu.scala:1054:34] wire failed_loads_10; // @[lsu.scala:1054:34] wire failed_loads_9; // @[lsu.scala:1054:34] wire failed_loads_8; // @[lsu.scala:1054:34] wire failed_loads_7; // @[lsu.scala:1054:34] wire failed_loads_6; // @[lsu.scala:1054:34] wire failed_loads_5; // @[lsu.scala:1054:34] wire failed_loads_4; // @[lsu.scala:1054:34] wire failed_loads_3; // @[lsu.scala:1054:34] wire failed_loads_2; // @[lsu.scala:1054:34] wire failed_loads_1; // @[lsu.scala:1054:34] wire failed_loads_0; // @[lsu.scala:1054:34] wire mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [15:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [15:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [15:0] mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [15:0] mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [63:0] stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_committed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_data_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_data_valid; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:263:49] wire [23:0] ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_observed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_executed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:263:49] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:263:49] wire [11:0] ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:263:49] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:263:49] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:263:49] wire [9:0] ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:263:49] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:263:49] wire [31:0] ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:263:49] wire [6:0] ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49] wire ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49] wire [4:0] ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49] wire [2:0] ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49] wire [1:0] ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49] wire [3:0] ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:263:49] wire [1:0] exe_req_0_bits_uop_debug_tsrc; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_debug_fsrc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bp_debug_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_single; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_fp_val; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_frs3_en; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_dst_rtype; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_val; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs3; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs2; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_lrs1; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_ldst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_flush_on_commit; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_unique; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_stq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_uses_ldq; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_amo; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fencei; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_fence; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_mem_signed; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_mem_size; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_mem_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_bypassable; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_uop_exc_cause; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_exception; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_stale_pdst; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ppred_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs3_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs2_busy; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_prs1_busy; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ppred; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_prs3; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_prs2; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_prs1; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_pdst; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_rxq_idx; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_stq_idx; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_rob_idx; // @[lsu.scala:383:25] wire [11:0] exe_req_0_bits_uop_csr_addr; // @[lsu.scala:383:25] wire [19:0] exe_req_0_bits_uop_imm_packed; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_taken; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_uop_pc_lob; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_edge_inst; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ftq_idx; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_br_tag; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_sfb; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jal; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_jalr; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_br; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_iw_state; // @[lsu.scala:383:25] wire [9:0] exe_req_0_bits_uop_fu_code; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_iq_type; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_uop_debug_pc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_is_rvc; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_debug_inst; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_uop_inst; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_uop_uopc; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:383:25] wire exe_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:383:25] wire _dtlb_io_miss_rdy; // @[lsu.scala:247:20] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:247:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:201:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:201:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:201:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:201:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:201:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:201:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:201:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:201:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:201:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:201:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:201:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:201:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:201:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:201:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:201:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:201:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:201:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:201:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:201:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:201:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:201:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:201:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:201:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:201:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:201:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:201:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:201:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:201:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:201:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:201:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:201:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:201:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:201:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:201:7] wire io_core_exe_0_req_valid_0 = io_core_exe_0_req_valid; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_uopc_0 = io_core_exe_0_req_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_inst_0 = io_core_exe_0_req_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_uop_debug_inst_0 = io_core_exe_0_req_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_rvc_0 = io_core_exe_0_req_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_uop_debug_pc_0 = io_core_exe_0_req_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_iq_type_0 = io_core_exe_0_req_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_req_bits_uop_fu_code_0 = io_core_exe_0_req_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type_0 = io_core_exe_0_req_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 = io_core_exe_0_req_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 = io_core_exe_0_req_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 = io_core_exe_0_req_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 = io_core_exe_0_req_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 = io_core_exe_0_req_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_load_0 = io_core_exe_0_req_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_sta_0 = io_core_exe_0_req_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ctrl_is_std_0 = io_core_exe_0_req_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_iw_state_0 = io_core_exe_0_req_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 = io_core_exe_0_req_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_br_0 = io_core_exe_0_req_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jalr_0 = io_core_exe_0_req_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_jal_0 = io_core_exe_0_req_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sfb_0 = io_core_exe_0_req_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_req_bits_uop_br_mask_0 = io_core_exe_0_req_bits_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_uop_br_tag_0 = io_core_exe_0_req_bits_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ftq_idx_0 = io_core_exe_0_req_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_edge_inst_0 = io_core_exe_0_req_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_pc_lob_0 = io_core_exe_0_req_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_taken_0 = io_core_exe_0_req_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_req_bits_uop_imm_packed_0 = io_core_exe_0_req_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_req_bits_uop_csr_addr_0 = io_core_exe_0_req_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_rob_idx_0 = io_core_exe_0_req_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ldq_idx_0 = io_core_exe_0_req_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_stq_idx_0 = io_core_exe_0_req_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_rxq_idx_0 = io_core_exe_0_req_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_pdst_0 = io_core_exe_0_req_bits_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_prs1_0 = io_core_exe_0_req_bits_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_prs2_0 = io_core_exe_0_req_bits_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_prs3_0 = io_core_exe_0_req_bits_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_ppred_0 = io_core_exe_0_req_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs1_busy_0 = io_core_exe_0_req_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs2_busy_0 = io_core_exe_0_req_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_prs3_busy_0 = io_core_exe_0_req_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ppred_busy_0 = io_core_exe_0_req_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_uop_stale_pdst_0 = io_core_exe_0_req_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_exception_0 = io_core_exe_0_req_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_uop_exc_cause_0 = io_core_exe_0_req_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bypassable_0 = io_core_exe_0_req_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_uop_mem_cmd_0 = io_core_exe_0_req_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_mem_size_0 = io_core_exe_0_req_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_mem_signed_0 = io_core_exe_0_req_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fence_0 = io_core_exe_0_req_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_fencei_0 = io_core_exe_0_req_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_amo_0 = io_core_exe_0_req_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_ldq_0 = io_core_exe_0_req_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_uses_stq_0 = io_core_exe_0_req_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 = io_core_exe_0_req_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_is_unique_0 = io_core_exe_0_req_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_flush_on_commit_0 = io_core_exe_0_req_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_is_rs1_0 = io_core_exe_0_req_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_ldst_0 = io_core_exe_0_req_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs1_0 = io_core_exe_0_req_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs2_0 = io_core_exe_0_req_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_uop_lrs3_0 = io_core_exe_0_req_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_ldst_val_0 = io_core_exe_0_req_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_dst_rtype_0 = io_core_exe_0_req_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype_0 = io_core_exe_0_req_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype_0 = io_core_exe_0_req_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_frs3_en_0 = io_core_exe_0_req_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_val_0 = io_core_exe_0_req_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_fp_single_0 = io_core_exe_0_req_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_pf_if_0 = io_core_exe_0_req_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ae_if_0 = io_core_exe_0_req_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_xcpt_ma_if_0 = io_core_exe_0_req_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_debug_if_0 = io_core_exe_0_req_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_uop_bp_xcpt_if_0 = io_core_exe_0_req_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_fsrc_0 = io_core_exe_0_req_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_uop_debug_tsrc_0 = io_core_exe_0_req_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_data_0 = io_core_exe_0_req_bits_data; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_req_bits_addr_0 = io_core_exe_0_req_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_mxcpt_valid_0 = io_core_exe_0_req_bits_mxcpt_valid; // @[lsu.scala:201:7] wire [24:0] io_core_exe_0_req_bits_mxcpt_bits_0 = io_core_exe_0_req_bits_mxcpt_bits; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_valid_0 = io_core_exe_0_req_bits_sfence_valid; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs1_0 = io_core_exe_0_req_bits_sfence_bits_rs1; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_rs2_0 = io_core_exe_0_req_bits_sfence_bits_rs2; // @[lsu.scala:201:7] wire [38:0] io_core_exe_0_req_bits_sfence_bits_addr_0 = io_core_exe_0_req_bits_sfence_bits_addr; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_asid_0 = io_core_exe_0_req_bits_sfence_bits_asid; // @[lsu.scala:201:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_uopc_0 = io_core_dis_uops_0_bits_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_iq_type_0 = io_core_dis_uops_0_bits_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_dis_uops_0_bits_fu_code_0 = io_core_dis_uops_0_bits_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_ctrl_br_type_0 = io_core_dis_uops_0_bits_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel_0 = io_core_dis_uops_0_bits_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel_0 = io_core_dis_uops_0_bits_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel_0 = io_core_dis_uops_0_bits_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn_0 = io_core_dis_uops_0_bits_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_fcn_dw_0 = io_core_dis_uops_0_bits_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd_0 = io_core_dis_uops_0_bits_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_load_0 = io_core_dis_uops_0_bits_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_sta_0 = io_core_dis_uops_0_bits_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ctrl_is_std_0 = io_core_dis_uops_0_bits_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_iw_state_0 = io_core_dis_uops_0_bits_iw_state; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p1_poisoned_0 = io_core_dis_uops_0_bits_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_iw_p2_poisoned_0 = io_core_dis_uops_0_bits_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_br_0 = io_core_dis_uops_0_bits_is_br; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jalr_0 = io_core_dis_uops_0_bits_is_jalr; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_jal_0 = io_core_dis_uops_0_bits_is_jal; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:201:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_dis_uops_0_bits_csr_addr_0 = io_core_dis_uops_0_bits_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:201:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bypassable_0 = io_core_dis_uops_0_bits_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ldst_val_0 = io_core_dis_uops_0_bits_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_fp_single_0 = io_core_dis_uops_0_bits_fp_single; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:201:7] wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_uopc_0 = io_core_dis_uops_1_bits_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_1_bits_iq_type_0 = io_core_dis_uops_1_bits_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_dis_uops_1_bits_fu_code_0 = io_core_dis_uops_1_bits_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_1_bits_ctrl_br_type_0 = io_core_dis_uops_1_bits_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_ctrl_op1_sel_0 = io_core_dis_uops_1_bits_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_1_bits_ctrl_op2_sel_0 = io_core_dis_uops_1_bits_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_1_bits_ctrl_imm_sel_0 = io_core_dis_uops_1_bits_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_ctrl_op_fcn_0 = io_core_dis_uops_1_bits_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ctrl_fcn_dw_0 = io_core_dis_uops_1_bits_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_1_bits_ctrl_csr_cmd_0 = io_core_dis_uops_1_bits_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ctrl_is_load_0 = io_core_dis_uops_1_bits_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ctrl_is_sta_0 = io_core_dis_uops_1_bits_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ctrl_is_std_0 = io_core_dis_uops_1_bits_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_iw_state_0 = io_core_dis_uops_1_bits_iw_state; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_iw_p1_poisoned_0 = io_core_dis_uops_1_bits_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_iw_p2_poisoned_0 = io_core_dis_uops_1_bits_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_br_0 = io_core_dis_uops_1_bits_is_br; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_jalr_0 = io_core_dis_uops_1_bits_is_jalr; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_jal_0 = io_core_dis_uops_1_bits_is_jal; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:201:7] wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_dis_uops_1_bits_csr_addr_0 = io_core_dis_uops_1_bits_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:201:7] wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_bypassable_0 = io_core_dis_uops_1_bits_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ldst_val_0 = io_core_dis_uops_1_bits_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_fp_single_0 = io_core_dis_uops_1_bits_fp_single; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:201:7] wire io_core_dis_uops_2_valid_0 = io_core_dis_uops_2_valid; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_uopc_0 = io_core_dis_uops_2_bits_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_2_bits_inst_0 = io_core_dis_uops_2_bits_inst; // @[lsu.scala:201:7] wire [31:0] io_core_dis_uops_2_bits_debug_inst_0 = io_core_dis_uops_2_bits_debug_inst; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_rvc_0 = io_core_dis_uops_2_bits_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_dis_uops_2_bits_debug_pc_0 = io_core_dis_uops_2_bits_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_2_bits_iq_type_0 = io_core_dis_uops_2_bits_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_dis_uops_2_bits_fu_code_0 = io_core_dis_uops_2_bits_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_2_bits_ctrl_br_type_0 = io_core_dis_uops_2_bits_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_ctrl_op1_sel_0 = io_core_dis_uops_2_bits_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_2_bits_ctrl_op2_sel_0 = io_core_dis_uops_2_bits_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_2_bits_ctrl_imm_sel_0 = io_core_dis_uops_2_bits_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_ctrl_op_fcn_0 = io_core_dis_uops_2_bits_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ctrl_fcn_dw_0 = io_core_dis_uops_2_bits_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_dis_uops_2_bits_ctrl_csr_cmd_0 = io_core_dis_uops_2_bits_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ctrl_is_load_0 = io_core_dis_uops_2_bits_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ctrl_is_sta_0 = io_core_dis_uops_2_bits_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ctrl_is_std_0 = io_core_dis_uops_2_bits_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_iw_state_0 = io_core_dis_uops_2_bits_iw_state; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_iw_p1_poisoned_0 = io_core_dis_uops_2_bits_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_iw_p2_poisoned_0 = io_core_dis_uops_2_bits_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_br_0 = io_core_dis_uops_2_bits_is_br; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_jalr_0 = io_core_dis_uops_2_bits_is_jalr; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_jal_0 = io_core_dis_uops_2_bits_is_jal; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_sfb_0 = io_core_dis_uops_2_bits_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_dis_uops_2_bits_br_mask_0 = io_core_dis_uops_2_bits_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_dis_uops_2_bits_br_tag_0 = io_core_dis_uops_2_bits_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_ftq_idx_0 = io_core_dis_uops_2_bits_ftq_idx; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_edge_inst_0 = io_core_dis_uops_2_bits_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_2_bits_pc_lob_0 = io_core_dis_uops_2_bits_pc_lob; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_taken_0 = io_core_dis_uops_2_bits_taken; // @[lsu.scala:201:7] wire [19:0] io_core_dis_uops_2_bits_imm_packed_0 = io_core_dis_uops_2_bits_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_dis_uops_2_bits_csr_addr_0 = io_core_dis_uops_2_bits_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_rob_idx_0 = io_core_dis_uops_2_bits_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_ldq_idx_0 = io_core_dis_uops_2_bits_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_stq_idx_0 = io_core_dis_uops_2_bits_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_rxq_idx_0 = io_core_dis_uops_2_bits_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_pdst_0 = io_core_dis_uops_2_bits_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_prs1_0 = io_core_dis_uops_2_bits_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_prs2_0 = io_core_dis_uops_2_bits_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_prs3_0 = io_core_dis_uops_2_bits_prs3; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_prs1_busy_0 = io_core_dis_uops_2_bits_prs1_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_prs2_busy_0 = io_core_dis_uops_2_bits_prs2_busy; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_prs3_busy_0 = io_core_dis_uops_2_bits_prs3_busy; // @[lsu.scala:201:7] wire [6:0] io_core_dis_uops_2_bits_stale_pdst_0 = io_core_dis_uops_2_bits_stale_pdst; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_exception_0 = io_core_dis_uops_2_bits_exception; // @[lsu.scala:201:7] wire [63:0] io_core_dis_uops_2_bits_exc_cause_0 = io_core_dis_uops_2_bits_exc_cause; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_bypassable_0 = io_core_dis_uops_2_bits_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_mem_cmd_0 = io_core_dis_uops_2_bits_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_mem_size_0 = io_core_dis_uops_2_bits_mem_size; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_mem_signed_0 = io_core_dis_uops_2_bits_mem_signed; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_fence_0 = io_core_dis_uops_2_bits_is_fence; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_fencei_0 = io_core_dis_uops_2_bits_is_fencei; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_amo_0 = io_core_dis_uops_2_bits_is_amo; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_uses_ldq_0 = io_core_dis_uops_2_bits_uses_ldq; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_uses_stq_0 = io_core_dis_uops_2_bits_uses_stq; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_sys_pc2epc_0 = io_core_dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_is_unique_0 = io_core_dis_uops_2_bits_is_unique; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_flush_on_commit_0 = io_core_dis_uops_2_bits_flush_on_commit; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ldst_is_rs1_0 = io_core_dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_2_bits_ldst_0 = io_core_dis_uops_2_bits_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_2_bits_lrs1_0 = io_core_dis_uops_2_bits_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_2_bits_lrs2_0 = io_core_dis_uops_2_bits_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_dis_uops_2_bits_lrs3_0 = io_core_dis_uops_2_bits_lrs3; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ldst_val_0 = io_core_dis_uops_2_bits_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_dst_rtype_0 = io_core_dis_uops_2_bits_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_lrs1_rtype_0 = io_core_dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_lrs2_rtype_0 = io_core_dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_frs3_en_0 = io_core_dis_uops_2_bits_frs3_en; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_fp_val_0 = io_core_dis_uops_2_bits_fp_val; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_fp_single_0 = io_core_dis_uops_2_bits_fp_single; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_xcpt_pf_if_0 = io_core_dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_xcpt_ae_if_0 = io_core_dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_xcpt_ma_if_0 = io_core_dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_bp_debug_if_0 = io_core_dis_uops_2_bits_bp_debug_if; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_bp_xcpt_if_0 = io_core_dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_debug_fsrc_0 = io_core_dis_uops_2_bits_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_dis_uops_2_bits_debug_tsrc_0 = io_core_dis_uops_2_bits_debug_tsrc; // @[lsu.scala:201:7] wire io_core_fp_stdata_valid_0 = io_core_fp_stdata_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_uopc_0 = io_core_fp_stdata_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_inst_0 = io_core_fp_stdata_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_iq_type_0 = io_core_fp_stdata_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_uop_fu_code_0 = io_core_fp_stdata_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_iw_state_0 = io_core_fp_stdata_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_br_0 = io_core_fp_stdata_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_jal_0 = io_core_fp_stdata_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_fp_stdata_bits_uop_br_mask_0 = io_core_fp_stdata_bits_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_uop_br_tag_0 = io_core_fp_stdata_bits_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_taken_0 = io_core_fp_stdata_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_pdst_0 = io_core_fp_stdata_bits_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_prs1_0 = io_core_fp_stdata_bits_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_prs2_0 = io_core_fp_stdata_bits_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_prs3_0 = io_core_fp_stdata_bits_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_ppred_0 = io_core_fp_stdata_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_exception_0 = io_core_fp_stdata_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bypassable_0 = io_core_fp_stdata_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_mem_size_0 = io_core_fp_stdata_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fence_0 = io_core_fp_stdata_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_amo_0 = io_core_fp_stdata_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_is_unique_0 = io_core_fp_stdata_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_ldst_0 = io_core_fp_stdata_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs1_0 = io_core_fp_stdata_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs2_0 = io_core_fp_stdata_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_uop_lrs3_0 = io_core_fp_stdata_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_val_0 = io_core_fp_stdata_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_fp_single_0 = io_core_fp_stdata_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_data_0 = io_core_fp_stdata_bits_data; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_predicated_0 = io_core_fp_stdata_bits_predicated; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_valid_0 = io_core_fp_stdata_bits_fflags_valid; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_uopc_0 = io_core_fp_stdata_bits_fflags_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_rvc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_pc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_iq_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_fp_stdata_bits_fflags_bits_uop_fu_code_0 = io_core_fp_stdata_bits_fflags_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0 = io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_iw_state_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_br_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_br; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jalr_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_jal_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sfb_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_fp_stdata_bits_fflags_bits_uop_br_mask_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_fp_stdata_bits_fflags_bits_uop_br_tag_0 = io_core_fp_stdata_bits_fflags_bits_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_edge_inst_0 = io_core_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_pc_lob_0 = io_core_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_taken_0 = io_core_fp_stdata_bits_fflags_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_fp_stdata_bits_fflags_bits_uop_imm_packed_0 = io_core_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_fp_stdata_bits_fflags_bits_uop_csr_addr_0 = io_core_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_rob_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_stq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx_0 = io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_prs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_ppred_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy_0 = io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst_0 = io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_exception_0 = io_core_fp_stdata_bits_fflags_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_fp_stdata_bits_fflags_bits_uop_exc_cause_0 = io_core_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bypassable_0 = io_core_fp_stdata_bits_fflags_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_mem_size_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_mem_signed_0 = io_core_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fence_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_fencei_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_amo_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_uses_stq_0 = io_core_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_is_unique_0 = io_core_fp_stdata_bits_fflags_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0 = io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_ldst_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs3_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_ldst_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0 = io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_frs3_en_0 = io_core_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_val_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_fp_single_0 = io_core_fp_stdata_bits_fflags_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0 = io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0 = io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [4:0] io_core_fp_stdata_bits_fflags_bits_flags_0 = io_core_fp_stdata_bits_fflags_bits_flags; // @[lsu.scala:201:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:201:7] wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:201:7] wire io_core_commit_valids_2_0 = io_core_commit_valids_2; // @[lsu.scala:201:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:201:7] wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:201:7] wire io_core_commit_arch_valids_2_0 = io_core_commit_arch_valids_2; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_uopc_0 = io_core_commit_uops_0_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_iq_type_0 = io_core_commit_uops_0_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_commit_uops_0_fu_code_0 = io_core_commit_uops_0_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_ctrl_br_type_0 = io_core_commit_uops_0_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_ctrl_op1_sel_0 = io_core_commit_uops_0_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_op2_sel_0 = io_core_commit_uops_0_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_imm_sel_0 = io_core_commit_uops_0_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ctrl_op_fcn_0 = io_core_commit_uops_0_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_fcn_dw_0 = io_core_commit_uops_0_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_0_ctrl_csr_cmd_0 = io_core_commit_uops_0_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_load_0 = io_core_commit_uops_0_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_sta_0 = io_core_commit_uops_0_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ctrl_is_std_0 = io_core_commit_uops_0_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_iw_state_0 = io_core_commit_uops_0_iw_state; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p1_poisoned_0 = io_core_commit_uops_0_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_iw_p2_poisoned_0 = io_core_commit_uops_0_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_br_0 = io_core_commit_uops_0_is_br; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jalr_0 = io_core_commit_uops_0_is_jalr; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_jal_0 = io_core_commit_uops_0_is_jal; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:201:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:201:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:201:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_commit_uops_0_csr_addr_0 = io_core_commit_uops_0_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:201:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:201:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bypassable_0 = io_core_commit_uops_0_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:201:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:201:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:201:7] wire io_core_commit_uops_0_ldst_val_0 = io_core_commit_uops_0_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:201:7] wire io_core_commit_uops_0_fp_single_0 = io_core_commit_uops_0_fp_single; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:201:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_uopc_0 = io_core_commit_uops_1_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_1_iq_type_0 = io_core_commit_uops_1_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_commit_uops_1_fu_code_0 = io_core_commit_uops_1_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_1_ctrl_br_type_0 = io_core_commit_uops_1_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_ctrl_op1_sel_0 = io_core_commit_uops_1_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_1_ctrl_op2_sel_0 = io_core_commit_uops_1_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_1_ctrl_imm_sel_0 = io_core_commit_uops_1_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_ctrl_op_fcn_0 = io_core_commit_uops_1_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ctrl_fcn_dw_0 = io_core_commit_uops_1_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_1_ctrl_csr_cmd_0 = io_core_commit_uops_1_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ctrl_is_load_0 = io_core_commit_uops_1_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ctrl_is_sta_0 = io_core_commit_uops_1_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ctrl_is_std_0 = io_core_commit_uops_1_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_iw_state_0 = io_core_commit_uops_1_iw_state; // @[lsu.scala:201:7] wire io_core_commit_uops_1_iw_p1_poisoned_0 = io_core_commit_uops_1_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_1_iw_p2_poisoned_0 = io_core_commit_uops_1_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_br_0 = io_core_commit_uops_1_is_br; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_jalr_0 = io_core_commit_uops_1_is_jalr; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_jal_0 = io_core_commit_uops_1_is_jal; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:201:7] wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:201:7] wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:201:7] wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_commit_uops_1_csr_addr_0 = io_core_commit_uops_1_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:201:7] wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:201:7] wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:201:7] wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:201:7] wire io_core_commit_uops_1_bypassable_0 = io_core_commit_uops_1_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:201:7] wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:201:7] wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:201:7] wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:201:7] wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:201:7] wire io_core_commit_uops_1_ldst_val_0 = io_core_commit_uops_1_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:201:7] wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:201:7] wire io_core_commit_uops_1_fp_single_0 = io_core_commit_uops_1_fp_single; // @[lsu.scala:201:7] wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:201:7] wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_uopc_0 = io_core_commit_uops_2_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_2_inst_0 = io_core_commit_uops_2_inst; // @[lsu.scala:201:7] wire [31:0] io_core_commit_uops_2_debug_inst_0 = io_core_commit_uops_2_debug_inst; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_rvc_0 = io_core_commit_uops_2_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_commit_uops_2_debug_pc_0 = io_core_commit_uops_2_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_2_iq_type_0 = io_core_commit_uops_2_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_commit_uops_2_fu_code_0 = io_core_commit_uops_2_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_2_ctrl_br_type_0 = io_core_commit_uops_2_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_ctrl_op1_sel_0 = io_core_commit_uops_2_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_2_ctrl_op2_sel_0 = io_core_commit_uops_2_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_2_ctrl_imm_sel_0 = io_core_commit_uops_2_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_ctrl_op_fcn_0 = io_core_commit_uops_2_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ctrl_fcn_dw_0 = io_core_commit_uops_2_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_commit_uops_2_ctrl_csr_cmd_0 = io_core_commit_uops_2_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ctrl_is_load_0 = io_core_commit_uops_2_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ctrl_is_sta_0 = io_core_commit_uops_2_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ctrl_is_std_0 = io_core_commit_uops_2_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_iw_state_0 = io_core_commit_uops_2_iw_state; // @[lsu.scala:201:7] wire io_core_commit_uops_2_iw_p1_poisoned_0 = io_core_commit_uops_2_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_2_iw_p2_poisoned_0 = io_core_commit_uops_2_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_br_0 = io_core_commit_uops_2_is_br; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_jalr_0 = io_core_commit_uops_2_is_jalr; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_jal_0 = io_core_commit_uops_2_is_jal; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_sfb_0 = io_core_commit_uops_2_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_commit_uops_2_br_mask_0 = io_core_commit_uops_2_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_commit_uops_2_br_tag_0 = io_core_commit_uops_2_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_ftq_idx_0 = io_core_commit_uops_2_ftq_idx; // @[lsu.scala:201:7] wire io_core_commit_uops_2_edge_inst_0 = io_core_commit_uops_2_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_2_pc_lob_0 = io_core_commit_uops_2_pc_lob; // @[lsu.scala:201:7] wire io_core_commit_uops_2_taken_0 = io_core_commit_uops_2_taken; // @[lsu.scala:201:7] wire [19:0] io_core_commit_uops_2_imm_packed_0 = io_core_commit_uops_2_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_commit_uops_2_csr_addr_0 = io_core_commit_uops_2_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_rob_idx_0 = io_core_commit_uops_2_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_ldq_idx_0 = io_core_commit_uops_2_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_stq_idx_0 = io_core_commit_uops_2_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_rxq_idx_0 = io_core_commit_uops_2_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_pdst_0 = io_core_commit_uops_2_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_prs1_0 = io_core_commit_uops_2_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_prs2_0 = io_core_commit_uops_2_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_prs3_0 = io_core_commit_uops_2_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_ppred_0 = io_core_commit_uops_2_ppred; // @[lsu.scala:201:7] wire io_core_commit_uops_2_prs1_busy_0 = io_core_commit_uops_2_prs1_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_2_prs2_busy_0 = io_core_commit_uops_2_prs2_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_2_prs3_busy_0 = io_core_commit_uops_2_prs3_busy; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ppred_busy_0 = io_core_commit_uops_2_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_commit_uops_2_stale_pdst_0 = io_core_commit_uops_2_stale_pdst; // @[lsu.scala:201:7] wire io_core_commit_uops_2_exception_0 = io_core_commit_uops_2_exception; // @[lsu.scala:201:7] wire [63:0] io_core_commit_uops_2_exc_cause_0 = io_core_commit_uops_2_exc_cause; // @[lsu.scala:201:7] wire io_core_commit_uops_2_bypassable_0 = io_core_commit_uops_2_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_commit_uops_2_mem_cmd_0 = io_core_commit_uops_2_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_mem_size_0 = io_core_commit_uops_2_mem_size; // @[lsu.scala:201:7] wire io_core_commit_uops_2_mem_signed_0 = io_core_commit_uops_2_mem_signed; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_fence_0 = io_core_commit_uops_2_is_fence; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_fencei_0 = io_core_commit_uops_2_is_fencei; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_amo_0 = io_core_commit_uops_2_is_amo; // @[lsu.scala:201:7] wire io_core_commit_uops_2_uses_ldq_0 = io_core_commit_uops_2_uses_ldq; // @[lsu.scala:201:7] wire io_core_commit_uops_2_uses_stq_0 = io_core_commit_uops_2_uses_stq; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_sys_pc2epc_0 = io_core_commit_uops_2_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_commit_uops_2_is_unique_0 = io_core_commit_uops_2_is_unique; // @[lsu.scala:201:7] wire io_core_commit_uops_2_flush_on_commit_0 = io_core_commit_uops_2_flush_on_commit; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ldst_is_rs1_0 = io_core_commit_uops_2_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_2_ldst_0 = io_core_commit_uops_2_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_2_lrs1_0 = io_core_commit_uops_2_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_2_lrs2_0 = io_core_commit_uops_2_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_commit_uops_2_lrs3_0 = io_core_commit_uops_2_lrs3; // @[lsu.scala:201:7] wire io_core_commit_uops_2_ldst_val_0 = io_core_commit_uops_2_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_dst_rtype_0 = io_core_commit_uops_2_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_lrs1_rtype_0 = io_core_commit_uops_2_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_lrs2_rtype_0 = io_core_commit_uops_2_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_commit_uops_2_frs3_en_0 = io_core_commit_uops_2_frs3_en; // @[lsu.scala:201:7] wire io_core_commit_uops_2_fp_val_0 = io_core_commit_uops_2_fp_val; // @[lsu.scala:201:7] wire io_core_commit_uops_2_fp_single_0 = io_core_commit_uops_2_fp_single; // @[lsu.scala:201:7] wire io_core_commit_uops_2_xcpt_pf_if_0 = io_core_commit_uops_2_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_commit_uops_2_xcpt_ae_if_0 = io_core_commit_uops_2_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_commit_uops_2_xcpt_ma_if_0 = io_core_commit_uops_2_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_commit_uops_2_bp_debug_if_0 = io_core_commit_uops_2_bp_debug_if; // @[lsu.scala:201:7] wire io_core_commit_uops_2_bp_xcpt_if_0 = io_core_commit_uops_2_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_debug_fsrc_0 = io_core_commit_uops_2_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_commit_uops_2_debug_tsrc_0 = io_core_commit_uops_2_debug_tsrc; // @[lsu.scala:201:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:201:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:201:7] wire [31:0] io_core_commit_debug_insts_0_0 = io_core_commit_debug_insts_0; // @[lsu.scala:201:7] wire [31:0] io_core_commit_debug_insts_1_0 = io_core_commit_debug_insts_1; // @[lsu.scala:201:7] wire [31:0] io_core_commit_debug_insts_2_0 = io_core_commit_debug_insts_2; // @[lsu.scala:201:7] wire io_core_commit_rbk_valids_0_0 = io_core_commit_rbk_valids_0; // @[lsu.scala:201:7] wire io_core_commit_rbk_valids_1_0 = io_core_commit_rbk_valids_1; // @[lsu.scala:201:7] wire io_core_commit_rbk_valids_2_0 = io_core_commit_rbk_valids_2; // @[lsu.scala:201:7] wire io_core_commit_rollback_0 = io_core_commit_rollback; // @[lsu.scala:201:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:201:7] wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:201:7] wire [63:0] io_core_commit_debug_wdata_2_0 = io_core_commit_debug_wdata_2; // @[lsu.scala:201:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:201:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:201:7] wire [15:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:201:7] wire [15:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_core_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_core_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:201:7] wire io_core_brupdate_b2_valid_0 = io_core_brupdate_b2_valid; // @[lsu.scala:201:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:201:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:201:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:201:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:201:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:201:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:201:7] wire [6:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:201:7] wire [6:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:201:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:201:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:201:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:201:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_uopc_0 = io_dmem_resp_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_iq_type_0 = io_dmem_resp_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_resp_0_bits_uop_fu_code_0 = io_dmem_resp_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_ctrl_br_type_0 = io_dmem_resp_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_ctrl_op1_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_op2_sel_0 = io_dmem_resp_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_imm_sel_0 = io_dmem_resp_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ctrl_op_fcn_0 = io_dmem_resp_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_resp_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_resp_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_resp_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_load_0 = io_dmem_resp_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_sta_0 = io_dmem_resp_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ctrl_is_std_0 = io_dmem_resp_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_iw_state_0 = io_dmem_resp_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p1_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_iw_p2_poisoned_0 = io_dmem_resp_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_br_0 = io_dmem_resp_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jalr_0 = io_dmem_resp_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_jal_0 = io_dmem_resp_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_resp_0_bits_uop_csr_addr_0 = io_dmem_resp_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bypassable_0 = io_dmem_resp_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_ldst_val_0 = io_dmem_resp_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_fp_single_0 = io_dmem_resp_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_uopc_0 = io_dmem_nack_0_bits_uop_uopc; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:201:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_iq_type_0 = io_dmem_nack_0_bits_uop_iq_type; // @[lsu.scala:201:7] wire [9:0] io_dmem_nack_0_bits_uop_fu_code_0 = io_dmem_nack_0_bits_uop_fu_code; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_ctrl_br_type_0 = io_dmem_nack_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_ctrl_op1_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_op2_sel_0 = io_dmem_nack_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_imm_sel_0 = io_dmem_nack_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ctrl_op_fcn_0 = io_dmem_nack_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_fcn_dw_0 = io_dmem_nack_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7] wire [2:0] io_dmem_nack_0_bits_uop_ctrl_csr_cmd_0 = io_dmem_nack_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_load_0 = io_dmem_nack_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_sta_0 = io_dmem_nack_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ctrl_is_std_0 = io_dmem_nack_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_iw_state_0 = io_dmem_nack_0_bits_uop_iw_state; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p1_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_iw_p2_poisoned_0 = io_dmem_nack_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_br_0 = io_dmem_nack_0_bits_uop_is_br; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jalr_0 = io_dmem_nack_0_bits_uop_is_jalr; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_jal_0 = io_dmem_nack_0_bits_uop_is_jal; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:201:7] wire [15:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:201:7] wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:201:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:201:7] wire [11:0] io_dmem_nack_0_bits_uop_csr_addr_0 = io_dmem_nack_0_bits_uop_csr_addr; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:201:7] wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bypassable_0 = io_dmem_nack_0_bits_uop_bypassable; // @[lsu.scala:201:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:201:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_ldst_val_0 = io_dmem_nack_0_bits_uop_ldst_val; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_fp_single_0 = io_dmem_nack_0_bits_uop_fp_single; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7] wire [1:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:201:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:201:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:201:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:201:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:201:7] wire [2:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:201:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:201:7] wire [127:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:201:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:201:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:201:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:201:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:201:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:201:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:201:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:201:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:201:7] wire [15:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:383:33] wire [15:0] exe_req_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[lsu.scala:383:25] wire [15:0] exe_tlb_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] exe_tlb_uop_uop_1_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] _exe_tlb_uop_T_3_br_mask = 16'h0; // @[lsu.scala:602:24] wire [15:0] dmem_req_0_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [15:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:918:90] wire [15:0] _mem_stq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:922:89] wire [15:0] lcam_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_0_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_1_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_2_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_3_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_4_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_5_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_6_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_7_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_8_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_9_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_10_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_11_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_12_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_13_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_14_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_15_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_16_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_17_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_18_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_19_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_20_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_21_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_22_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] stq_23_bits_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:201:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:201:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:201:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ppred_busy_0 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_predicated = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_valid = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:201:7] wire io_core_dis_uops_0_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_dis_uops_1_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_dis_uops_2_bits_ppred_busy = 1'h0; // @[lsu.scala:201:7] wire io_core_clr_unsafe_0_valid = 1'h0; // @[lsu.scala:201:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_dv = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_resp_bits_has_data = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire io_hellacache_clock_enabled = 1'h0; // @[lsu.scala:201:7] wire _exe_req_WIRE_0_bits_predicated = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:33] wire _exe_req_WIRE_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:33] wire exe_req_0_bits_predicated = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_valid = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_br = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_taken = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_exception = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hv = 1'h0; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_hg = 1'h0; // @[lsu.scala:383:25] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_16 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_17 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_18 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_19 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_20 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_21 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_22 = 1'h0; // @[lsu.scala:396:44] wire _block_load_mask_WIRE_23 = 1'h0; // @[lsu.scala:396:44] wire ldq_incoming_e_0_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:263:49] wire _can_fire_sta_retry_T_4 = 1'h0; // @[lsu.scala:482:75] wire _can_fire_sta_retry_T_6 = 1'h0; // @[lsu.scala:483:75] wire _can_fire_sta_retry_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire _will_fire_load_incoming_0_will_fire_T = 1'h0; // @[lsu.scala:533:51] wire _will_fire_load_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_incoming_0_will_fire_T_4 = 1'h0; // @[lsu.scala:534:52] wire _will_fire_load_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_load_incoming_0_will_fire_T_8 = 1'h0; // @[lsu.scala:535:50] wire _will_fire_load_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_load_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_load_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_stad_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_stad_incoming_0_will_fire_T_12 = 1'h0; // @[lsu.scala:536:51] wire _will_fire_stad_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_stad_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sta_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_std_incoming_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_std_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_std_incoming_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_std_incoming_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_std_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_std_incoming_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_release_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_release_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_incoming_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_incoming_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_hella_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_hella_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_load_retry_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_retry_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_sta_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:535:47] wire _will_fire_sta_retry_0_T_6 = 1'h0; // @[lsu.scala:539:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_load_wakeup_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_load_wakeup_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire _will_fire_store_commit_0_will_fire_T_1 = 1'h0; // @[lsu.scala:533:48] wire _will_fire_store_commit_0_will_fire_T_5 = 1'h0; // @[lsu.scala:534:49] wire _will_fire_store_commit_0_will_fire_T_13 = 1'h0; // @[lsu.scala:536:48] wire _will_fire_store_commit_0_T = 1'h0; // @[lsu.scala:537:46] wire _will_fire_store_commit_0_T_3 = 1'h0; // @[lsu.scala:538:46] wire _will_fire_store_commit_0_T_9 = 1'h0; // @[lsu.scala:540:46] wire exe_tlb_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_br = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_taken = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_exception = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_tlb_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_tlb_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18] wire _exe_tlb_uop_T_3_is_rvc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_fcn_dw = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_load = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_sta = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ctrl_is_std = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p1_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_iw_p2_poisoned = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_br = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jalr = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_jal = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sfb = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_edge_inst = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_taken = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs1_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs2_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_prs3_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ppred_busy = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_exception = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bypassable = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_mem_signed = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fence = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_fencei = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_amo = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_ldq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_uses_stq = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_sys_pc2epc = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_is_unique = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_flush_on_commit = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_is_rs1 = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_ldst_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_frs3_en = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_val = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_fp_single = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_pf_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ae_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_xcpt_ma_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_debug_if = 1'h0; // @[lsu.scala:602:24] wire _exe_tlb_uop_T_3_bp_xcpt_if = 1'h0; // @[lsu.scala:602:24] wire _exe_sfence_WIRE_valid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs1 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_rs2 = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_asid = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hv = 1'h0; // @[lsu.scala:615:43] wire _exe_sfence_WIRE_bits_hg = 1'h0; // @[lsu.scala:615:43] wire exe_sfence_bits_hv = 1'h0; // @[lsu.scala:615:28] wire exe_sfence_bits_hg = 1'h0; // @[lsu.scala:615:28] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:709:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_16 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_17 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_18 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_19 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_20 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_21 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_22 = 1'h0; // @[lsu.scala:755:44] wire _s0_executing_loads_WIRE_23 = 1'h0; // @[lsu.scala:755:44] wire dmem_req_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire dmem_req_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire dmem_req_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = 1'h0; // @[util.scala:106:23] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:918:90] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:918:90] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_fcn_dw = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_load = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_sta = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ctrl_is_std = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p1_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_iw_p2_poisoned = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_br = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jalr = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_jal = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bypassable = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_ldst_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_fp_single = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:922:89] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:922:89] wire _clr_bsy_valid_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire lcam_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire lcam_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire lcam_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _ldst_addr_matches_WIRE_0 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_2 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_3 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_4 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_5 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_6 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_7 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_8 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_9 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_10 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_11 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_12 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_13 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_14 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_15 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_16 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_17 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_18 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_19 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_20 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_21 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_22 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_23 = 1'h0; // @[lsu.scala:1050:60] wire _ldst_addr_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_8 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_9 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_10 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_11 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_12 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_13 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_14 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_15 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_16 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_17 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_18 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_19 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_20 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_21 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_22 = 1'h0; // @[lsu.scala:263:49] wire _ldst_addr_matches_WIRE_1_0_23 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_0 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_2 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_3 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_4 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_5 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_6 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_7 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_8 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_9 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_10 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_11 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_12 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_13 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_14 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_15 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_16 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_17 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_18 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_19 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_20 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_21 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_22 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_23 = 1'h0; // @[lsu.scala:1052:60] wire _ldst_forward_matches_WIRE_1_0_0 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_1 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_2 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_3 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_4 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_5 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_6 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_7 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_8 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_9 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_10 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_11 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_12 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_13 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_14 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_15 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_16 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_17 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_18 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_19 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_20 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_21 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_22 = 1'h0; // @[lsu.scala:263:49] wire _ldst_forward_matches_WIRE_1_0_23 = 1'h0; // @[lsu.scala:263:49] wire _failed_loads_WIRE_0 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_1 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_2 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_3 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_4 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_5 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_6 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_7 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_8 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_9 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_10 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_11 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_12 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_13 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_14 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_15 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_16 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_17 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_18 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_19 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_20 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_21 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_22 = 1'h0; // @[lsu.scala:1054:42] wire _failed_loads_WIRE_23 = 1'h0; // @[lsu.scala:1054:42] wire _nacking_loads_WIRE_0 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_1 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_2 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_3 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_4 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_5 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_6 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_7 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_8 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_9 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_10 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_11 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_12 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_13 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_14 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_15 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_16 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_17 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_18 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_19 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_20 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_21 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_22 = 1'h0; // @[lsu.scala:1055:42] wire _nacking_loads_WIRE_23 = 1'h0; // @[lsu.scala:1055:42] wire _searcher_is_older_T = 1'h0; // @[util.scala:363:52] wire _io_core_clr_unsafe_0_valid_T_3 = 1'h0; // @[lsu.scala:1221:107] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:263:49] wire io_core_exe_0_iresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_iresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_core_exe_0_fresp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_bits_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1528:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1528:44] wire _st_exc_killed_mask_WIRE_0 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_1 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_2 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_3 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_4 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_5 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_6 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_7 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_8 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_9 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_10 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_11 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_12 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_13 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_14 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_15 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_16 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_17 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_18 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_19 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_20 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_21 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_22 = 1'h0; // @[lsu.scala:1598:44] wire _st_exc_killed_mask_WIRE_23 = 1'h0; // @[lsu.scala:1598:44] wire stq_0_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_0_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_0_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_1_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_1_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_2_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_2_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_3_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_3_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_4_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_4_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_5_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_5_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_6_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_6_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_7_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_7_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_8_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_8_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_8_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_8_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_8_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_9_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_9_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_9_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_9_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_9_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_10_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_10_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_10_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_10_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_10_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_11_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_11_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_11_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_11_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_11_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_12_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_12_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_12_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_12_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_12_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_13_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_13_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_13_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_13_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_13_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_14_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_14_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_14_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_14_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_14_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_15_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_15_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_15_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_15_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_15_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_16_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_16_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_16_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_16_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_16_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_17_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_17_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_17_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_17_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_17_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_18_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_18_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_18_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_18_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_18_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_19_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_19_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_19_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_19_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_19_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_20_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_20_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_20_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_20_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_20_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_21_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_21_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_21_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_21_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_21_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_22_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_22_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_22_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_22_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_22_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire stq_23_bits_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire stq_23_bits_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire stq_23_bits_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire stq_23_bits_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire stq_23_bits_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:201:7] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_dprv = 2'h0; // @[lsu.scala:201:7] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:33] wire [1:0] exe_req_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_req_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:383:25] wire [1:0] exe_tlb_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] exe_tlb_uop_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _exe_tlb_uop_T_3_ctrl_op1_sel = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_iw_state = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_mem_size = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_fsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] _exe_tlb_uop_T_3_debug_tsrc = 2'h0; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] dmem_req_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:918:90] wire [1:0] _mem_stq_e_WIRE_bits_uop_ctrl_op1_sel = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_iw_state = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 2'h0; // @[lsu.scala:922:89] wire [1:0] lcam_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] lcam_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_0_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_1_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_2_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_3_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_4_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_5_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_6_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_7_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_8_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_9_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_10_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_11_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_12_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_13_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_14_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_15_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_16_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_17_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_18_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_19_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_20_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_21_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_22_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] stq_23_bits_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:201:7] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:383:33] wire [6:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:383:33] wire [6:0] exe_req_0_bits_fflags_bits_uop_uopc = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_pdst = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_req_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:383:25] wire [6:0] exe_tlb_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_tlb_uop_uop_1_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] _exe_tlb_uop_T_3_uopc = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_rob_idx = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_pdst = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_prs1 = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_prs2 = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_prs3 = 7'h0; // @[lsu.scala:602:24] wire [6:0] _exe_tlb_uop_T_3_stale_pdst = 7'h0; // @[lsu.scala:602:24] wire [6:0] dmem_req_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] dmem_req_0_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] _mem_ldq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:918:90] wire [6:0] _mem_stq_e_WIRE_bits_uop_uopc = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:922:89] wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:922:89] wire [6:0] lcam_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] lcam_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_0_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_1_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_2_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_3_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_4_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_5_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_6_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_7_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_8_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_9_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_10_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_11_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_12_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_13_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_14_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_15_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_16_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_17_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_18_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_19_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_20_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_21_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_22_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] stq_23_bits_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ppred_0 = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_0_bits_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_1_bits_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_uops_2_bits_ppred = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:201:7] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:33] wire [4:0] _exe_req_WIRE_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:33] wire [4:0] exe_req_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_ppred = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:383:25] wire [4:0] exe_req_0_bits_fflags_bits_flags = 5'h0; // @[lsu.scala:383:25] wire [4:0] ldq_incoming_e_0_bits_uop_ppred = 5'h0; // @[lsu.scala:263:49] wire [4:0] exe_tlb_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] exe_tlb_uop_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_tlb_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] _exe_tlb_uop_T_3_ctrl_op_fcn = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_ftq_idx = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_ldq_idx = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_stq_idx = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_ppred = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = 5'h0; // @[lsu.scala:602:24] wire [4:0] _exe_cmd_T_5 = 5'h0; // @[lsu.scala:638:23] wire [4:0] dmem_req_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] dmem_req_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = 5'h0; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = 5'h0; // @[util.scala:106:23] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_youngest_stq_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 5'h0; // @[lsu.scala:918:90] wire [4:0] _mem_stq_e_WIRE_bits_uop_ctrl_op_fcn = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:922:89] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:922:89] wire [4:0] lcam_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] lcam_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_0_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_0_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_1_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_1_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_2_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_2_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_3_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_3_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_4_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_4_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_5_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_5_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_6_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_6_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_7_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_7_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_8_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_8_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_9_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_9_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_10_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_10_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_11_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_11_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_12_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_12_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_13_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_13_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_14_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_14_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_15_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_15_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_16_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_16_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_17_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_17_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_18_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_18_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_19_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_19_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_20_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_20_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_21_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_21_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_22_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_22_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] stq_23_bits_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] stq_23_bits_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:201:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire io_core_exe_0_iresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_ready = 1'h1; // @[lsu.scala:201:7] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:201:7] wire _can_fire_sta_retry_T_7 = 1'h1; // @[lsu.scala:482:34] wire _will_fire_load_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_load_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_load_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_incoming_0_T_11 = 1'h1; // @[lsu.scala:540:31] wire _will_fire_stad_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_stad_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_stad_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sta_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_std_incoming_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_std_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_std_incoming_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_std_incoming_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_std_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_std_incoming_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_release_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_release_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_incoming_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_incoming_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_hella_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_hella_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_load_retry_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_retry_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_sta_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:535:35] wire _will_fire_sta_retry_0_T_7 = 1'h1; // @[lsu.scala:539:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_load_wakeup_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_load_wakeup_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _will_fire_store_commit_0_will_fire_T_2 = 1'h1; // @[lsu.scala:533:35] wire _will_fire_store_commit_0_will_fire_T_6 = 1'h1; // @[lsu.scala:534:35] wire _will_fire_store_commit_0_will_fire_T_14 = 1'h1; // @[lsu.scala:536:35] wire _will_fire_store_commit_0_T_1 = 1'h1; // @[lsu.scala:537:34] wire _will_fire_store_commit_0_T_4 = 1'h1; // @[lsu.scala:538:34] wire _will_fire_store_commit_0_T_10 = 1'h1; // @[lsu.scala:540:34] wire _dmem_req_0_valid_T_8 = 1'h1; // @[lsu.scala:806:86] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_word_bypass = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_data_raw = 64'h0; // @[lsu.scala:201:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:201:7] wire [63:0] _exe_req_WIRE_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:33] wire [63:0] exe_req_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[lsu.scala:383:25] wire [63:0] exe_tlb_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] exe_tlb_uop_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _exe_tlb_uop_T_3_exc_cause = 64'h0; // @[lsu.scala:602:24] wire [63:0] dmem_req_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:918:90] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:922:89] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:922:89] wire [63:0] lcam_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_0_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_1_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_2_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_3_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_4_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_5_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_6_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_7_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_8_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_9_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_10_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_11_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_12_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_13_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_14_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_15_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_16_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_17_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_18_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_19_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_20_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_21_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_22_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] stq_23_bits_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:201:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:201:7] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:33] wire [3:0] _exe_req_WIRE_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:383:33] wire [3:0] exe_req_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_req_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[lsu.scala:383:25] wire [3:0] exe_tlb_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] exe_tlb_uop_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_uop_1_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_tlb_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] _exe_tlb_uop_T_3_ctrl_br_type = 4'h0; // @[lsu.scala:602:24] wire [3:0] _exe_tlb_uop_T_3_br_tag = 4'h0; // @[lsu.scala:602:24] wire [3:0] dmem_req_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] dmem_req_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] _mem_ldq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:918:90] wire [3:0] _mem_stq_e_WIRE_bits_uop_ctrl_br_type = 4'h0; // @[lsu.scala:922:89] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:922:89] wire [3:0] lcam_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] lcam_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_0_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_0_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_1_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_1_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_2_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_2_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_3_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_3_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_4_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_4_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_5_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_5_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_6_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_6_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_7_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_7_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_8_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_8_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_8_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_9_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_9_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_9_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_10_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_10_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_10_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_11_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_11_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_11_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_12_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_12_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_12_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_13_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_13_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_13_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_14_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_14_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_14_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_15_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_15_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_15_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_16_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_16_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_16_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_17_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_17_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_17_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_18_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_18_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_18_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_19_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_19_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_19_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_20_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_20_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_20_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_21_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_21_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_21_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_22_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_22_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_22_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] stq_23_bits_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_23_bits_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] stq_23_bits_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:201:7] wire [1:0] exe_tlb_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] exe_tlb_uop_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = 2'h2; // @[lsu.scala:602:24] wire [1:0] dmem_req_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] lcam_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_0_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_1_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_2_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_3_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_4_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_5_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_6_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_7_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_8_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_9_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_10_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_11_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_12_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_13_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_14_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_15_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_16_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_17_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_18_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_19_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_20_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_21_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_22_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] stq_23_bits_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:201:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:201:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:201:7] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:33] wire [5:0] _exe_req_WIRE_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:33] wire [5:0] exe_req_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_ldst = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_req_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[lsu.scala:383:25] wire [5:0] exe_tlb_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_tlb_uop_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _exe_tlb_uop_T_3_pc_lob = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_ldst = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs1 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs2 = 6'h0; // @[lsu.scala:602:24] wire [5:0] _exe_tlb_uop_T_3_lrs3 = 6'h0; // @[lsu.scala:602:24] wire [5:0] dmem_req_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] dmem_req_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:918:90] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:922:89] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:922:89] wire [5:0] lcam_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] lcam_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_0_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_1_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_2_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_3_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_4_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_5_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_6_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_7_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_8_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_8_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_8_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_8_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_8_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_9_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_9_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_9_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_9_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_9_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_10_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_10_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_10_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_10_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_10_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_11_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_11_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_11_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_11_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_11_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_12_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_12_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_12_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_12_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_12_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_13_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_13_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_13_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_13_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_13_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_14_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_14_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_14_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_14_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_14_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_15_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_15_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_15_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_15_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_15_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_16_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_16_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_16_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_16_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_16_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_17_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_17_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_17_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_17_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_17_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_18_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_18_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_18_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_18_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_18_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_19_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_19_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_19_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_19_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_19_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_20_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_20_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_20_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_20_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_20_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_21_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_21_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_21_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_21_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_21_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_22_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_22_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_22_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_22_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_22_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_23_bits_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_23_bits_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_23_bits_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_23_bits_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] stq_23_bits_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:201:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:201:7] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:33] wire [31:0] exe_req_0_bits_fflags_bits_uop_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_req_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[lsu.scala:383:25] wire [31:0] exe_tlb_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_tlb_uop_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _exe_tlb_uop_T_3_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] _exe_tlb_uop_T_3_debug_inst = 32'h0; // @[lsu.scala:602:24] wire [31:0] dmem_req_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] dmem_req_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:918:90] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:922:89] wire [31:0] lcam_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] lcam_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_0_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_1_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_2_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_3_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_4_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_5_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_6_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_7_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_8_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_8_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_9_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_9_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_10_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_10_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_11_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_11_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_12_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_12_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_13_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_13_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_14_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_14_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_15_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_15_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_16_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_16_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_17_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_17_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_18_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_18_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_19_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_19_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_20_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_20_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_21_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_21_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_22_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_22_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_23_bits_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] stq_23_bits_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [39:0] io_core_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:201:7] wire [39:0] _exe_req_WIRE_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:33] wire [39:0] exe_req_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[lsu.scala:383:25] wire [39:0] exe_tlb_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] exe_tlb_uop_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _exe_tlb_uop_T_3_debug_pc = 40'h0; // @[lsu.scala:602:24] wire [39:0] dmem_req_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:918:90] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:922:89] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:922:89] wire [39:0] lcam_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_0_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_1_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_2_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_3_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_4_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_5_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_6_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_7_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_8_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_9_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_10_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_11_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_12_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_13_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_14_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_15_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_16_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_17_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_18_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_19_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_20_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_21_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_22_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] stq_23_bits_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:201:7] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:33] wire [2:0] _exe_req_WIRE_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:33] wire [2:0] exe_req_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_req_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:383:25] wire [2:0] exe_tlb_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_uop_1_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_tlb_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_tlb_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _exe_tlb_uop_T_3_iq_type = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_op2_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_imm_sel = 3'h0; // @[lsu.scala:602:24] wire [2:0] _exe_tlb_uop_T_3_ctrl_csr_cmd = 3'h0; // @[lsu.scala:602:24] wire [2:0] dmem_req_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] dmem_req_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] dmem_req_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_ldq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:918:90] wire [2:0] _mem_stq_e_WIRE_bits_uop_iq_type = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_op2_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_imm_sel = 3'h0; // @[lsu.scala:922:89] wire [2:0] _mem_stq_e_WIRE_bits_uop_ctrl_csr_cmd = 3'h0; // @[lsu.scala:922:89] wire [2:0] lcam_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] lcam_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] lcam_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_0_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_0_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_1_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_1_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_2_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_2_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_3_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_3_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_4_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_4_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_5_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_5_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_6_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_6_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_7_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_7_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_8_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_8_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_8_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_8_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_8_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_8_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_8_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_9_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_9_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_9_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_9_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_9_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_9_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_9_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_10_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_10_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_10_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_10_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_10_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_10_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_10_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_11_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_11_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_11_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_11_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_11_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_11_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_11_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_12_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_12_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_12_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_12_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_12_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_12_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_12_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_13_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_13_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_13_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_13_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_13_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_13_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_13_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_14_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_14_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_14_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_14_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_14_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_14_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_14_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_15_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_15_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_15_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_15_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_15_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_15_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_15_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_16_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_16_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_16_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_16_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_16_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_16_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_16_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_17_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_17_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_17_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_17_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_17_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_17_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_17_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_18_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_18_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_18_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_18_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_18_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_18_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_18_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_19_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_19_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_19_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_19_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_19_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_19_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_19_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_20_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_20_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_20_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_20_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_20_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_20_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_20_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_21_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_21_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_21_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_21_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_21_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_21_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_21_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_22_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_22_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_22_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_22_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_22_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_22_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_22_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_23_bits_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_23_bits_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_23_bits_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_23_bits_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] stq_23_bits_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_23_bits_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] stq_23_bits_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [9:0] io_core_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:201:7] wire [9:0] _exe_req_WIRE_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:33] wire [9:0] exe_req_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[lsu.scala:383:25] wire [9:0] exe_tlb_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] exe_tlb_uop_uop_1_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _exe_tlb_uop_T_3_fu_code = 10'h0; // @[lsu.scala:602:24] wire [9:0] dmem_req_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] _mem_ldq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:918:90] wire [9:0] _mem_stq_e_WIRE_bits_uop_fu_code = 10'h0; // @[lsu.scala:922:89] wire [9:0] lcam_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_0_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_1_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_2_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_3_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_4_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_5_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_6_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_7_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_8_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_9_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_10_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_11_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_12_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_13_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_14_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_15_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_16_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_17_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_18_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_19_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_20_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_21_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_22_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] stq_23_bits_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [19:0] io_core_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:201:7] wire [19:0] _exe_req_WIRE_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:33] wire [19:0] exe_req_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[lsu.scala:383:25] wire [19:0] exe_tlb_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] exe_tlb_uop_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _exe_tlb_uop_T_3_imm_packed = 20'h0; // @[lsu.scala:602:24] wire [19:0] dmem_req_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:918:90] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:922:89] wire [19:0] lcam_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_0_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_1_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_2_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_3_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_4_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_5_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_6_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_7_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_8_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_9_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_10_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_11_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_12_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_13_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_14_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_15_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_16_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_17_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_18_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_19_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_20_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_21_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_22_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] stq_23_bits_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [11:0] io_core_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:201:7] wire [11:0] _exe_req_WIRE_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:33] wire [11:0] exe_req_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[lsu.scala:383:25] wire [11:0] exe_tlb_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] exe_tlb_uop_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _exe_tlb_uop_T_3_csr_addr = 12'h0; // @[lsu.scala:602:24] wire [11:0] dmem_req_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] _mem_ldq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:918:90] wire [11:0] _mem_stq_e_WIRE_bits_uop_csr_addr = 12'h0; // @[lsu.scala:922:89] wire [11:0] lcam_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_0_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_1_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_2_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_3_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_4_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_5_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_6_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_7_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_8_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_9_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_10_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_11_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_12_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_13_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_14_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_15_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_16_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_17_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_18_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_19_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_20_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_21_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_22_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] stq_23_bits_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _l_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16] wire [23:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 24'h0; // @[lsu.scala:918:90] wire [38:0] _exe_sfence_WIRE_bits_addr = 39'h0; // @[lsu.scala:615:43] wire _exe_req_WIRE_0_valid = io_core_exe_0_req_valid_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_uopc = io_core_exe_0_req_bits_uop_uopc_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_inst = io_core_exe_0_req_bits_uop_inst_0; // @[lsu.scala:201:7, :383:33] wire [31:0] _exe_req_WIRE_0_bits_uop_debug_inst = io_core_exe_0_req_bits_uop_debug_inst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_rvc = io_core_exe_0_req_bits_uop_is_rvc_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_uop_debug_pc = io_core_exe_0_req_bits_uop_debug_pc_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_iq_type = io_core_exe_0_req_bits_uop_iq_type_0; // @[lsu.scala:201:7, :383:33] wire [9:0] _exe_req_WIRE_0_bits_uop_fu_code = io_core_exe_0_req_bits_uop_fu_code_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7, :383:33] wire [2:0] _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_iw_state = io_core_exe_0_req_bits_uop_iw_state_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_br = io_core_exe_0_req_bits_uop_is_br_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jalr = io_core_exe_0_req_bits_uop_is_jalr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_jal = io_core_exe_0_req_bits_uop_is_jal_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sfb = io_core_exe_0_req_bits_uop_is_sfb_0; // @[lsu.scala:201:7, :383:33] wire [15:0] _exe_req_WIRE_0_bits_uop_br_mask = io_core_exe_0_req_bits_uop_br_mask_0; // @[lsu.scala:201:7, :383:33] wire [3:0] _exe_req_WIRE_0_bits_uop_br_tag = io_core_exe_0_req_bits_uop_br_tag_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_uop_ftq_idx_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_edge_inst = io_core_exe_0_req_bits_uop_edge_inst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_pc_lob = io_core_exe_0_req_bits_uop_pc_lob_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_taken = io_core_exe_0_req_bits_uop_taken_0; // @[lsu.scala:201:7, :383:33] wire [19:0] _exe_req_WIRE_0_bits_uop_imm_packed = io_core_exe_0_req_bits_uop_imm_packed_0; // @[lsu.scala:201:7, :383:33] wire [11:0] _exe_req_WIRE_0_bits_uop_csr_addr = io_core_exe_0_req_bits_uop_csr_addr_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_rob_idx = io_core_exe_0_req_bits_uop_rob_idx_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_uop_ldq_idx_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_stq_idx = io_core_exe_0_req_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_uop_rxq_idx_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_pdst = io_core_exe_0_req_bits_uop_pdst_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_prs1 = io_core_exe_0_req_bits_uop_prs1_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_prs2 = io_core_exe_0_req_bits_uop_prs2_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_prs3 = io_core_exe_0_req_bits_uop_prs3_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_ppred = io_core_exe_0_req_bits_uop_ppred_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_uop_prs1_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_uop_prs2_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_uop_prs3_busy_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_uop_ppred_busy_0; // @[lsu.scala:201:7, :383:33] wire [6:0] _exe_req_WIRE_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_uop_stale_pdst_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_exception = io_core_exe_0_req_bits_uop_exception_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_uop_exc_cause = io_core_exe_0_req_bits_uop_exc_cause_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bypassable = io_core_exe_0_req_bits_uop_bypassable_0; // @[lsu.scala:201:7, :383:33] wire [4:0] _exe_req_WIRE_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_uop_mem_cmd_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_mem_size = io_core_exe_0_req_bits_uop_mem_size_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_mem_signed = io_core_exe_0_req_bits_uop_mem_signed_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fence = io_core_exe_0_req_bits_uop_is_fence_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_fencei = io_core_exe_0_req_bits_uop_is_fencei_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_amo = io_core_exe_0_req_bits_uop_is_amo_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_uses_stq = io_core_exe_0_req_bits_uop_uses_stq_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_is_unique = io_core_exe_0_req_bits_uop_is_unique_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_ldst = io_core_exe_0_req_bits_uop_ldst_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs1 = io_core_exe_0_req_bits_uop_lrs1_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs2 = io_core_exe_0_req_bits_uop_lrs2_0; // @[lsu.scala:201:7, :383:33] wire [5:0] _exe_req_WIRE_0_bits_uop_lrs3 = io_core_exe_0_req_bits_uop_lrs3_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_ldst_val = io_core_exe_0_req_bits_uop_ldst_val_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_uop_dst_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_frs3_en = io_core_exe_0_req_bits_uop_frs3_en_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_val = io_core_exe_0_req_bits_uop_fp_val_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_fp_single = io_core_exe_0_req_bits_uop_fp_single_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7, :383:33] wire [1:0] _exe_req_WIRE_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7, :383:33] wire [63:0] _exe_req_WIRE_0_bits_data = io_core_exe_0_req_bits_data_0; // @[lsu.scala:201:7, :383:33] wire [39:0] _exe_req_WIRE_0_bits_addr = io_core_exe_0_req_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_mxcpt_valid = io_core_exe_0_req_bits_mxcpt_valid_0; // @[lsu.scala:201:7, :383:33] wire [24:0] _exe_req_WIRE_0_bits_mxcpt_bits = io_core_exe_0_req_bits_mxcpt_bits_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_bits_rs1_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_bits_rs2_0; // @[lsu.scala:201:7, :383:33] wire [38:0] _exe_req_WIRE_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_bits_addr_0; // @[lsu.scala:201:7, :383:33] wire _exe_req_WIRE_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_bits_asid_0; // @[lsu.scala:201:7, :383:33] wire _io_core_fp_stdata_ready_T_2; // @[lsu.scala:867:61] wire [6:0] mem_stdf_uop_out_uopc = io_core_fp_stdata_bits_uop_uopc_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_inst = io_core_fp_stdata_bits_uop_inst_0; // @[util.scala:96:23] wire [31:0] mem_stdf_uop_out_debug_inst = io_core_fp_stdata_bits_uop_debug_inst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_rvc = io_core_fp_stdata_bits_uop_is_rvc_0; // @[util.scala:96:23] wire [39:0] mem_stdf_uop_out_debug_pc = io_core_fp_stdata_bits_uop_debug_pc_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_iq_type = io_core_fp_stdata_bits_uop_iq_type_0; // @[util.scala:96:23] wire [9:0] mem_stdf_uop_out_fu_code = io_core_fp_stdata_bits_uop_fu_code_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_ctrl_br_type = io_core_fp_stdata_bits_uop_ctrl_br_type_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_ctrl_op1_sel = io_core_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_op2_sel = io_core_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_imm_sel = io_core_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ctrl_op_fcn = io_core_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_fcn_dw = io_core_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[util.scala:96:23] wire [2:0] mem_stdf_uop_out_ctrl_csr_cmd = io_core_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_load = io_core_fp_stdata_bits_uop_ctrl_is_load_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_sta = io_core_fp_stdata_bits_uop_ctrl_is_sta_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ctrl_is_std = io_core_fp_stdata_bits_uop_ctrl_is_std_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_iw_state = io_core_fp_stdata_bits_uop_iw_state_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p1_poisoned = io_core_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_iw_p2_poisoned = io_core_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_br = io_core_fp_stdata_bits_uop_is_br_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jalr = io_core_fp_stdata_bits_uop_is_jalr_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_jal = io_core_fp_stdata_bits_uop_is_jal_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sfb = io_core_fp_stdata_bits_uop_is_sfb_0; // @[util.scala:96:23] wire [3:0] mem_stdf_uop_out_br_tag = io_core_fp_stdata_bits_uop_br_tag_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ftq_idx = io_core_fp_stdata_bits_uop_ftq_idx_0; // @[util.scala:96:23] wire mem_stdf_uop_out_edge_inst = io_core_fp_stdata_bits_uop_edge_inst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_pc_lob = io_core_fp_stdata_bits_uop_pc_lob_0; // @[util.scala:96:23] wire mem_stdf_uop_out_taken = io_core_fp_stdata_bits_uop_taken_0; // @[util.scala:96:23] wire [19:0] mem_stdf_uop_out_imm_packed = io_core_fp_stdata_bits_uop_imm_packed_0; // @[util.scala:96:23] wire [11:0] mem_stdf_uop_out_csr_addr = io_core_fp_stdata_bits_uop_csr_addr_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_rob_idx = io_core_fp_stdata_bits_uop_rob_idx_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ldq_idx = io_core_fp_stdata_bits_uop_ldq_idx_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_stq_idx = io_core_fp_stdata_bits_uop_stq_idx_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_rxq_idx = io_core_fp_stdata_bits_uop_rxq_idx_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_pdst = io_core_fp_stdata_bits_uop_pdst_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_prs1 = io_core_fp_stdata_bits_uop_prs1_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_prs2 = io_core_fp_stdata_bits_uop_prs2_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_prs3 = io_core_fp_stdata_bits_uop_prs3_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_ppred = io_core_fp_stdata_bits_uop_ppred_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs1_busy = io_core_fp_stdata_bits_uop_prs1_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs2_busy = io_core_fp_stdata_bits_uop_prs2_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_prs3_busy = io_core_fp_stdata_bits_uop_prs3_busy_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ppred_busy = io_core_fp_stdata_bits_uop_ppred_busy_0; // @[util.scala:96:23] wire [6:0] mem_stdf_uop_out_stale_pdst = io_core_fp_stdata_bits_uop_stale_pdst_0; // @[util.scala:96:23] wire mem_stdf_uop_out_exception = io_core_fp_stdata_bits_uop_exception_0; // @[util.scala:96:23] wire [63:0] mem_stdf_uop_out_exc_cause = io_core_fp_stdata_bits_uop_exc_cause_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bypassable = io_core_fp_stdata_bits_uop_bypassable_0; // @[util.scala:96:23] wire [4:0] mem_stdf_uop_out_mem_cmd = io_core_fp_stdata_bits_uop_mem_cmd_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_mem_size = io_core_fp_stdata_bits_uop_mem_size_0; // @[util.scala:96:23] wire mem_stdf_uop_out_mem_signed = io_core_fp_stdata_bits_uop_mem_signed_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fence = io_core_fp_stdata_bits_uop_is_fence_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_fencei = io_core_fp_stdata_bits_uop_is_fencei_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_amo = io_core_fp_stdata_bits_uop_is_amo_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_ldq = io_core_fp_stdata_bits_uop_uses_ldq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_uses_stq = io_core_fp_stdata_bits_uop_uses_stq_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_sys_pc2epc = io_core_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[util.scala:96:23] wire mem_stdf_uop_out_is_unique = io_core_fp_stdata_bits_uop_is_unique_0; // @[util.scala:96:23] wire mem_stdf_uop_out_flush_on_commit = io_core_fp_stdata_bits_uop_flush_on_commit_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_is_rs1 = io_core_fp_stdata_bits_uop_ldst_is_rs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_ldst = io_core_fp_stdata_bits_uop_ldst_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs1 = io_core_fp_stdata_bits_uop_lrs1_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs2 = io_core_fp_stdata_bits_uop_lrs2_0; // @[util.scala:96:23] wire [5:0] mem_stdf_uop_out_lrs3 = io_core_fp_stdata_bits_uop_lrs3_0; // @[util.scala:96:23] wire mem_stdf_uop_out_ldst_val = io_core_fp_stdata_bits_uop_ldst_val_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_dst_rtype = io_core_fp_stdata_bits_uop_dst_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs1_rtype = io_core_fp_stdata_bits_uop_lrs1_rtype_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_lrs2_rtype = io_core_fp_stdata_bits_uop_lrs2_rtype_0; // @[util.scala:96:23] wire mem_stdf_uop_out_frs3_en = io_core_fp_stdata_bits_uop_frs3_en_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_val = io_core_fp_stdata_bits_uop_fp_val_0; // @[util.scala:96:23] wire mem_stdf_uop_out_fp_single = io_core_fp_stdata_bits_uop_fp_single_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_pf_if = io_core_fp_stdata_bits_uop_xcpt_pf_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ae_if = io_core_fp_stdata_bits_uop_xcpt_ae_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_xcpt_ma_if = io_core_fp_stdata_bits_uop_xcpt_ma_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_debug_if = io_core_fp_stdata_bits_uop_bp_debug_if_0; // @[util.scala:96:23] wire mem_stdf_uop_out_bp_xcpt_if = io_core_fp_stdata_bits_uop_bp_xcpt_if_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_fsrc = io_core_fp_stdata_bits_uop_debug_fsrc_0; // @[util.scala:96:23] wire [1:0] mem_stdf_uop_out_debug_tsrc = io_core_fp_stdata_bits_uop_debug_tsrc_0; // @[util.scala:96:23] wire _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:980:82] wire _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:1005:87] wire _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:1261:69] wire [15:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:201:7] wire [15:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_uopc_0 = io_core_brupdate_b2_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_iq_type_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_brupdate_b2_uop_fu_code_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_ctrl_br_type_0 = io_core_brupdate_b2_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_ctrl_op1_sel_0 = io_core_brupdate_b2_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_op2_sel_0 = io_core_brupdate_b2_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_imm_sel_0 = io_core_brupdate_b2_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ctrl_op_fcn_0 = io_core_brupdate_b2_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_fcn_dw_0 = io_core_brupdate_b2_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_uop_ctrl_csr_cmd_0 = io_core_brupdate_b2_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_load_0 = io_core_brupdate_b2_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_sta_0 = io_core_brupdate_b2_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ctrl_is_std_0 = io_core_brupdate_b2_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_iw_state_0 = io_core_brupdate_b2_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p1_poisoned_0 = io_core_brupdate_b2_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_iw_p2_poisoned_0 = io_core_brupdate_b2_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_br_0 = io_core_brupdate_b2_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jalr_0 = io_core_brupdate_b2_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_jal_0 = io_core_brupdate_b2_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:201:7] wire [15:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_brupdate_b2_uop_csr_addr_0 = io_core_brupdate_b2_uop_csr_addr_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bypassable_0 = io_core_brupdate_b2_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_ldst_val_0 = io_core_brupdate_b2_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_fp_single_0 = io_core_brupdate_b2_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_valid_0 = io_core_brupdate_b2_valid_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:201:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:201:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:201:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:201:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:347:42] wire _io_core_lxcpt_valid_T_5; // @[lsu.scala:1254:61] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_uopc; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:750:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_iq_type; // @[lsu.scala:750:22] wire [9:0] dmem_req_0_bits_uop_fu_code; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:750:22] wire [2:0] dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_iw_state; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_br; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_jal; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:750:22] wire [15:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:750:22] wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:750:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:750:22] wire [11:0] dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:750:22] wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bypassable; // @[lsu.scala:750:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:750:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_fp_single; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:750:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:750:22] wire [1:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:750:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:750:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:750:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:750:22] wire [63:0] io_hellacache_resp_bits_data_0 = io_dmem_resp_0_bits_data_0; // @[lsu.scala:201:7] wire will_fire_release_0; // @[lsu.scala:377:38] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:201:7, :459:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:201:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:201:7] wire _io_hellacache_store_pending_T_22; // @[lsu.scala:1530:59] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:201:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:201:7] wire io_ptw_req_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_iresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_iresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_iresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_iresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_iresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_iresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_iresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_iresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_iresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_iresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_iresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_iresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_iresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_iresp_valid_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_exe_0_fresp_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_exe_0_fresp_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_exe_0_fresp_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_exe_0_fresp_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [15:0] io_core_exe_0_fresp_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [3:0] io_core_exe_0_fresp_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_exe_0_fresp_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_exe_0_fresp_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_prs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire [6:0] io_core_exe_0_fresp_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_exe_0_fresp_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_exe_0_fresp_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_exe_0_fresp_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_exe_0_fresp_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [64:0] io_core_exe_0_fresp_bits_data_0; // @[lsu.scala:201:7] wire io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_ldq_idx_2_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:201:7] wire [4:0] io_core_dis_stq_idx_2_0; // @[lsu.scala:201:7] wire io_core_ldq_full_0_0; // @[lsu.scala:201:7] wire io_core_ldq_full_1_0; // @[lsu.scala:201:7] wire io_core_ldq_full_2_0; // @[lsu.scala:201:7] wire io_core_stq_full_0_0; // @[lsu.scala:201:7] wire io_core_stq_full_1_0; // @[lsu.scala:201:7] wire io_core_stq_full_2_0; // @[lsu.scala:201:7] wire io_core_fp_stdata_ready_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:201:7] wire [6:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:201:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:201:7] wire [6:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:201:7] wire [6:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:201:7] wire io_core_spec_ld_wakeup_0_valid_0; // @[lsu.scala:201:7] wire [6:0] io_core_spec_ld_wakeup_0_bits_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_core_lxcpt_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_core_lxcpt_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [15:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_core_lxcpt_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:201:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:201:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:201:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:201:7] wire io_core_ld_miss_0; // @[lsu.scala:201:7] wire io_core_fencei_rdy_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_load_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ctrl_is_std_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_uopc_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:201:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:201:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iq_type_0; // @[lsu.scala:201:7] wire [9:0] io_dmem_req_bits_0_bits_uop_fu_code_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_iw_state_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_br_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jalr_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_jal_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:201:7] wire [15:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:201:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:201:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:201:7] wire [11:0] io_dmem_req_bits_0_bits_uop_csr_addr_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:201:7] wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bypassable_0; // @[lsu.scala:201:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:201:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_ldst_val_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_fp_single_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:201:7] wire [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:201:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:201:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:201:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:201:7] wire io_dmem_req_valid_0; // @[lsu.scala:201:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:201:7] wire io_dmem_release_ready_0; // @[lsu.scala:201:7] wire io_dmem_force_order_0; // @[lsu.scala:201:7] wire io_hellacache_req_ready_0; // @[lsu.scala:201:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:201:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:201:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:201:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:201:7] wire io_hellacache_store_pending_0; // @[lsu.scala:201:7] reg ldq_0_valid; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_0_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_0_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_0_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_0_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_0_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_0_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_0_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_0_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_0_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_0_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_0_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_0_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_0_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_0_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_0_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_0_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_0_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_0_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_0_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_0_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_0_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_0_bits_executed; // @[lsu.scala:208:16] reg ldq_0_bits_succeeded; // @[lsu.scala:208:16] reg ldq_0_bits_order_fail; // @[lsu.scala:208:16] reg ldq_0_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_0_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_0_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_0_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_1_valid; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_1_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_1_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_1_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_1_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_1_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_1_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_1_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_1_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_1_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_1_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_1_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_1_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_1_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_1_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_1_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_1_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_1_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_1_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_1_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_1_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_1_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_1_bits_executed; // @[lsu.scala:208:16] reg ldq_1_bits_succeeded; // @[lsu.scala:208:16] reg ldq_1_bits_order_fail; // @[lsu.scala:208:16] reg ldq_1_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_1_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_1_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_1_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_2_valid; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_2_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_2_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_2_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_2_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_2_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_2_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_2_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_2_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_2_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_2_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_2_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_2_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_2_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_2_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_2_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_2_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_2_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_2_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_2_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_2_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_2_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_2_bits_executed; // @[lsu.scala:208:16] reg ldq_2_bits_succeeded; // @[lsu.scala:208:16] reg ldq_2_bits_order_fail; // @[lsu.scala:208:16] reg ldq_2_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_2_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_2_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_2_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_3_valid; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_3_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_3_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_3_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_3_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_3_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_3_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_3_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_3_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_3_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_3_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_3_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_3_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_3_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_3_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_3_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_3_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_3_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_3_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_3_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_3_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_3_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_3_bits_executed; // @[lsu.scala:208:16] reg ldq_3_bits_succeeded; // @[lsu.scala:208:16] reg ldq_3_bits_order_fail; // @[lsu.scala:208:16] reg ldq_3_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_3_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_3_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_3_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_4_valid; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_4_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_4_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_4_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_4_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_4_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_4_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_4_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_4_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_4_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_4_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_4_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_4_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_4_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_4_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_4_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_4_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_4_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_4_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_4_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_4_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_4_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_4_bits_executed; // @[lsu.scala:208:16] reg ldq_4_bits_succeeded; // @[lsu.scala:208:16] reg ldq_4_bits_order_fail; // @[lsu.scala:208:16] reg ldq_4_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_4_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_4_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_4_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_5_valid; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_5_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_5_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_5_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_5_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_5_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_5_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_5_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_5_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_5_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_5_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_5_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_5_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_5_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_5_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_5_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_5_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_5_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_5_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_5_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_5_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_5_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_5_bits_executed; // @[lsu.scala:208:16] reg ldq_5_bits_succeeded; // @[lsu.scala:208:16] reg ldq_5_bits_order_fail; // @[lsu.scala:208:16] reg ldq_5_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_5_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_5_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_5_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_6_valid; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_6_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_6_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_6_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_6_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_6_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_6_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_6_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_6_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_6_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_6_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_6_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_6_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_6_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_6_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_6_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_6_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_6_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_6_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_6_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_6_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_6_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_6_bits_executed; // @[lsu.scala:208:16] reg ldq_6_bits_succeeded; // @[lsu.scala:208:16] reg ldq_6_bits_order_fail; // @[lsu.scala:208:16] reg ldq_6_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_6_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_6_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_6_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_7_valid; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_7_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_7_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_7_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_7_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_7_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_7_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_7_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_7_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_7_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_7_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_7_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_7_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_7_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_7_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_7_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_7_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_7_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_7_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_7_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_7_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_7_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_7_bits_executed; // @[lsu.scala:208:16] reg ldq_7_bits_succeeded; // @[lsu.scala:208:16] reg ldq_7_bits_order_fail; // @[lsu.scala:208:16] reg ldq_7_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_7_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_7_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_7_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_8_valid; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_8_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_8_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_8_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_8_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_8_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_8_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_8_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_8_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_8_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_8_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_8_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_8_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_8_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_8_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_8_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_8_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_8_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_8_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_8_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_8_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_8_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_8_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_8_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_8_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_8_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_8_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_8_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_8_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_8_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_8_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_8_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_8_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_8_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_8_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_8_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_8_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_8_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_8_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_8_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_8_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_8_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_8_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_8_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_8_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_8_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_8_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_8_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_8_bits_executed; // @[lsu.scala:208:16] reg ldq_8_bits_succeeded; // @[lsu.scala:208:16] reg ldq_8_bits_order_fail; // @[lsu.scala:208:16] reg ldq_8_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_8_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_8_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_8_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_8_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_9_valid; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_9_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_9_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_9_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_9_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_9_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_9_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_9_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_9_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_9_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_9_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_9_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_9_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_9_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_9_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_9_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_9_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_9_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_9_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_9_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_9_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_9_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_9_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_9_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_9_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_9_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_9_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_9_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_9_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_9_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_9_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_9_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_9_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_9_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_9_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_9_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_9_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_9_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_9_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_9_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_9_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_9_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_9_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_9_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_9_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_9_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_9_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_9_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_9_bits_executed; // @[lsu.scala:208:16] reg ldq_9_bits_succeeded; // @[lsu.scala:208:16] reg ldq_9_bits_order_fail; // @[lsu.scala:208:16] reg ldq_9_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_9_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_9_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_9_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_9_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_10_valid; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_10_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_10_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_10_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_10_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_10_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_10_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_10_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_10_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_10_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_10_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_10_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_10_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_10_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_10_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_10_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_10_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_10_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_10_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_10_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_10_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_10_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_10_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_10_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_10_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_10_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_10_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_10_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_10_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_10_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_10_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_10_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_10_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_10_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_10_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_10_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_10_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_10_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_10_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_10_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_10_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_10_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_10_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_10_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_10_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_10_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_10_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_10_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_10_bits_executed; // @[lsu.scala:208:16] reg ldq_10_bits_succeeded; // @[lsu.scala:208:16] reg ldq_10_bits_order_fail; // @[lsu.scala:208:16] reg ldq_10_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_10_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_10_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_10_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_10_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_11_valid; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_11_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_11_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_11_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_11_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_11_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_11_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_11_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_11_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_11_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_11_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_11_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_11_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_11_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_11_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_11_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_11_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_11_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_11_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_11_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_11_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_11_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_11_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_11_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_11_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_11_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_11_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_11_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_11_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_11_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_11_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_11_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_11_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_11_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_11_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_11_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_11_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_11_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_11_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_11_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_11_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_11_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_11_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_11_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_11_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_11_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_11_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_11_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_11_bits_executed; // @[lsu.scala:208:16] reg ldq_11_bits_succeeded; // @[lsu.scala:208:16] reg ldq_11_bits_order_fail; // @[lsu.scala:208:16] reg ldq_11_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_11_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_11_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_11_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_11_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_12_valid; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_12_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_12_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_12_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_12_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_12_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_12_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_12_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_12_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_12_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_12_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_12_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_12_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_12_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_12_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_12_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_12_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_12_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_12_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_12_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_12_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_12_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_12_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_12_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_12_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_12_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_12_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_12_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_12_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_12_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_12_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_12_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_12_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_12_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_12_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_12_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_12_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_12_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_12_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_12_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_12_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_12_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_12_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_12_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_12_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_12_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_12_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_12_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_12_bits_executed; // @[lsu.scala:208:16] reg ldq_12_bits_succeeded; // @[lsu.scala:208:16] reg ldq_12_bits_order_fail; // @[lsu.scala:208:16] reg ldq_12_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_12_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_12_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_12_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_12_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_13_valid; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_13_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_13_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_13_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_13_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_13_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_13_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_13_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_13_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_13_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_13_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_13_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_13_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_13_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_13_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_13_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_13_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_13_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_13_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_13_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_13_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_13_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_13_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_13_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_13_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_13_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_13_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_13_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_13_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_13_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_13_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_13_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_13_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_13_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_13_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_13_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_13_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_13_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_13_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_13_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_13_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_13_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_13_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_13_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_13_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_13_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_13_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_13_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_13_bits_executed; // @[lsu.scala:208:16] reg ldq_13_bits_succeeded; // @[lsu.scala:208:16] reg ldq_13_bits_order_fail; // @[lsu.scala:208:16] reg ldq_13_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_13_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_13_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_13_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_13_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_14_valid; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_14_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_14_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_14_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_14_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_14_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_14_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_14_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_14_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_14_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_14_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_14_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_14_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_14_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_14_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_14_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_14_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_14_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_14_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_14_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_14_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_14_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_14_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_14_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_14_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_14_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_14_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_14_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_14_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_14_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_14_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_14_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_14_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_14_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_14_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_14_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_14_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_14_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_14_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_14_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_14_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_14_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_14_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_14_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_14_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_14_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_14_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_14_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_14_bits_executed; // @[lsu.scala:208:16] reg ldq_14_bits_succeeded; // @[lsu.scala:208:16] reg ldq_14_bits_order_fail; // @[lsu.scala:208:16] reg ldq_14_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_14_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_14_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_14_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_14_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_15_valid; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_15_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_15_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_15_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_15_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_15_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_15_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_15_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_15_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_15_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_15_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_15_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_15_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_15_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_15_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_15_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_15_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_15_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_15_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_15_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_15_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_15_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_15_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_15_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_15_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_15_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_15_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_15_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_15_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_15_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_15_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_15_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_15_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_15_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_15_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_15_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_15_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_15_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_15_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_15_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_15_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_15_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_15_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_15_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_15_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_15_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_15_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_15_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_15_bits_executed; // @[lsu.scala:208:16] reg ldq_15_bits_succeeded; // @[lsu.scala:208:16] reg ldq_15_bits_order_fail; // @[lsu.scala:208:16] reg ldq_15_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_15_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_15_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_15_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_15_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_16_valid; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_16_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_16_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_16_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_16_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_16_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_16_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_16_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_16_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_16_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_16_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_16_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_16_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_16_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_16_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_16_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_16_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_16_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_16_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_16_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_16_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_16_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_16_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_16_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_16_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_16_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_16_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_16_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_16_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_16_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_16_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_16_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_16_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_16_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_16_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_16_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_16_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_16_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_16_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_16_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_16_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_16_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_16_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_16_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_16_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_16_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_16_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_16_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_16_bits_executed; // @[lsu.scala:208:16] reg ldq_16_bits_succeeded; // @[lsu.scala:208:16] reg ldq_16_bits_order_fail; // @[lsu.scala:208:16] reg ldq_16_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_16_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_16_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_16_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_16_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_17_valid; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_17_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_17_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_17_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_17_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_17_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_17_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_17_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_17_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_17_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_17_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_17_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_17_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_17_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_17_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_17_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_17_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_17_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_17_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_17_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_17_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_17_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_17_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_17_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_17_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_17_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_17_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_17_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_17_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_17_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_17_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_17_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_17_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_17_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_17_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_17_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_17_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_17_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_17_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_17_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_17_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_17_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_17_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_17_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_17_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_17_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_17_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_17_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_17_bits_executed; // @[lsu.scala:208:16] reg ldq_17_bits_succeeded; // @[lsu.scala:208:16] reg ldq_17_bits_order_fail; // @[lsu.scala:208:16] reg ldq_17_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_17_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_17_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_17_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_17_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_18_valid; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_18_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_18_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_18_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_18_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_18_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_18_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_18_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_18_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_18_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_18_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_18_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_18_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_18_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_18_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_18_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_18_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_18_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_18_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_18_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_18_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_18_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_18_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_18_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_18_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_18_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_18_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_18_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_18_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_18_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_18_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_18_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_18_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_18_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_18_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_18_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_18_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_18_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_18_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_18_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_18_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_18_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_18_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_18_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_18_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_18_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_18_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_18_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_18_bits_executed; // @[lsu.scala:208:16] reg ldq_18_bits_succeeded; // @[lsu.scala:208:16] reg ldq_18_bits_order_fail; // @[lsu.scala:208:16] reg ldq_18_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_18_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_18_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_18_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_18_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_19_valid; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_19_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_19_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_19_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_19_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_19_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_19_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_19_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_19_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_19_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_19_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_19_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_19_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_19_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_19_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_19_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_19_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_19_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_19_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_19_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_19_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_19_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_19_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_19_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_19_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_19_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_19_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_19_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_19_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_19_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_19_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_19_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_19_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_19_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_19_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_19_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_19_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_19_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_19_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_19_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_19_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_19_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_19_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_19_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_19_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_19_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_19_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_19_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_19_bits_executed; // @[lsu.scala:208:16] reg ldq_19_bits_succeeded; // @[lsu.scala:208:16] reg ldq_19_bits_order_fail; // @[lsu.scala:208:16] reg ldq_19_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_19_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_19_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_19_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_19_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_20_valid; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_20_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_20_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_20_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_20_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_20_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_20_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_20_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_20_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_20_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_20_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_20_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_20_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_20_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_20_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_20_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_20_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_20_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_20_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_20_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_20_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_20_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_20_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_20_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_20_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_20_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_20_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_20_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_20_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_20_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_20_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_20_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_20_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_20_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_20_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_20_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_20_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_20_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_20_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_20_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_20_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_20_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_20_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_20_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_20_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_20_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_20_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_20_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_20_bits_executed; // @[lsu.scala:208:16] reg ldq_20_bits_succeeded; // @[lsu.scala:208:16] reg ldq_20_bits_order_fail; // @[lsu.scala:208:16] reg ldq_20_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_20_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_20_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_20_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_20_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_21_valid; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_21_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_21_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_21_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_21_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_21_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_21_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_21_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_21_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_21_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_21_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_21_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_21_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_21_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_21_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_21_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_21_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_21_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_21_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_21_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_21_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_21_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_21_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_21_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_21_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_21_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_21_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_21_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_21_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_21_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_21_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_21_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_21_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_21_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_21_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_21_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_21_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_21_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_21_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_21_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_21_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_21_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_21_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_21_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_21_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_21_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_21_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_21_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_21_bits_executed; // @[lsu.scala:208:16] reg ldq_21_bits_succeeded; // @[lsu.scala:208:16] reg ldq_21_bits_order_fail; // @[lsu.scala:208:16] reg ldq_21_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_21_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_21_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_21_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_21_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_22_valid; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_22_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_22_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_22_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_22_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_22_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_22_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_22_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_22_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_22_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_22_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_22_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_22_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_22_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_22_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_22_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_22_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_22_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_22_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_22_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_22_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_22_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_22_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_22_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_22_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_22_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_22_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_22_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_22_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_22_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_22_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_22_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_22_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_22_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_22_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_22_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_22_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_22_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_22_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_22_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_22_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_22_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_22_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_22_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_22_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_22_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_22_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_22_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_22_bits_executed; // @[lsu.scala:208:16] reg ldq_22_bits_succeeded; // @[lsu.scala:208:16] reg ldq_22_bits_order_fail; // @[lsu.scala:208:16] reg ldq_22_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_22_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_22_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_22_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_22_bits_debug_wb_data; // @[lsu.scala:208:16] reg ldq_23_valid; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_uopc; // @[lsu.scala:208:16] reg [31:0] ldq_23_bits_uop_inst; // @[lsu.scala:208:16] reg [31:0] ldq_23_bits_uop_debug_inst; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_rvc; // @[lsu.scala:208:16] reg [39:0] ldq_23_bits_uop_debug_pc; // @[lsu.scala:208:16] reg [2:0] ldq_23_bits_uop_iq_type; // @[lsu.scala:208:16] reg [9:0] ldq_23_bits_uop_fu_code; // @[lsu.scala:208:16] reg [3:0] ldq_23_bits_uop_ctrl_br_type; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_ctrl_op1_sel; // @[lsu.scala:208:16] reg [2:0] ldq_23_bits_uop_ctrl_op2_sel; // @[lsu.scala:208:16] reg [2:0] ldq_23_bits_uop_ctrl_imm_sel; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_uop_ctrl_op_fcn; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ctrl_fcn_dw; // @[lsu.scala:208:16] reg [2:0] ldq_23_bits_uop_ctrl_csr_cmd; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ctrl_is_load; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ctrl_is_sta; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ctrl_is_std; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_iw_state; // @[lsu.scala:208:16] reg ldq_23_bits_uop_iw_p1_poisoned; // @[lsu.scala:208:16] reg ldq_23_bits_uop_iw_p2_poisoned; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_br; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_jalr; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_jal; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_sfb; // @[lsu.scala:208:16] reg [15:0] ldq_23_bits_uop_br_mask; // @[lsu.scala:208:16] reg [3:0] ldq_23_bits_uop_br_tag; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_uop_ftq_idx; // @[lsu.scala:208:16] reg ldq_23_bits_uop_edge_inst; // @[lsu.scala:208:16] reg [5:0] ldq_23_bits_uop_pc_lob; // @[lsu.scala:208:16] reg ldq_23_bits_uop_taken; // @[lsu.scala:208:16] reg [19:0] ldq_23_bits_uop_imm_packed; // @[lsu.scala:208:16] reg [11:0] ldq_23_bits_uop_csr_addr; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_rob_idx; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_uop_ldq_idx; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_uop_stq_idx; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_rxq_idx; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_pdst; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_prs1; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_prs2; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_prs3; // @[lsu.scala:208:16] reg ldq_23_bits_uop_prs1_busy; // @[lsu.scala:208:16] reg ldq_23_bits_uop_prs2_busy; // @[lsu.scala:208:16] reg ldq_23_bits_uop_prs3_busy; // @[lsu.scala:208:16] reg [6:0] ldq_23_bits_uop_stale_pdst; // @[lsu.scala:208:16] reg ldq_23_bits_uop_exception; // @[lsu.scala:208:16] reg [63:0] ldq_23_bits_uop_exc_cause; // @[lsu.scala:208:16] reg ldq_23_bits_uop_bypassable; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_uop_mem_cmd; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_mem_size; // @[lsu.scala:208:16] reg ldq_23_bits_uop_mem_signed; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_fence; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_fencei; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_amo; // @[lsu.scala:208:16] reg ldq_23_bits_uop_uses_ldq; // @[lsu.scala:208:16] reg ldq_23_bits_uop_uses_stq; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_sys_pc2epc; // @[lsu.scala:208:16] reg ldq_23_bits_uop_is_unique; // @[lsu.scala:208:16] reg ldq_23_bits_uop_flush_on_commit; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ldst_is_rs1; // @[lsu.scala:208:16] reg [5:0] ldq_23_bits_uop_ldst; // @[lsu.scala:208:16] reg [5:0] ldq_23_bits_uop_lrs1; // @[lsu.scala:208:16] reg [5:0] ldq_23_bits_uop_lrs2; // @[lsu.scala:208:16] reg [5:0] ldq_23_bits_uop_lrs3; // @[lsu.scala:208:16] reg ldq_23_bits_uop_ldst_val; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_dst_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_lrs1_rtype; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_lrs2_rtype; // @[lsu.scala:208:16] reg ldq_23_bits_uop_frs3_en; // @[lsu.scala:208:16] reg ldq_23_bits_uop_fp_val; // @[lsu.scala:208:16] reg ldq_23_bits_uop_fp_single; // @[lsu.scala:208:16] reg ldq_23_bits_uop_xcpt_pf_if; // @[lsu.scala:208:16] reg ldq_23_bits_uop_xcpt_ae_if; // @[lsu.scala:208:16] reg ldq_23_bits_uop_xcpt_ma_if; // @[lsu.scala:208:16] reg ldq_23_bits_uop_bp_debug_if; // @[lsu.scala:208:16] reg ldq_23_bits_uop_bp_xcpt_if; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_debug_fsrc; // @[lsu.scala:208:16] reg [1:0] ldq_23_bits_uop_debug_tsrc; // @[lsu.scala:208:16] reg ldq_23_bits_addr_valid; // @[lsu.scala:208:16] reg [39:0] ldq_23_bits_addr_bits; // @[lsu.scala:208:16] reg ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16] reg ldq_23_bits_addr_is_uncacheable; // @[lsu.scala:208:16] reg ldq_23_bits_executed; // @[lsu.scala:208:16] reg ldq_23_bits_succeeded; // @[lsu.scala:208:16] reg ldq_23_bits_order_fail; // @[lsu.scala:208:16] reg ldq_23_bits_observed; // @[lsu.scala:208:16] reg [23:0] ldq_23_bits_st_dep_mask; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_youngest_stq_idx; // @[lsu.scala:208:16] reg ldq_23_bits_forward_std_val; // @[lsu.scala:208:16] reg [4:0] ldq_23_bits_forward_stq_idx; // @[lsu.scala:208:16] reg [63:0] ldq_23_bits_debug_wb_data; // @[lsu.scala:208:16] reg stq_0_valid; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_0_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_0_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_0_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_0_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_0_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_0_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_0_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_0_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_0_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_0_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_0_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_0_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_0_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_0_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_0_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_0_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_0_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_0_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_0_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_0_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_0_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_0_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_0_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_0_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_0_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_0_bits_addr_bits; // @[lsu.scala:209:16] reg stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_0_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_data_bits; // @[lsu.scala:209:16] reg stq_0_bits_committed; // @[lsu.scala:209:16] reg stq_0_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_0_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_1_valid; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_1_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_1_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_1_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_1_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_1_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_1_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_1_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_1_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_1_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_1_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_1_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_1_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_1_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_1_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_1_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_1_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_1_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_1_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_1_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_1_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_1_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_1_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_1_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_1_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_1_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_1_bits_addr_bits; // @[lsu.scala:209:16] reg stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_1_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_data_bits; // @[lsu.scala:209:16] reg stq_1_bits_committed; // @[lsu.scala:209:16] reg stq_1_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_1_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_2_valid; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_2_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_2_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_2_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_2_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_2_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_2_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_2_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_2_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_2_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_2_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_2_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_2_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_2_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_2_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_2_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_2_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_2_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_2_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_2_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_2_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_2_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_2_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_2_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_2_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_2_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_2_bits_addr_bits; // @[lsu.scala:209:16] reg stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_2_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_data_bits; // @[lsu.scala:209:16] reg stq_2_bits_committed; // @[lsu.scala:209:16] reg stq_2_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_2_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_3_valid; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_3_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_3_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_3_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_3_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_3_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_3_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_3_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_3_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_3_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_3_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_3_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_3_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_3_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_3_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_3_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_3_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_3_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_3_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_3_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_3_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_3_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_3_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_3_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_3_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_3_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_3_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_3_bits_addr_bits; // @[lsu.scala:209:16] reg stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_3_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_data_bits; // @[lsu.scala:209:16] reg stq_3_bits_committed; // @[lsu.scala:209:16] reg stq_3_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_3_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_4_valid; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_4_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_4_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_4_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_4_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_4_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_4_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_4_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_4_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_4_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_4_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_4_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_4_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_4_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_4_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_4_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_4_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_4_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_4_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_4_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_4_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_4_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_4_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_4_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_4_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_4_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_4_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_4_bits_addr_bits; // @[lsu.scala:209:16] reg stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_4_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_data_bits; // @[lsu.scala:209:16] reg stq_4_bits_committed; // @[lsu.scala:209:16] reg stq_4_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_4_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_5_valid; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_5_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_5_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_5_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_5_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_5_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_5_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_5_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_5_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_5_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_5_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_5_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_5_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_5_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_5_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_5_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_5_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_5_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_5_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_5_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_5_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_5_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_5_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_5_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_5_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_5_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_5_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_5_bits_addr_bits; // @[lsu.scala:209:16] reg stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_5_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_data_bits; // @[lsu.scala:209:16] reg stq_5_bits_committed; // @[lsu.scala:209:16] reg stq_5_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_5_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_6_valid; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_6_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_6_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_6_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_6_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_6_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_6_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_6_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_6_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_6_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_6_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_6_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_6_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_6_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_6_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_6_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_6_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_6_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_6_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_6_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_6_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_6_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_6_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_6_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_6_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_6_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_6_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_6_bits_addr_bits; // @[lsu.scala:209:16] reg stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_6_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_data_bits; // @[lsu.scala:209:16] reg stq_6_bits_committed; // @[lsu.scala:209:16] reg stq_6_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_6_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_7_valid; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_7_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_7_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_7_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_7_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_7_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_7_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_7_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_7_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_7_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_7_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_7_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_7_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_7_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_7_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_7_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_7_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_7_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_7_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_7_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_7_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_7_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_7_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_7_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_7_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_7_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_7_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_7_bits_addr_bits; // @[lsu.scala:209:16] reg stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_7_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_data_bits; // @[lsu.scala:209:16] reg stq_7_bits_committed; // @[lsu.scala:209:16] reg stq_7_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_7_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_8_valid; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_8_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_8_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_8_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_8_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_8_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_8_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_8_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_8_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_8_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_8_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_8_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_8_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_8_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_8_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_8_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_8_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_8_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_8_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_8_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_8_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_8_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_8_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_8_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_8_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_8_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_8_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_8_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_8_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_8_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_8_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_8_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_8_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_8_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_8_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_8_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_8_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_8_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_8_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_8_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_8_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_8_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_8_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_8_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_8_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_8_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_8_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_8_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_8_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_8_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_8_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_8_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_8_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_8_bits_addr_bits; // @[lsu.scala:209:16] reg stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_8_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_8_bits_data_bits; // @[lsu.scala:209:16] reg stq_8_bits_committed; // @[lsu.scala:209:16] reg stq_8_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_8_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_9_valid; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_9_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_9_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_9_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_9_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_9_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_9_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_9_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_9_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_9_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_9_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_9_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_9_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_9_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_9_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_9_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_9_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_9_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_9_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_9_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_9_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_9_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_9_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_9_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_9_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_9_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_9_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_9_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_9_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_9_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_9_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_9_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_9_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_9_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_9_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_9_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_9_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_9_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_9_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_9_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_9_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_9_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_9_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_9_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_9_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_9_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_9_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_9_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_9_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_9_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_9_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_9_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_9_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_9_bits_addr_bits; // @[lsu.scala:209:16] reg stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_9_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_9_bits_data_bits; // @[lsu.scala:209:16] reg stq_9_bits_committed; // @[lsu.scala:209:16] reg stq_9_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_9_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_10_valid; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_10_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_10_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_10_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_10_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_10_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_10_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_10_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_10_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_10_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_10_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_10_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_10_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_10_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_10_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_10_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_10_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_10_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_10_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_10_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_10_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_10_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_10_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_10_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_10_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_10_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_10_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_10_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_10_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_10_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_10_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_10_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_10_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_10_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_10_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_10_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_10_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_10_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_10_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_10_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_10_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_10_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_10_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_10_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_10_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_10_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_10_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_10_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_10_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_10_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_10_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_10_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_10_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_10_bits_addr_bits; // @[lsu.scala:209:16] reg stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_10_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_10_bits_data_bits; // @[lsu.scala:209:16] reg stq_10_bits_committed; // @[lsu.scala:209:16] reg stq_10_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_10_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_11_valid; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_11_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_11_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_11_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_11_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_11_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_11_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_11_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_11_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_11_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_11_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_11_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_11_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_11_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_11_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_11_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_11_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_11_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_11_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_11_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_11_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_11_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_11_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_11_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_11_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_11_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_11_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_11_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_11_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_11_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_11_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_11_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_11_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_11_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_11_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_11_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_11_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_11_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_11_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_11_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_11_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_11_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_11_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_11_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_11_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_11_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_11_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_11_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_11_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_11_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_11_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_11_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_11_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_11_bits_addr_bits; // @[lsu.scala:209:16] reg stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_11_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_11_bits_data_bits; // @[lsu.scala:209:16] reg stq_11_bits_committed; // @[lsu.scala:209:16] reg stq_11_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_11_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_12_valid; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_12_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_12_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_12_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_12_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_12_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_12_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_12_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_12_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_12_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_12_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_12_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_12_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_12_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_12_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_12_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_12_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_12_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_12_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_12_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_12_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_12_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_12_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_12_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_12_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_12_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_12_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_12_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_12_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_12_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_12_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_12_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_12_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_12_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_12_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_12_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_12_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_12_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_12_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_12_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_12_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_12_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_12_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_12_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_12_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_12_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_12_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_12_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_12_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_12_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_12_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_12_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_12_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_12_bits_addr_bits; // @[lsu.scala:209:16] reg stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_12_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_12_bits_data_bits; // @[lsu.scala:209:16] reg stq_12_bits_committed; // @[lsu.scala:209:16] reg stq_12_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_12_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_13_valid; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_13_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_13_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_13_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_13_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_13_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_13_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_13_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_13_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_13_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_13_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_13_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_13_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_13_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_13_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_13_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_13_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_13_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_13_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_13_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_13_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_13_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_13_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_13_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_13_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_13_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_13_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_13_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_13_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_13_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_13_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_13_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_13_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_13_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_13_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_13_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_13_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_13_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_13_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_13_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_13_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_13_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_13_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_13_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_13_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_13_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_13_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_13_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_13_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_13_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_13_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_13_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_13_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_13_bits_addr_bits; // @[lsu.scala:209:16] reg stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_13_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_13_bits_data_bits; // @[lsu.scala:209:16] reg stq_13_bits_committed; // @[lsu.scala:209:16] reg stq_13_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_13_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_14_valid; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_14_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_14_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_14_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_14_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_14_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_14_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_14_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_14_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_14_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_14_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_14_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_14_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_14_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_14_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_14_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_14_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_14_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_14_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_14_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_14_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_14_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_14_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_14_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_14_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_14_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_14_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_14_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_14_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_14_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_14_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_14_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_14_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_14_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_14_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_14_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_14_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_14_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_14_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_14_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_14_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_14_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_14_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_14_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_14_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_14_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_14_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_14_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_14_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_14_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_14_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_14_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_14_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_14_bits_addr_bits; // @[lsu.scala:209:16] reg stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_14_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_14_bits_data_bits; // @[lsu.scala:209:16] reg stq_14_bits_committed; // @[lsu.scala:209:16] reg stq_14_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_14_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_15_valid; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_15_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_15_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_15_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_15_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_15_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_15_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_15_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_15_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_15_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_15_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_15_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_15_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_15_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_15_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_15_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_15_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_15_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_15_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_15_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_15_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_15_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_15_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_15_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_15_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_15_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_15_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_15_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_15_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_15_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_15_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_15_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_15_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_15_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_15_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_15_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_15_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_15_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_15_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_15_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_15_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_15_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_15_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_15_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_15_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_15_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_15_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_15_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_15_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_15_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_15_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_15_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_15_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_15_bits_addr_bits; // @[lsu.scala:209:16] reg stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_15_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_15_bits_data_bits; // @[lsu.scala:209:16] reg stq_15_bits_committed; // @[lsu.scala:209:16] reg stq_15_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_15_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_16_valid; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_16_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_16_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_16_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_16_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_16_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_16_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_16_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_16_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_16_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_16_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_16_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_16_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_16_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_16_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_16_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_16_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_16_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_16_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_16_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_16_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_16_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_16_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_16_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_16_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_16_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_16_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_16_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_16_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_16_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_16_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_16_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_16_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_16_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_16_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_16_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_16_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_16_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_16_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_16_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_16_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_16_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_16_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_16_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_16_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_16_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_16_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_16_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_16_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_16_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_16_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_16_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_16_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_16_bits_addr_bits; // @[lsu.scala:209:16] reg stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_16_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_16_bits_data_bits; // @[lsu.scala:209:16] reg stq_16_bits_committed; // @[lsu.scala:209:16] reg stq_16_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_16_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_17_valid; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_17_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_17_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_17_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_17_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_17_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_17_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_17_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_17_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_17_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_17_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_17_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_17_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_17_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_17_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_17_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_17_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_17_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_17_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_17_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_17_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_17_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_17_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_17_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_17_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_17_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_17_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_17_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_17_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_17_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_17_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_17_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_17_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_17_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_17_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_17_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_17_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_17_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_17_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_17_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_17_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_17_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_17_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_17_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_17_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_17_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_17_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_17_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_17_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_17_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_17_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_17_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_17_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_17_bits_addr_bits; // @[lsu.scala:209:16] reg stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_17_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_17_bits_data_bits; // @[lsu.scala:209:16] reg stq_17_bits_committed; // @[lsu.scala:209:16] reg stq_17_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_17_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_18_valid; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_18_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_18_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_18_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_18_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_18_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_18_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_18_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_18_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_18_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_18_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_18_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_18_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_18_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_18_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_18_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_18_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_18_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_18_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_18_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_18_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_18_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_18_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_18_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_18_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_18_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_18_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_18_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_18_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_18_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_18_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_18_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_18_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_18_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_18_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_18_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_18_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_18_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_18_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_18_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_18_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_18_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_18_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_18_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_18_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_18_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_18_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_18_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_18_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_18_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_18_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_18_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_18_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_18_bits_addr_bits; // @[lsu.scala:209:16] reg stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_18_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_18_bits_data_bits; // @[lsu.scala:209:16] reg stq_18_bits_committed; // @[lsu.scala:209:16] reg stq_18_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_18_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_19_valid; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_19_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_19_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_19_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_19_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_19_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_19_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_19_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_19_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_19_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_19_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_19_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_19_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_19_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_19_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_19_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_19_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_19_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_19_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_19_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_19_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_19_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_19_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_19_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_19_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_19_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_19_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_19_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_19_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_19_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_19_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_19_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_19_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_19_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_19_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_19_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_19_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_19_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_19_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_19_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_19_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_19_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_19_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_19_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_19_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_19_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_19_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_19_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_19_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_19_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_19_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_19_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_19_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_19_bits_addr_bits; // @[lsu.scala:209:16] reg stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_19_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_19_bits_data_bits; // @[lsu.scala:209:16] reg stq_19_bits_committed; // @[lsu.scala:209:16] reg stq_19_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_19_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_20_valid; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_20_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_20_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_20_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_20_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_20_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_20_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_20_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_20_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_20_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_20_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_20_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_20_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_20_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_20_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_20_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_20_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_20_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_20_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_20_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_20_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_20_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_20_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_20_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_20_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_20_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_20_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_20_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_20_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_20_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_20_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_20_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_20_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_20_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_20_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_20_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_20_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_20_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_20_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_20_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_20_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_20_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_20_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_20_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_20_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_20_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_20_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_20_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_20_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_20_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_20_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_20_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_20_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_20_bits_addr_bits; // @[lsu.scala:209:16] reg stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_20_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_20_bits_data_bits; // @[lsu.scala:209:16] reg stq_20_bits_committed; // @[lsu.scala:209:16] reg stq_20_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_20_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_21_valid; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_21_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_21_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_21_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_21_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_21_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_21_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_21_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_21_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_21_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_21_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_21_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_21_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_21_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_21_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_21_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_21_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_21_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_21_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_21_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_21_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_21_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_21_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_21_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_21_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_21_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_21_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_21_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_21_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_21_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_21_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_21_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_21_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_21_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_21_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_21_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_21_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_21_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_21_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_21_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_21_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_21_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_21_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_21_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_21_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_21_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_21_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_21_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_21_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_21_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_21_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_21_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_21_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_21_bits_addr_bits; // @[lsu.scala:209:16] reg stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_21_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_21_bits_data_bits; // @[lsu.scala:209:16] reg stq_21_bits_committed; // @[lsu.scala:209:16] reg stq_21_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_21_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_22_valid; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_22_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_22_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_22_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_22_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_22_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_22_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_22_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_22_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_22_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_22_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_22_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_22_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_22_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_22_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_22_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_22_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_22_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_22_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_22_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_22_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_22_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_22_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_22_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_22_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_22_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_22_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_22_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_22_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_22_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_22_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_22_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_22_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_22_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_22_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_22_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_22_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_22_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_22_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_22_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_22_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_22_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_22_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_22_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_22_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_22_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_22_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_22_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_22_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_22_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_22_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_22_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_22_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_22_bits_addr_bits; // @[lsu.scala:209:16] reg stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_22_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_22_bits_data_bits; // @[lsu.scala:209:16] reg stq_22_bits_committed; // @[lsu.scala:209:16] reg stq_22_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_22_bits_debug_wb_data; // @[lsu.scala:209:16] reg stq_23_valid; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_uopc; // @[lsu.scala:209:16] reg [31:0] stq_23_bits_uop_inst; // @[lsu.scala:209:16] reg [31:0] stq_23_bits_uop_debug_inst; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_rvc; // @[lsu.scala:209:16] reg [39:0] stq_23_bits_uop_debug_pc; // @[lsu.scala:209:16] reg [2:0] stq_23_bits_uop_iq_type; // @[lsu.scala:209:16] reg [9:0] stq_23_bits_uop_fu_code; // @[lsu.scala:209:16] reg [3:0] stq_23_bits_uop_ctrl_br_type; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_ctrl_op1_sel; // @[lsu.scala:209:16] reg [2:0] stq_23_bits_uop_ctrl_op2_sel; // @[lsu.scala:209:16] reg [2:0] stq_23_bits_uop_ctrl_imm_sel; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_ctrl_op_fcn; // @[lsu.scala:209:16] reg stq_23_bits_uop_ctrl_fcn_dw; // @[lsu.scala:209:16] reg [2:0] stq_23_bits_uop_ctrl_csr_cmd; // @[lsu.scala:209:16] reg stq_23_bits_uop_ctrl_is_load; // @[lsu.scala:209:16] reg stq_23_bits_uop_ctrl_is_sta; // @[lsu.scala:209:16] reg stq_23_bits_uop_ctrl_is_std; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_iw_state; // @[lsu.scala:209:16] reg stq_23_bits_uop_iw_p1_poisoned; // @[lsu.scala:209:16] reg stq_23_bits_uop_iw_p2_poisoned; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_br; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_jalr; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_jal; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_sfb; // @[lsu.scala:209:16] reg [15:0] stq_23_bits_uop_br_mask; // @[lsu.scala:209:16] reg [3:0] stq_23_bits_uop_br_tag; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_ftq_idx; // @[lsu.scala:209:16] reg stq_23_bits_uop_edge_inst; // @[lsu.scala:209:16] reg [5:0] stq_23_bits_uop_pc_lob; // @[lsu.scala:209:16] reg stq_23_bits_uop_taken; // @[lsu.scala:209:16] reg [19:0] stq_23_bits_uop_imm_packed; // @[lsu.scala:209:16] reg [11:0] stq_23_bits_uop_csr_addr; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_rob_idx; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_ldq_idx; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_stq_idx; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_rxq_idx; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_pdst; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_prs1; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_prs2; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_prs3; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_ppred; // @[lsu.scala:209:16] reg stq_23_bits_uop_prs1_busy; // @[lsu.scala:209:16] reg stq_23_bits_uop_prs2_busy; // @[lsu.scala:209:16] reg stq_23_bits_uop_prs3_busy; // @[lsu.scala:209:16] reg stq_23_bits_uop_ppred_busy; // @[lsu.scala:209:16] reg [6:0] stq_23_bits_uop_stale_pdst; // @[lsu.scala:209:16] reg stq_23_bits_uop_exception; // @[lsu.scala:209:16] reg [63:0] stq_23_bits_uop_exc_cause; // @[lsu.scala:209:16] reg stq_23_bits_uop_bypassable; // @[lsu.scala:209:16] reg [4:0] stq_23_bits_uop_mem_cmd; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_mem_size; // @[lsu.scala:209:16] reg stq_23_bits_uop_mem_signed; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_fence; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_fencei; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_amo; // @[lsu.scala:209:16] reg stq_23_bits_uop_uses_ldq; // @[lsu.scala:209:16] reg stq_23_bits_uop_uses_stq; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_sys_pc2epc; // @[lsu.scala:209:16] reg stq_23_bits_uop_is_unique; // @[lsu.scala:209:16] reg stq_23_bits_uop_flush_on_commit; // @[lsu.scala:209:16] reg stq_23_bits_uop_ldst_is_rs1; // @[lsu.scala:209:16] reg [5:0] stq_23_bits_uop_ldst; // @[lsu.scala:209:16] reg [5:0] stq_23_bits_uop_lrs1; // @[lsu.scala:209:16] reg [5:0] stq_23_bits_uop_lrs2; // @[lsu.scala:209:16] reg [5:0] stq_23_bits_uop_lrs3; // @[lsu.scala:209:16] reg stq_23_bits_uop_ldst_val; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_dst_rtype; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_lrs1_rtype; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_lrs2_rtype; // @[lsu.scala:209:16] reg stq_23_bits_uop_frs3_en; // @[lsu.scala:209:16] reg stq_23_bits_uop_fp_val; // @[lsu.scala:209:16] reg stq_23_bits_uop_fp_single; // @[lsu.scala:209:16] reg stq_23_bits_uop_xcpt_pf_if; // @[lsu.scala:209:16] reg stq_23_bits_uop_xcpt_ae_if; // @[lsu.scala:209:16] reg stq_23_bits_uop_xcpt_ma_if; // @[lsu.scala:209:16] reg stq_23_bits_uop_bp_debug_if; // @[lsu.scala:209:16] reg stq_23_bits_uop_bp_xcpt_if; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_debug_fsrc; // @[lsu.scala:209:16] reg [1:0] stq_23_bits_uop_debug_tsrc; // @[lsu.scala:209:16] reg stq_23_bits_addr_valid; // @[lsu.scala:209:16] reg [39:0] stq_23_bits_addr_bits; // @[lsu.scala:209:16] reg stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16] reg stq_23_bits_data_valid; // @[lsu.scala:209:16] reg [63:0] stq_23_bits_data_bits; // @[lsu.scala:209:16] reg stq_23_bits_committed; // @[lsu.scala:209:16] reg stq_23_bits_succeeded; // @[lsu.scala:209:16] reg [63:0] stq_23_bits_debug_wb_data; // @[lsu.scala:209:16] reg [4:0] ldq_head; // @[lsu.scala:213:29] reg [4:0] ldq_tail; // @[lsu.scala:214:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:201:7, :214:29] reg [4:0] stq_head; // @[lsu.scala:215:29] reg [4:0] stq_tail; // @[lsu.scala:216:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:201:7, :216:29] reg [4:0] stq_commit_head; // @[lsu.scala:217:29] reg [4:0] stq_execute_head; // @[lsu.scala:218:29] wire [31:0] _GEN = {{stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_0_valid}, {stq_23_valid}, {stq_22_valid}, {stq_21_valid}, {stq_20_valid}, {stq_19_valid}, {stq_18_valid}, {stq_17_valid}, {stq_16_valid}, {stq_15_valid}, {stq_14_valid}, {stq_13_valid}, {stq_12_valid}, {stq_11_valid}, {stq_10_valid}, {stq_9_valid}, {stq_8_valid}, {stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}}; // @[lsu.scala:209:16, :222:42] wire _GEN_0 = _GEN[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [31:0][6:0] _GEN_1 = {{stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_0_bits_uop_uopc}, {stq_23_bits_uop_uopc}, {stq_22_bits_uop_uopc}, {stq_21_bits_uop_uopc}, {stq_20_bits_uop_uopc}, {stq_19_bits_uop_uopc}, {stq_18_bits_uop_uopc}, {stq_17_bits_uop_uopc}, {stq_16_bits_uop_uopc}, {stq_15_bits_uop_uopc}, {stq_14_bits_uop_uopc}, {stq_13_bits_uop_uopc}, {stq_12_bits_uop_uopc}, {stq_11_bits_uop_uopc}, {stq_10_bits_uop_uopc}, {stq_9_bits_uop_uopc}, {stq_8_bits_uop_uopc}, {stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}}; // @[lsu.scala:209:16, :222:42] wire [31:0][31:0] _GEN_2 = {{stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_0_bits_uop_inst}, {stq_23_bits_uop_inst}, {stq_22_bits_uop_inst}, {stq_21_bits_uop_inst}, {stq_20_bits_uop_inst}, {stq_19_bits_uop_inst}, {stq_18_bits_uop_inst}, {stq_17_bits_uop_inst}, {stq_16_bits_uop_inst}, {stq_15_bits_uop_inst}, {stq_14_bits_uop_inst}, {stq_13_bits_uop_inst}, {stq_12_bits_uop_inst}, {stq_11_bits_uop_inst}, {stq_10_bits_uop_inst}, {stq_9_bits_uop_inst}, {stq_8_bits_uop_inst}, {stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}}; // @[lsu.scala:209:16, :222:42] wire [31:0][31:0] _GEN_3 = {{stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}, {stq_23_bits_uop_debug_inst}, {stq_22_bits_uop_debug_inst}, {stq_21_bits_uop_debug_inst}, {stq_20_bits_uop_debug_inst}, {stq_19_bits_uop_debug_inst}, {stq_18_bits_uop_debug_inst}, {stq_17_bits_uop_debug_inst}, {stq_16_bits_uop_debug_inst}, {stq_15_bits_uop_debug_inst}, {stq_14_bits_uop_debug_inst}, {stq_13_bits_uop_debug_inst}, {stq_12_bits_uop_debug_inst}, {stq_11_bits_uop_debug_inst}, {stq_10_bits_uop_debug_inst}, {stq_9_bits_uop_debug_inst}, {stq_8_bits_uop_debug_inst}, {stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_4 = {{stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}, {stq_23_bits_uop_is_rvc}, {stq_22_bits_uop_is_rvc}, {stq_21_bits_uop_is_rvc}, {stq_20_bits_uop_is_rvc}, {stq_19_bits_uop_is_rvc}, {stq_18_bits_uop_is_rvc}, {stq_17_bits_uop_is_rvc}, {stq_16_bits_uop_is_rvc}, {stq_15_bits_uop_is_rvc}, {stq_14_bits_uop_is_rvc}, {stq_13_bits_uop_is_rvc}, {stq_12_bits_uop_is_rvc}, {stq_11_bits_uop_is_rvc}, {stq_10_bits_uop_is_rvc}, {stq_9_bits_uop_is_rvc}, {stq_8_bits_uop_is_rvc}, {stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}}; // @[lsu.scala:209:16, :222:42] wire [31:0][39:0] _GEN_5 = {{stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}, {stq_23_bits_uop_debug_pc}, {stq_22_bits_uop_debug_pc}, {stq_21_bits_uop_debug_pc}, {stq_20_bits_uop_debug_pc}, {stq_19_bits_uop_debug_pc}, {stq_18_bits_uop_debug_pc}, {stq_17_bits_uop_debug_pc}, {stq_16_bits_uop_debug_pc}, {stq_15_bits_uop_debug_pc}, {stq_14_bits_uop_debug_pc}, {stq_13_bits_uop_debug_pc}, {stq_12_bits_uop_debug_pc}, {stq_11_bits_uop_debug_pc}, {stq_10_bits_uop_debug_pc}, {stq_9_bits_uop_debug_pc}, {stq_8_bits_uop_debug_pc}, {stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}}; // @[lsu.scala:209:16, :222:42] wire [31:0][2:0] _GEN_6 = {{stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}, {stq_23_bits_uop_iq_type}, {stq_22_bits_uop_iq_type}, {stq_21_bits_uop_iq_type}, {stq_20_bits_uop_iq_type}, {stq_19_bits_uop_iq_type}, {stq_18_bits_uop_iq_type}, {stq_17_bits_uop_iq_type}, {stq_16_bits_uop_iq_type}, {stq_15_bits_uop_iq_type}, {stq_14_bits_uop_iq_type}, {stq_13_bits_uop_iq_type}, {stq_12_bits_uop_iq_type}, {stq_11_bits_uop_iq_type}, {stq_10_bits_uop_iq_type}, {stq_9_bits_uop_iq_type}, {stq_8_bits_uop_iq_type}, {stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}}; // @[lsu.scala:209:16, :222:42] wire [31:0][9:0] _GEN_7 = {{stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}, {stq_23_bits_uop_fu_code}, {stq_22_bits_uop_fu_code}, {stq_21_bits_uop_fu_code}, {stq_20_bits_uop_fu_code}, {stq_19_bits_uop_fu_code}, {stq_18_bits_uop_fu_code}, {stq_17_bits_uop_fu_code}, {stq_16_bits_uop_fu_code}, {stq_15_bits_uop_fu_code}, {stq_14_bits_uop_fu_code}, {stq_13_bits_uop_fu_code}, {stq_12_bits_uop_fu_code}, {stq_11_bits_uop_fu_code}, {stq_10_bits_uop_fu_code}, {stq_9_bits_uop_fu_code}, {stq_8_bits_uop_fu_code}, {stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}}; // @[lsu.scala:209:16, :222:42] wire [31:0][3:0] _GEN_8 = {{stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}, {stq_23_bits_uop_ctrl_br_type}, {stq_22_bits_uop_ctrl_br_type}, {stq_21_bits_uop_ctrl_br_type}, {stq_20_bits_uop_ctrl_br_type}, {stq_19_bits_uop_ctrl_br_type}, {stq_18_bits_uop_ctrl_br_type}, {stq_17_bits_uop_ctrl_br_type}, {stq_16_bits_uop_ctrl_br_type}, {stq_15_bits_uop_ctrl_br_type}, {stq_14_bits_uop_ctrl_br_type}, {stq_13_bits_uop_ctrl_br_type}, {stq_12_bits_uop_ctrl_br_type}, {stq_11_bits_uop_ctrl_br_type}, {stq_10_bits_uop_ctrl_br_type}, {stq_9_bits_uop_ctrl_br_type}, {stq_8_bits_uop_ctrl_br_type}, {stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_9 = {{stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}, {stq_23_bits_uop_ctrl_op1_sel}, {stq_22_bits_uop_ctrl_op1_sel}, {stq_21_bits_uop_ctrl_op1_sel}, {stq_20_bits_uop_ctrl_op1_sel}, {stq_19_bits_uop_ctrl_op1_sel}, {stq_18_bits_uop_ctrl_op1_sel}, {stq_17_bits_uop_ctrl_op1_sel}, {stq_16_bits_uop_ctrl_op1_sel}, {stq_15_bits_uop_ctrl_op1_sel}, {stq_14_bits_uop_ctrl_op1_sel}, {stq_13_bits_uop_ctrl_op1_sel}, {stq_12_bits_uop_ctrl_op1_sel}, {stq_11_bits_uop_ctrl_op1_sel}, {stq_10_bits_uop_ctrl_op1_sel}, {stq_9_bits_uop_ctrl_op1_sel}, {stq_8_bits_uop_ctrl_op1_sel}, {stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:209:16, :222:42] wire [31:0][2:0] _GEN_10 = {{stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}, {stq_23_bits_uop_ctrl_op2_sel}, {stq_22_bits_uop_ctrl_op2_sel}, {stq_21_bits_uop_ctrl_op2_sel}, {stq_20_bits_uop_ctrl_op2_sel}, {stq_19_bits_uop_ctrl_op2_sel}, {stq_18_bits_uop_ctrl_op2_sel}, {stq_17_bits_uop_ctrl_op2_sel}, {stq_16_bits_uop_ctrl_op2_sel}, {stq_15_bits_uop_ctrl_op2_sel}, {stq_14_bits_uop_ctrl_op2_sel}, {stq_13_bits_uop_ctrl_op2_sel}, {stq_12_bits_uop_ctrl_op2_sel}, {stq_11_bits_uop_ctrl_op2_sel}, {stq_10_bits_uop_ctrl_op2_sel}, {stq_9_bits_uop_ctrl_op2_sel}, {stq_8_bits_uop_ctrl_op2_sel}, {stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:209:16, :222:42] wire [31:0][2:0] _GEN_11 = {{stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}, {stq_23_bits_uop_ctrl_imm_sel}, {stq_22_bits_uop_ctrl_imm_sel}, {stq_21_bits_uop_ctrl_imm_sel}, {stq_20_bits_uop_ctrl_imm_sel}, {stq_19_bits_uop_ctrl_imm_sel}, {stq_18_bits_uop_ctrl_imm_sel}, {stq_17_bits_uop_ctrl_imm_sel}, {stq_16_bits_uop_ctrl_imm_sel}, {stq_15_bits_uop_ctrl_imm_sel}, {stq_14_bits_uop_ctrl_imm_sel}, {stq_13_bits_uop_ctrl_imm_sel}, {stq_12_bits_uop_ctrl_imm_sel}, {stq_11_bits_uop_ctrl_imm_sel}, {stq_10_bits_uop_ctrl_imm_sel}, {stq_9_bits_uop_ctrl_imm_sel}, {stq_8_bits_uop_ctrl_imm_sel}, {stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_12 = {{stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}, {stq_23_bits_uop_ctrl_op_fcn}, {stq_22_bits_uop_ctrl_op_fcn}, {stq_21_bits_uop_ctrl_op_fcn}, {stq_20_bits_uop_ctrl_op_fcn}, {stq_19_bits_uop_ctrl_op_fcn}, {stq_18_bits_uop_ctrl_op_fcn}, {stq_17_bits_uop_ctrl_op_fcn}, {stq_16_bits_uop_ctrl_op_fcn}, {stq_15_bits_uop_ctrl_op_fcn}, {stq_14_bits_uop_ctrl_op_fcn}, {stq_13_bits_uop_ctrl_op_fcn}, {stq_12_bits_uop_ctrl_op_fcn}, {stq_11_bits_uop_ctrl_op_fcn}, {stq_10_bits_uop_ctrl_op_fcn}, {stq_9_bits_uop_ctrl_op_fcn}, {stq_8_bits_uop_ctrl_op_fcn}, {stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_13 = {{stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}, {stq_23_bits_uop_ctrl_fcn_dw}, {stq_22_bits_uop_ctrl_fcn_dw}, {stq_21_bits_uop_ctrl_fcn_dw}, {stq_20_bits_uop_ctrl_fcn_dw}, {stq_19_bits_uop_ctrl_fcn_dw}, {stq_18_bits_uop_ctrl_fcn_dw}, {stq_17_bits_uop_ctrl_fcn_dw}, {stq_16_bits_uop_ctrl_fcn_dw}, {stq_15_bits_uop_ctrl_fcn_dw}, {stq_14_bits_uop_ctrl_fcn_dw}, {stq_13_bits_uop_ctrl_fcn_dw}, {stq_12_bits_uop_ctrl_fcn_dw}, {stq_11_bits_uop_ctrl_fcn_dw}, {stq_10_bits_uop_ctrl_fcn_dw}, {stq_9_bits_uop_ctrl_fcn_dw}, {stq_8_bits_uop_ctrl_fcn_dw}, {stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:209:16, :222:42] wire [31:0][2:0] _GEN_14 = {{stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}, {stq_23_bits_uop_ctrl_csr_cmd}, {stq_22_bits_uop_ctrl_csr_cmd}, {stq_21_bits_uop_ctrl_csr_cmd}, {stq_20_bits_uop_ctrl_csr_cmd}, {stq_19_bits_uop_ctrl_csr_cmd}, {stq_18_bits_uop_ctrl_csr_cmd}, {stq_17_bits_uop_ctrl_csr_cmd}, {stq_16_bits_uop_ctrl_csr_cmd}, {stq_15_bits_uop_ctrl_csr_cmd}, {stq_14_bits_uop_ctrl_csr_cmd}, {stq_13_bits_uop_ctrl_csr_cmd}, {stq_12_bits_uop_ctrl_csr_cmd}, {stq_11_bits_uop_ctrl_csr_cmd}, {stq_10_bits_uop_ctrl_csr_cmd}, {stq_9_bits_uop_ctrl_csr_cmd}, {stq_8_bits_uop_ctrl_csr_cmd}, {stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_15 = {{stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}, {stq_23_bits_uop_ctrl_is_load}, {stq_22_bits_uop_ctrl_is_load}, {stq_21_bits_uop_ctrl_is_load}, {stq_20_bits_uop_ctrl_is_load}, {stq_19_bits_uop_ctrl_is_load}, {stq_18_bits_uop_ctrl_is_load}, {stq_17_bits_uop_ctrl_is_load}, {stq_16_bits_uop_ctrl_is_load}, {stq_15_bits_uop_ctrl_is_load}, {stq_14_bits_uop_ctrl_is_load}, {stq_13_bits_uop_ctrl_is_load}, {stq_12_bits_uop_ctrl_is_load}, {stq_11_bits_uop_ctrl_is_load}, {stq_10_bits_uop_ctrl_is_load}, {stq_9_bits_uop_ctrl_is_load}, {stq_8_bits_uop_ctrl_is_load}, {stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_16 = {{stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}, {stq_23_bits_uop_ctrl_is_sta}, {stq_22_bits_uop_ctrl_is_sta}, {stq_21_bits_uop_ctrl_is_sta}, {stq_20_bits_uop_ctrl_is_sta}, {stq_19_bits_uop_ctrl_is_sta}, {stq_18_bits_uop_ctrl_is_sta}, {stq_17_bits_uop_ctrl_is_sta}, {stq_16_bits_uop_ctrl_is_sta}, {stq_15_bits_uop_ctrl_is_sta}, {stq_14_bits_uop_ctrl_is_sta}, {stq_13_bits_uop_ctrl_is_sta}, {stq_12_bits_uop_ctrl_is_sta}, {stq_11_bits_uop_ctrl_is_sta}, {stq_10_bits_uop_ctrl_is_sta}, {stq_9_bits_uop_ctrl_is_sta}, {stq_8_bits_uop_ctrl_is_sta}, {stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_17 = {{stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}, {stq_23_bits_uop_ctrl_is_std}, {stq_22_bits_uop_ctrl_is_std}, {stq_21_bits_uop_ctrl_is_std}, {stq_20_bits_uop_ctrl_is_std}, {stq_19_bits_uop_ctrl_is_std}, {stq_18_bits_uop_ctrl_is_std}, {stq_17_bits_uop_ctrl_is_std}, {stq_16_bits_uop_ctrl_is_std}, {stq_15_bits_uop_ctrl_is_std}, {stq_14_bits_uop_ctrl_is_std}, {stq_13_bits_uop_ctrl_is_std}, {stq_12_bits_uop_ctrl_is_std}, {stq_11_bits_uop_ctrl_is_std}, {stq_10_bits_uop_ctrl_is_std}, {stq_9_bits_uop_ctrl_is_std}, {stq_8_bits_uop_ctrl_is_std}, {stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_18 = {{stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}, {stq_23_bits_uop_iw_state}, {stq_22_bits_uop_iw_state}, {stq_21_bits_uop_iw_state}, {stq_20_bits_uop_iw_state}, {stq_19_bits_uop_iw_state}, {stq_18_bits_uop_iw_state}, {stq_17_bits_uop_iw_state}, {stq_16_bits_uop_iw_state}, {stq_15_bits_uop_iw_state}, {stq_14_bits_uop_iw_state}, {stq_13_bits_uop_iw_state}, {stq_12_bits_uop_iw_state}, {stq_11_bits_uop_iw_state}, {stq_10_bits_uop_iw_state}, {stq_9_bits_uop_iw_state}, {stq_8_bits_uop_iw_state}, {stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_19 = {{stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}, {stq_23_bits_uop_iw_p1_poisoned}, {stq_22_bits_uop_iw_p1_poisoned}, {stq_21_bits_uop_iw_p1_poisoned}, {stq_20_bits_uop_iw_p1_poisoned}, {stq_19_bits_uop_iw_p1_poisoned}, {stq_18_bits_uop_iw_p1_poisoned}, {stq_17_bits_uop_iw_p1_poisoned}, {stq_16_bits_uop_iw_p1_poisoned}, {stq_15_bits_uop_iw_p1_poisoned}, {stq_14_bits_uop_iw_p1_poisoned}, {stq_13_bits_uop_iw_p1_poisoned}, {stq_12_bits_uop_iw_p1_poisoned}, {stq_11_bits_uop_iw_p1_poisoned}, {stq_10_bits_uop_iw_p1_poisoned}, {stq_9_bits_uop_iw_p1_poisoned}, {stq_8_bits_uop_iw_p1_poisoned}, {stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_20 = {{stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}, {stq_23_bits_uop_iw_p2_poisoned}, {stq_22_bits_uop_iw_p2_poisoned}, {stq_21_bits_uop_iw_p2_poisoned}, {stq_20_bits_uop_iw_p2_poisoned}, {stq_19_bits_uop_iw_p2_poisoned}, {stq_18_bits_uop_iw_p2_poisoned}, {stq_17_bits_uop_iw_p2_poisoned}, {stq_16_bits_uop_iw_p2_poisoned}, {stq_15_bits_uop_iw_p2_poisoned}, {stq_14_bits_uop_iw_p2_poisoned}, {stq_13_bits_uop_iw_p2_poisoned}, {stq_12_bits_uop_iw_p2_poisoned}, {stq_11_bits_uop_iw_p2_poisoned}, {stq_10_bits_uop_iw_p2_poisoned}, {stq_9_bits_uop_iw_p2_poisoned}, {stq_8_bits_uop_iw_p2_poisoned}, {stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_21 = {{stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_0_bits_uop_is_br}, {stq_23_bits_uop_is_br}, {stq_22_bits_uop_is_br}, {stq_21_bits_uop_is_br}, {stq_20_bits_uop_is_br}, {stq_19_bits_uop_is_br}, {stq_18_bits_uop_is_br}, {stq_17_bits_uop_is_br}, {stq_16_bits_uop_is_br}, {stq_15_bits_uop_is_br}, {stq_14_bits_uop_is_br}, {stq_13_bits_uop_is_br}, {stq_12_bits_uop_is_br}, {stq_11_bits_uop_is_br}, {stq_10_bits_uop_is_br}, {stq_9_bits_uop_is_br}, {stq_8_bits_uop_is_br}, {stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_22 = {{stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}, {stq_23_bits_uop_is_jalr}, {stq_22_bits_uop_is_jalr}, {stq_21_bits_uop_is_jalr}, {stq_20_bits_uop_is_jalr}, {stq_19_bits_uop_is_jalr}, {stq_18_bits_uop_is_jalr}, {stq_17_bits_uop_is_jalr}, {stq_16_bits_uop_is_jalr}, {stq_15_bits_uop_is_jalr}, {stq_14_bits_uop_is_jalr}, {stq_13_bits_uop_is_jalr}, {stq_12_bits_uop_is_jalr}, {stq_11_bits_uop_is_jalr}, {stq_10_bits_uop_is_jalr}, {stq_9_bits_uop_is_jalr}, {stq_8_bits_uop_is_jalr}, {stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_23 = {{stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}, {stq_23_bits_uop_is_jal}, {stq_22_bits_uop_is_jal}, {stq_21_bits_uop_is_jal}, {stq_20_bits_uop_is_jal}, {stq_19_bits_uop_is_jal}, {stq_18_bits_uop_is_jal}, {stq_17_bits_uop_is_jal}, {stq_16_bits_uop_is_jal}, {stq_15_bits_uop_is_jal}, {stq_14_bits_uop_is_jal}, {stq_13_bits_uop_is_jal}, {stq_12_bits_uop_is_jal}, {stq_11_bits_uop_is_jal}, {stq_10_bits_uop_is_jal}, {stq_9_bits_uop_is_jal}, {stq_8_bits_uop_is_jal}, {stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_24 = {{stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}, {stq_23_bits_uop_is_sfb}, {stq_22_bits_uop_is_sfb}, {stq_21_bits_uop_is_sfb}, {stq_20_bits_uop_is_sfb}, {stq_19_bits_uop_is_sfb}, {stq_18_bits_uop_is_sfb}, {stq_17_bits_uop_is_sfb}, {stq_16_bits_uop_is_sfb}, {stq_15_bits_uop_is_sfb}, {stq_14_bits_uop_is_sfb}, {stq_13_bits_uop_is_sfb}, {stq_12_bits_uop_is_sfb}, {stq_11_bits_uop_is_sfb}, {stq_10_bits_uop_is_sfb}, {stq_9_bits_uop_is_sfb}, {stq_8_bits_uop_is_sfb}, {stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}}; // @[lsu.scala:209:16, :222:42] wire [31:0][15:0] _GEN_25 = {{stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}, {stq_23_bits_uop_br_mask}, {stq_22_bits_uop_br_mask}, {stq_21_bits_uop_br_mask}, {stq_20_bits_uop_br_mask}, {stq_19_bits_uop_br_mask}, {stq_18_bits_uop_br_mask}, {stq_17_bits_uop_br_mask}, {stq_16_bits_uop_br_mask}, {stq_15_bits_uop_br_mask}, {stq_14_bits_uop_br_mask}, {stq_13_bits_uop_br_mask}, {stq_12_bits_uop_br_mask}, {stq_11_bits_uop_br_mask}, {stq_10_bits_uop_br_mask}, {stq_9_bits_uop_br_mask}, {stq_8_bits_uop_br_mask}, {stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}}; // @[lsu.scala:209:16, :222:42] wire [31:0][3:0] _GEN_26 = {{stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}, {stq_23_bits_uop_br_tag}, {stq_22_bits_uop_br_tag}, {stq_21_bits_uop_br_tag}, {stq_20_bits_uop_br_tag}, {stq_19_bits_uop_br_tag}, {stq_18_bits_uop_br_tag}, {stq_17_bits_uop_br_tag}, {stq_16_bits_uop_br_tag}, {stq_15_bits_uop_br_tag}, {stq_14_bits_uop_br_tag}, {stq_13_bits_uop_br_tag}, {stq_12_bits_uop_br_tag}, {stq_11_bits_uop_br_tag}, {stq_10_bits_uop_br_tag}, {stq_9_bits_uop_br_tag}, {stq_8_bits_uop_br_tag}, {stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_27 = {{stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}, {stq_23_bits_uop_ftq_idx}, {stq_22_bits_uop_ftq_idx}, {stq_21_bits_uop_ftq_idx}, {stq_20_bits_uop_ftq_idx}, {stq_19_bits_uop_ftq_idx}, {stq_18_bits_uop_ftq_idx}, {stq_17_bits_uop_ftq_idx}, {stq_16_bits_uop_ftq_idx}, {stq_15_bits_uop_ftq_idx}, {stq_14_bits_uop_ftq_idx}, {stq_13_bits_uop_ftq_idx}, {stq_12_bits_uop_ftq_idx}, {stq_11_bits_uop_ftq_idx}, {stq_10_bits_uop_ftq_idx}, {stq_9_bits_uop_ftq_idx}, {stq_8_bits_uop_ftq_idx}, {stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_28 = {{stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}, {stq_23_bits_uop_edge_inst}, {stq_22_bits_uop_edge_inst}, {stq_21_bits_uop_edge_inst}, {stq_20_bits_uop_edge_inst}, {stq_19_bits_uop_edge_inst}, {stq_18_bits_uop_edge_inst}, {stq_17_bits_uop_edge_inst}, {stq_16_bits_uop_edge_inst}, {stq_15_bits_uop_edge_inst}, {stq_14_bits_uop_edge_inst}, {stq_13_bits_uop_edge_inst}, {stq_12_bits_uop_edge_inst}, {stq_11_bits_uop_edge_inst}, {stq_10_bits_uop_edge_inst}, {stq_9_bits_uop_edge_inst}, {stq_8_bits_uop_edge_inst}, {stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}}; // @[lsu.scala:209:16, :222:42] wire [31:0][5:0] _GEN_29 = {{stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}, {stq_23_bits_uop_pc_lob}, {stq_22_bits_uop_pc_lob}, {stq_21_bits_uop_pc_lob}, {stq_20_bits_uop_pc_lob}, {stq_19_bits_uop_pc_lob}, {stq_18_bits_uop_pc_lob}, {stq_17_bits_uop_pc_lob}, {stq_16_bits_uop_pc_lob}, {stq_15_bits_uop_pc_lob}, {stq_14_bits_uop_pc_lob}, {stq_13_bits_uop_pc_lob}, {stq_12_bits_uop_pc_lob}, {stq_11_bits_uop_pc_lob}, {stq_10_bits_uop_pc_lob}, {stq_9_bits_uop_pc_lob}, {stq_8_bits_uop_pc_lob}, {stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_30 = {{stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_0_bits_uop_taken}, {stq_23_bits_uop_taken}, {stq_22_bits_uop_taken}, {stq_21_bits_uop_taken}, {stq_20_bits_uop_taken}, {stq_19_bits_uop_taken}, {stq_18_bits_uop_taken}, {stq_17_bits_uop_taken}, {stq_16_bits_uop_taken}, {stq_15_bits_uop_taken}, {stq_14_bits_uop_taken}, {stq_13_bits_uop_taken}, {stq_12_bits_uop_taken}, {stq_11_bits_uop_taken}, {stq_10_bits_uop_taken}, {stq_9_bits_uop_taken}, {stq_8_bits_uop_taken}, {stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}}; // @[lsu.scala:209:16, :222:42] wire [31:0][19:0] _GEN_31 = {{stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}, {stq_23_bits_uop_imm_packed}, {stq_22_bits_uop_imm_packed}, {stq_21_bits_uop_imm_packed}, {stq_20_bits_uop_imm_packed}, {stq_19_bits_uop_imm_packed}, {stq_18_bits_uop_imm_packed}, {stq_17_bits_uop_imm_packed}, {stq_16_bits_uop_imm_packed}, {stq_15_bits_uop_imm_packed}, {stq_14_bits_uop_imm_packed}, {stq_13_bits_uop_imm_packed}, {stq_12_bits_uop_imm_packed}, {stq_11_bits_uop_imm_packed}, {stq_10_bits_uop_imm_packed}, {stq_9_bits_uop_imm_packed}, {stq_8_bits_uop_imm_packed}, {stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}}; // @[lsu.scala:209:16, :222:42] wire [31:0][11:0] _GEN_32 = {{stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}, {stq_23_bits_uop_csr_addr}, {stq_22_bits_uop_csr_addr}, {stq_21_bits_uop_csr_addr}, {stq_20_bits_uop_csr_addr}, {stq_19_bits_uop_csr_addr}, {stq_18_bits_uop_csr_addr}, {stq_17_bits_uop_csr_addr}, {stq_16_bits_uop_csr_addr}, {stq_15_bits_uop_csr_addr}, {stq_14_bits_uop_csr_addr}, {stq_13_bits_uop_csr_addr}, {stq_12_bits_uop_csr_addr}, {stq_11_bits_uop_csr_addr}, {stq_10_bits_uop_csr_addr}, {stq_9_bits_uop_csr_addr}, {stq_8_bits_uop_csr_addr}, {stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_33 = {{stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}, {stq_23_bits_uop_rob_idx}, {stq_22_bits_uop_rob_idx}, {stq_21_bits_uop_rob_idx}, {stq_20_bits_uop_rob_idx}, {stq_19_bits_uop_rob_idx}, {stq_18_bits_uop_rob_idx}, {stq_17_bits_uop_rob_idx}, {stq_16_bits_uop_rob_idx}, {stq_15_bits_uop_rob_idx}, {stq_14_bits_uop_rob_idx}, {stq_13_bits_uop_rob_idx}, {stq_12_bits_uop_rob_idx}, {stq_11_bits_uop_rob_idx}, {stq_10_bits_uop_rob_idx}, {stq_9_bits_uop_rob_idx}, {stq_8_bits_uop_rob_idx}, {stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_34 = {{stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}, {stq_23_bits_uop_ldq_idx}, {stq_22_bits_uop_ldq_idx}, {stq_21_bits_uop_ldq_idx}, {stq_20_bits_uop_ldq_idx}, {stq_19_bits_uop_ldq_idx}, {stq_18_bits_uop_ldq_idx}, {stq_17_bits_uop_ldq_idx}, {stq_16_bits_uop_ldq_idx}, {stq_15_bits_uop_ldq_idx}, {stq_14_bits_uop_ldq_idx}, {stq_13_bits_uop_ldq_idx}, {stq_12_bits_uop_ldq_idx}, {stq_11_bits_uop_ldq_idx}, {stq_10_bits_uop_ldq_idx}, {stq_9_bits_uop_ldq_idx}, {stq_8_bits_uop_ldq_idx}, {stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_35 = {{stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}, {stq_23_bits_uop_stq_idx}, {stq_22_bits_uop_stq_idx}, {stq_21_bits_uop_stq_idx}, {stq_20_bits_uop_stq_idx}, {stq_19_bits_uop_stq_idx}, {stq_18_bits_uop_stq_idx}, {stq_17_bits_uop_stq_idx}, {stq_16_bits_uop_stq_idx}, {stq_15_bits_uop_stq_idx}, {stq_14_bits_uop_stq_idx}, {stq_13_bits_uop_stq_idx}, {stq_12_bits_uop_stq_idx}, {stq_11_bits_uop_stq_idx}, {stq_10_bits_uop_stq_idx}, {stq_9_bits_uop_stq_idx}, {stq_8_bits_uop_stq_idx}, {stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_36 = {{stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}, {stq_23_bits_uop_rxq_idx}, {stq_22_bits_uop_rxq_idx}, {stq_21_bits_uop_rxq_idx}, {stq_20_bits_uop_rxq_idx}, {stq_19_bits_uop_rxq_idx}, {stq_18_bits_uop_rxq_idx}, {stq_17_bits_uop_rxq_idx}, {stq_16_bits_uop_rxq_idx}, {stq_15_bits_uop_rxq_idx}, {stq_14_bits_uop_rxq_idx}, {stq_13_bits_uop_rxq_idx}, {stq_12_bits_uop_rxq_idx}, {stq_11_bits_uop_rxq_idx}, {stq_10_bits_uop_rxq_idx}, {stq_9_bits_uop_rxq_idx}, {stq_8_bits_uop_rxq_idx}, {stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_37 = {{stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_0_bits_uop_pdst}, {stq_23_bits_uop_pdst}, {stq_22_bits_uop_pdst}, {stq_21_bits_uop_pdst}, {stq_20_bits_uop_pdst}, {stq_19_bits_uop_pdst}, {stq_18_bits_uop_pdst}, {stq_17_bits_uop_pdst}, {stq_16_bits_uop_pdst}, {stq_15_bits_uop_pdst}, {stq_14_bits_uop_pdst}, {stq_13_bits_uop_pdst}, {stq_12_bits_uop_pdst}, {stq_11_bits_uop_pdst}, {stq_10_bits_uop_pdst}, {stq_9_bits_uop_pdst}, {stq_8_bits_uop_pdst}, {stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_38 = {{stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_0_bits_uop_prs1}, {stq_23_bits_uop_prs1}, {stq_22_bits_uop_prs1}, {stq_21_bits_uop_prs1}, {stq_20_bits_uop_prs1}, {stq_19_bits_uop_prs1}, {stq_18_bits_uop_prs1}, {stq_17_bits_uop_prs1}, {stq_16_bits_uop_prs1}, {stq_15_bits_uop_prs1}, {stq_14_bits_uop_prs1}, {stq_13_bits_uop_prs1}, {stq_12_bits_uop_prs1}, {stq_11_bits_uop_prs1}, {stq_10_bits_uop_prs1}, {stq_9_bits_uop_prs1}, {stq_8_bits_uop_prs1}, {stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_39 = {{stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_0_bits_uop_prs2}, {stq_23_bits_uop_prs2}, {stq_22_bits_uop_prs2}, {stq_21_bits_uop_prs2}, {stq_20_bits_uop_prs2}, {stq_19_bits_uop_prs2}, {stq_18_bits_uop_prs2}, {stq_17_bits_uop_prs2}, {stq_16_bits_uop_prs2}, {stq_15_bits_uop_prs2}, {stq_14_bits_uop_prs2}, {stq_13_bits_uop_prs2}, {stq_12_bits_uop_prs2}, {stq_11_bits_uop_prs2}, {stq_10_bits_uop_prs2}, {stq_9_bits_uop_prs2}, {stq_8_bits_uop_prs2}, {stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_40 = {{stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_0_bits_uop_prs3}, {stq_23_bits_uop_prs3}, {stq_22_bits_uop_prs3}, {stq_21_bits_uop_prs3}, {stq_20_bits_uop_prs3}, {stq_19_bits_uop_prs3}, {stq_18_bits_uop_prs3}, {stq_17_bits_uop_prs3}, {stq_16_bits_uop_prs3}, {stq_15_bits_uop_prs3}, {stq_14_bits_uop_prs3}, {stq_13_bits_uop_prs3}, {stq_12_bits_uop_prs3}, {stq_11_bits_uop_prs3}, {stq_10_bits_uop_prs3}, {stq_9_bits_uop_prs3}, {stq_8_bits_uop_prs3}, {stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_41 = {{stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_0_bits_uop_ppred}, {stq_23_bits_uop_ppred}, {stq_22_bits_uop_ppred}, {stq_21_bits_uop_ppred}, {stq_20_bits_uop_ppred}, {stq_19_bits_uop_ppred}, {stq_18_bits_uop_ppred}, {stq_17_bits_uop_ppred}, {stq_16_bits_uop_ppred}, {stq_15_bits_uop_ppred}, {stq_14_bits_uop_ppred}, {stq_13_bits_uop_ppred}, {stq_12_bits_uop_ppred}, {stq_11_bits_uop_ppred}, {stq_10_bits_uop_ppred}, {stq_9_bits_uop_ppred}, {stq_8_bits_uop_ppred}, {stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_42 = {{stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}, {stq_23_bits_uop_prs1_busy}, {stq_22_bits_uop_prs1_busy}, {stq_21_bits_uop_prs1_busy}, {stq_20_bits_uop_prs1_busy}, {stq_19_bits_uop_prs1_busy}, {stq_18_bits_uop_prs1_busy}, {stq_17_bits_uop_prs1_busy}, {stq_16_bits_uop_prs1_busy}, {stq_15_bits_uop_prs1_busy}, {stq_14_bits_uop_prs1_busy}, {stq_13_bits_uop_prs1_busy}, {stq_12_bits_uop_prs1_busy}, {stq_11_bits_uop_prs1_busy}, {stq_10_bits_uop_prs1_busy}, {stq_9_bits_uop_prs1_busy}, {stq_8_bits_uop_prs1_busy}, {stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_43 = {{stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}, {stq_23_bits_uop_prs2_busy}, {stq_22_bits_uop_prs2_busy}, {stq_21_bits_uop_prs2_busy}, {stq_20_bits_uop_prs2_busy}, {stq_19_bits_uop_prs2_busy}, {stq_18_bits_uop_prs2_busy}, {stq_17_bits_uop_prs2_busy}, {stq_16_bits_uop_prs2_busy}, {stq_15_bits_uop_prs2_busy}, {stq_14_bits_uop_prs2_busy}, {stq_13_bits_uop_prs2_busy}, {stq_12_bits_uop_prs2_busy}, {stq_11_bits_uop_prs2_busy}, {stq_10_bits_uop_prs2_busy}, {stq_9_bits_uop_prs2_busy}, {stq_8_bits_uop_prs2_busy}, {stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_44 = {{stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}, {stq_23_bits_uop_prs3_busy}, {stq_22_bits_uop_prs3_busy}, {stq_21_bits_uop_prs3_busy}, {stq_20_bits_uop_prs3_busy}, {stq_19_bits_uop_prs3_busy}, {stq_18_bits_uop_prs3_busy}, {stq_17_bits_uop_prs3_busy}, {stq_16_bits_uop_prs3_busy}, {stq_15_bits_uop_prs3_busy}, {stq_14_bits_uop_prs3_busy}, {stq_13_bits_uop_prs3_busy}, {stq_12_bits_uop_prs3_busy}, {stq_11_bits_uop_prs3_busy}, {stq_10_bits_uop_prs3_busy}, {stq_9_bits_uop_prs3_busy}, {stq_8_bits_uop_prs3_busy}, {stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_45 = {{stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}, {stq_23_bits_uop_ppred_busy}, {stq_22_bits_uop_ppred_busy}, {stq_21_bits_uop_ppred_busy}, {stq_20_bits_uop_ppred_busy}, {stq_19_bits_uop_ppred_busy}, {stq_18_bits_uop_ppred_busy}, {stq_17_bits_uop_ppred_busy}, {stq_16_bits_uop_ppred_busy}, {stq_15_bits_uop_ppred_busy}, {stq_14_bits_uop_ppred_busy}, {stq_13_bits_uop_ppred_busy}, {stq_12_bits_uop_ppred_busy}, {stq_11_bits_uop_ppred_busy}, {stq_10_bits_uop_ppred_busy}, {stq_9_bits_uop_ppred_busy}, {stq_8_bits_uop_ppred_busy}, {stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}}; // @[lsu.scala:209:16, :222:42] wire [31:0][6:0] _GEN_46 = {{stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}, {stq_23_bits_uop_stale_pdst}, {stq_22_bits_uop_stale_pdst}, {stq_21_bits_uop_stale_pdst}, {stq_20_bits_uop_stale_pdst}, {stq_19_bits_uop_stale_pdst}, {stq_18_bits_uop_stale_pdst}, {stq_17_bits_uop_stale_pdst}, {stq_16_bits_uop_stale_pdst}, {stq_15_bits_uop_stale_pdst}, {stq_14_bits_uop_stale_pdst}, {stq_13_bits_uop_stale_pdst}, {stq_12_bits_uop_stale_pdst}, {stq_11_bits_uop_stale_pdst}, {stq_10_bits_uop_stale_pdst}, {stq_9_bits_uop_stale_pdst}, {stq_8_bits_uop_stale_pdst}, {stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_47 = {{stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_0_bits_uop_exception}, {stq_23_bits_uop_exception}, {stq_22_bits_uop_exception}, {stq_21_bits_uop_exception}, {stq_20_bits_uop_exception}, {stq_19_bits_uop_exception}, {stq_18_bits_uop_exception}, {stq_17_bits_uop_exception}, {stq_16_bits_uop_exception}, {stq_15_bits_uop_exception}, {stq_14_bits_uop_exception}, {stq_13_bits_uop_exception}, {stq_12_bits_uop_exception}, {stq_11_bits_uop_exception}, {stq_10_bits_uop_exception}, {stq_9_bits_uop_exception}, {stq_8_bits_uop_exception}, {stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}}; // @[lsu.scala:209:16, :222:42] wire _GEN_48 = _GEN_47[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [31:0][63:0] _GEN_49 = {{stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}, {stq_23_bits_uop_exc_cause}, {stq_22_bits_uop_exc_cause}, {stq_21_bits_uop_exc_cause}, {stq_20_bits_uop_exc_cause}, {stq_19_bits_uop_exc_cause}, {stq_18_bits_uop_exc_cause}, {stq_17_bits_uop_exc_cause}, {stq_16_bits_uop_exc_cause}, {stq_15_bits_uop_exc_cause}, {stq_14_bits_uop_exc_cause}, {stq_13_bits_uop_exc_cause}, {stq_12_bits_uop_exc_cause}, {stq_11_bits_uop_exc_cause}, {stq_10_bits_uop_exc_cause}, {stq_9_bits_uop_exc_cause}, {stq_8_bits_uop_exc_cause}, {stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_50 = {{stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}, {stq_23_bits_uop_bypassable}, {stq_22_bits_uop_bypassable}, {stq_21_bits_uop_bypassable}, {stq_20_bits_uop_bypassable}, {stq_19_bits_uop_bypassable}, {stq_18_bits_uop_bypassable}, {stq_17_bits_uop_bypassable}, {stq_16_bits_uop_bypassable}, {stq_15_bits_uop_bypassable}, {stq_14_bits_uop_bypassable}, {stq_13_bits_uop_bypassable}, {stq_12_bits_uop_bypassable}, {stq_11_bits_uop_bypassable}, {stq_10_bits_uop_bypassable}, {stq_9_bits_uop_bypassable}, {stq_8_bits_uop_bypassable}, {stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}}; // @[lsu.scala:209:16, :222:42] wire [31:0][4:0] _GEN_51 = {{stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}, {stq_23_bits_uop_mem_cmd}, {stq_22_bits_uop_mem_cmd}, {stq_21_bits_uop_mem_cmd}, {stq_20_bits_uop_mem_cmd}, {stq_19_bits_uop_mem_cmd}, {stq_18_bits_uop_mem_cmd}, {stq_17_bits_uop_mem_cmd}, {stq_16_bits_uop_mem_cmd}, {stq_15_bits_uop_mem_cmd}, {stq_14_bits_uop_mem_cmd}, {stq_13_bits_uop_mem_cmd}, {stq_12_bits_uop_mem_cmd}, {stq_11_bits_uop_mem_cmd}, {stq_10_bits_uop_mem_cmd}, {stq_9_bits_uop_mem_cmd}, {stq_8_bits_uop_mem_cmd}, {stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_52 = {{stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}, {stq_23_bits_uop_mem_size}, {stq_22_bits_uop_mem_size}, {stq_21_bits_uop_mem_size}, {stq_20_bits_uop_mem_size}, {stq_19_bits_uop_mem_size}, {stq_18_bits_uop_mem_size}, {stq_17_bits_uop_mem_size}, {stq_16_bits_uop_mem_size}, {stq_15_bits_uop_mem_size}, {stq_14_bits_uop_mem_size}, {stq_13_bits_uop_mem_size}, {stq_12_bits_uop_mem_size}, {stq_11_bits_uop_mem_size}, {stq_10_bits_uop_mem_size}, {stq_9_bits_uop_mem_size}, {stq_8_bits_uop_mem_size}, {stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}}; // @[lsu.scala:209:16, :222:42] wire [1:0] dmem_req_0_bits_data_size = _GEN_52[stq_execute_head]; // @[AMOALU.scala:11:18] wire [31:0] _GEN_53 = {{stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}, {stq_23_bits_uop_mem_signed}, {stq_22_bits_uop_mem_signed}, {stq_21_bits_uop_mem_signed}, {stq_20_bits_uop_mem_signed}, {stq_19_bits_uop_mem_signed}, {stq_18_bits_uop_mem_signed}, {stq_17_bits_uop_mem_signed}, {stq_16_bits_uop_mem_signed}, {stq_15_bits_uop_mem_signed}, {stq_14_bits_uop_mem_signed}, {stq_13_bits_uop_mem_signed}, {stq_12_bits_uop_mem_signed}, {stq_11_bits_uop_mem_signed}, {stq_10_bits_uop_mem_signed}, {stq_9_bits_uop_mem_signed}, {stq_8_bits_uop_mem_signed}, {stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_54 = {{stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}, {stq_23_bits_uop_is_fence}, {stq_22_bits_uop_is_fence}, {stq_21_bits_uop_is_fence}, {stq_20_bits_uop_is_fence}, {stq_19_bits_uop_is_fence}, {stq_18_bits_uop_is_fence}, {stq_17_bits_uop_is_fence}, {stq_16_bits_uop_is_fence}, {stq_15_bits_uop_is_fence}, {stq_14_bits_uop_is_fence}, {stq_13_bits_uop_is_fence}, {stq_12_bits_uop_is_fence}, {stq_11_bits_uop_is_fence}, {stq_10_bits_uop_is_fence}, {stq_9_bits_uop_is_fence}, {stq_8_bits_uop_is_fence}, {stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}}; // @[lsu.scala:209:16, :222:42] wire _GEN_55 = _GEN_54[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [31:0] _GEN_56 = {{stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}, {stq_23_bits_uop_is_fencei}, {stq_22_bits_uop_is_fencei}, {stq_21_bits_uop_is_fencei}, {stq_20_bits_uop_is_fencei}, {stq_19_bits_uop_is_fencei}, {stq_18_bits_uop_is_fencei}, {stq_17_bits_uop_is_fencei}, {stq_16_bits_uop_is_fencei}, {stq_15_bits_uop_is_fencei}, {stq_14_bits_uop_is_fencei}, {stq_13_bits_uop_is_fencei}, {stq_12_bits_uop_is_fencei}, {stq_11_bits_uop_is_fencei}, {stq_10_bits_uop_is_fencei}, {stq_9_bits_uop_is_fencei}, {stq_8_bits_uop_is_fencei}, {stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_57 = {{stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}, {stq_23_bits_uop_is_amo}, {stq_22_bits_uop_is_amo}, {stq_21_bits_uop_is_amo}, {stq_20_bits_uop_is_amo}, {stq_19_bits_uop_is_amo}, {stq_18_bits_uop_is_amo}, {stq_17_bits_uop_is_amo}, {stq_16_bits_uop_is_amo}, {stq_15_bits_uop_is_amo}, {stq_14_bits_uop_is_amo}, {stq_13_bits_uop_is_amo}, {stq_12_bits_uop_is_amo}, {stq_11_bits_uop_is_amo}, {stq_10_bits_uop_is_amo}, {stq_9_bits_uop_is_amo}, {stq_8_bits_uop_is_amo}, {stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}}; // @[lsu.scala:209:16, :222:42] wire _GEN_58 = _GEN_57[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [31:0] _GEN_59 = {{stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}, {stq_23_bits_uop_uses_ldq}, {stq_22_bits_uop_uses_ldq}, {stq_21_bits_uop_uses_ldq}, {stq_20_bits_uop_uses_ldq}, {stq_19_bits_uop_uses_ldq}, {stq_18_bits_uop_uses_ldq}, {stq_17_bits_uop_uses_ldq}, {stq_16_bits_uop_uses_ldq}, {stq_15_bits_uop_uses_ldq}, {stq_14_bits_uop_uses_ldq}, {stq_13_bits_uop_uses_ldq}, {stq_12_bits_uop_uses_ldq}, {stq_11_bits_uop_uses_ldq}, {stq_10_bits_uop_uses_ldq}, {stq_9_bits_uop_uses_ldq}, {stq_8_bits_uop_uses_ldq}, {stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_60 = {{stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}, {stq_23_bits_uop_uses_stq}, {stq_22_bits_uop_uses_stq}, {stq_21_bits_uop_uses_stq}, {stq_20_bits_uop_uses_stq}, {stq_19_bits_uop_uses_stq}, {stq_18_bits_uop_uses_stq}, {stq_17_bits_uop_uses_stq}, {stq_16_bits_uop_uses_stq}, {stq_15_bits_uop_uses_stq}, {stq_14_bits_uop_uses_stq}, {stq_13_bits_uop_uses_stq}, {stq_12_bits_uop_uses_stq}, {stq_11_bits_uop_uses_stq}, {stq_10_bits_uop_uses_stq}, {stq_9_bits_uop_uses_stq}, {stq_8_bits_uop_uses_stq}, {stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_61 = {{stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}, {stq_23_bits_uop_is_sys_pc2epc}, {stq_22_bits_uop_is_sys_pc2epc}, {stq_21_bits_uop_is_sys_pc2epc}, {stq_20_bits_uop_is_sys_pc2epc}, {stq_19_bits_uop_is_sys_pc2epc}, {stq_18_bits_uop_is_sys_pc2epc}, {stq_17_bits_uop_is_sys_pc2epc}, {stq_16_bits_uop_is_sys_pc2epc}, {stq_15_bits_uop_is_sys_pc2epc}, {stq_14_bits_uop_is_sys_pc2epc}, {stq_13_bits_uop_is_sys_pc2epc}, {stq_12_bits_uop_is_sys_pc2epc}, {stq_11_bits_uop_is_sys_pc2epc}, {stq_10_bits_uop_is_sys_pc2epc}, {stq_9_bits_uop_is_sys_pc2epc}, {stq_8_bits_uop_is_sys_pc2epc}, {stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_62 = {{stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}, {stq_23_bits_uop_is_unique}, {stq_22_bits_uop_is_unique}, {stq_21_bits_uop_is_unique}, {stq_20_bits_uop_is_unique}, {stq_19_bits_uop_is_unique}, {stq_18_bits_uop_is_unique}, {stq_17_bits_uop_is_unique}, {stq_16_bits_uop_is_unique}, {stq_15_bits_uop_is_unique}, {stq_14_bits_uop_is_unique}, {stq_13_bits_uop_is_unique}, {stq_12_bits_uop_is_unique}, {stq_11_bits_uop_is_unique}, {stq_10_bits_uop_is_unique}, {stq_9_bits_uop_is_unique}, {stq_8_bits_uop_is_unique}, {stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_63 = {{stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}, {stq_23_bits_uop_flush_on_commit}, {stq_22_bits_uop_flush_on_commit}, {stq_21_bits_uop_flush_on_commit}, {stq_20_bits_uop_flush_on_commit}, {stq_19_bits_uop_flush_on_commit}, {stq_18_bits_uop_flush_on_commit}, {stq_17_bits_uop_flush_on_commit}, {stq_16_bits_uop_flush_on_commit}, {stq_15_bits_uop_flush_on_commit}, {stq_14_bits_uop_flush_on_commit}, {stq_13_bits_uop_flush_on_commit}, {stq_12_bits_uop_flush_on_commit}, {stq_11_bits_uop_flush_on_commit}, {stq_10_bits_uop_flush_on_commit}, {stq_9_bits_uop_flush_on_commit}, {stq_8_bits_uop_flush_on_commit}, {stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_64 = {{stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}, {stq_23_bits_uop_ldst_is_rs1}, {stq_22_bits_uop_ldst_is_rs1}, {stq_21_bits_uop_ldst_is_rs1}, {stq_20_bits_uop_ldst_is_rs1}, {stq_19_bits_uop_ldst_is_rs1}, {stq_18_bits_uop_ldst_is_rs1}, {stq_17_bits_uop_ldst_is_rs1}, {stq_16_bits_uop_ldst_is_rs1}, {stq_15_bits_uop_ldst_is_rs1}, {stq_14_bits_uop_ldst_is_rs1}, {stq_13_bits_uop_ldst_is_rs1}, {stq_12_bits_uop_ldst_is_rs1}, {stq_11_bits_uop_ldst_is_rs1}, {stq_10_bits_uop_ldst_is_rs1}, {stq_9_bits_uop_ldst_is_rs1}, {stq_8_bits_uop_ldst_is_rs1}, {stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:209:16, :222:42] wire [31:0][5:0] _GEN_65 = {{stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_0_bits_uop_ldst}, {stq_23_bits_uop_ldst}, {stq_22_bits_uop_ldst}, {stq_21_bits_uop_ldst}, {stq_20_bits_uop_ldst}, {stq_19_bits_uop_ldst}, {stq_18_bits_uop_ldst}, {stq_17_bits_uop_ldst}, {stq_16_bits_uop_ldst}, {stq_15_bits_uop_ldst}, {stq_14_bits_uop_ldst}, {stq_13_bits_uop_ldst}, {stq_12_bits_uop_ldst}, {stq_11_bits_uop_ldst}, {stq_10_bits_uop_ldst}, {stq_9_bits_uop_ldst}, {stq_8_bits_uop_ldst}, {stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}}; // @[lsu.scala:209:16, :222:42] wire [31:0][5:0] _GEN_66 = {{stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}, {stq_23_bits_uop_lrs1}, {stq_22_bits_uop_lrs1}, {stq_21_bits_uop_lrs1}, {stq_20_bits_uop_lrs1}, {stq_19_bits_uop_lrs1}, {stq_18_bits_uop_lrs1}, {stq_17_bits_uop_lrs1}, {stq_16_bits_uop_lrs1}, {stq_15_bits_uop_lrs1}, {stq_14_bits_uop_lrs1}, {stq_13_bits_uop_lrs1}, {stq_12_bits_uop_lrs1}, {stq_11_bits_uop_lrs1}, {stq_10_bits_uop_lrs1}, {stq_9_bits_uop_lrs1}, {stq_8_bits_uop_lrs1}, {stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}}; // @[lsu.scala:209:16, :222:42] wire [31:0][5:0] _GEN_67 = {{stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}, {stq_23_bits_uop_lrs2}, {stq_22_bits_uop_lrs2}, {stq_21_bits_uop_lrs2}, {stq_20_bits_uop_lrs2}, {stq_19_bits_uop_lrs2}, {stq_18_bits_uop_lrs2}, {stq_17_bits_uop_lrs2}, {stq_16_bits_uop_lrs2}, {stq_15_bits_uop_lrs2}, {stq_14_bits_uop_lrs2}, {stq_13_bits_uop_lrs2}, {stq_12_bits_uop_lrs2}, {stq_11_bits_uop_lrs2}, {stq_10_bits_uop_lrs2}, {stq_9_bits_uop_lrs2}, {stq_8_bits_uop_lrs2}, {stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}}; // @[lsu.scala:209:16, :222:42] wire [31:0][5:0] _GEN_68 = {{stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}, {stq_23_bits_uop_lrs3}, {stq_22_bits_uop_lrs3}, {stq_21_bits_uop_lrs3}, {stq_20_bits_uop_lrs3}, {stq_19_bits_uop_lrs3}, {stq_18_bits_uop_lrs3}, {stq_17_bits_uop_lrs3}, {stq_16_bits_uop_lrs3}, {stq_15_bits_uop_lrs3}, {stq_14_bits_uop_lrs3}, {stq_13_bits_uop_lrs3}, {stq_12_bits_uop_lrs3}, {stq_11_bits_uop_lrs3}, {stq_10_bits_uop_lrs3}, {stq_9_bits_uop_lrs3}, {stq_8_bits_uop_lrs3}, {stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_69 = {{stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}, {stq_23_bits_uop_ldst_val}, {stq_22_bits_uop_ldst_val}, {stq_21_bits_uop_ldst_val}, {stq_20_bits_uop_ldst_val}, {stq_19_bits_uop_ldst_val}, {stq_18_bits_uop_ldst_val}, {stq_17_bits_uop_ldst_val}, {stq_16_bits_uop_ldst_val}, {stq_15_bits_uop_ldst_val}, {stq_14_bits_uop_ldst_val}, {stq_13_bits_uop_ldst_val}, {stq_12_bits_uop_ldst_val}, {stq_11_bits_uop_ldst_val}, {stq_10_bits_uop_ldst_val}, {stq_9_bits_uop_ldst_val}, {stq_8_bits_uop_ldst_val}, {stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_70 = {{stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}, {stq_23_bits_uop_dst_rtype}, {stq_22_bits_uop_dst_rtype}, {stq_21_bits_uop_dst_rtype}, {stq_20_bits_uop_dst_rtype}, {stq_19_bits_uop_dst_rtype}, {stq_18_bits_uop_dst_rtype}, {stq_17_bits_uop_dst_rtype}, {stq_16_bits_uop_dst_rtype}, {stq_15_bits_uop_dst_rtype}, {stq_14_bits_uop_dst_rtype}, {stq_13_bits_uop_dst_rtype}, {stq_12_bits_uop_dst_rtype}, {stq_11_bits_uop_dst_rtype}, {stq_10_bits_uop_dst_rtype}, {stq_9_bits_uop_dst_rtype}, {stq_8_bits_uop_dst_rtype}, {stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_71 = {{stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}, {stq_23_bits_uop_lrs1_rtype}, {stq_22_bits_uop_lrs1_rtype}, {stq_21_bits_uop_lrs1_rtype}, {stq_20_bits_uop_lrs1_rtype}, {stq_19_bits_uop_lrs1_rtype}, {stq_18_bits_uop_lrs1_rtype}, {stq_17_bits_uop_lrs1_rtype}, {stq_16_bits_uop_lrs1_rtype}, {stq_15_bits_uop_lrs1_rtype}, {stq_14_bits_uop_lrs1_rtype}, {stq_13_bits_uop_lrs1_rtype}, {stq_12_bits_uop_lrs1_rtype}, {stq_11_bits_uop_lrs1_rtype}, {stq_10_bits_uop_lrs1_rtype}, {stq_9_bits_uop_lrs1_rtype}, {stq_8_bits_uop_lrs1_rtype}, {stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_72 = {{stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}, {stq_23_bits_uop_lrs2_rtype}, {stq_22_bits_uop_lrs2_rtype}, {stq_21_bits_uop_lrs2_rtype}, {stq_20_bits_uop_lrs2_rtype}, {stq_19_bits_uop_lrs2_rtype}, {stq_18_bits_uop_lrs2_rtype}, {stq_17_bits_uop_lrs2_rtype}, {stq_16_bits_uop_lrs2_rtype}, {stq_15_bits_uop_lrs2_rtype}, {stq_14_bits_uop_lrs2_rtype}, {stq_13_bits_uop_lrs2_rtype}, {stq_12_bits_uop_lrs2_rtype}, {stq_11_bits_uop_lrs2_rtype}, {stq_10_bits_uop_lrs2_rtype}, {stq_9_bits_uop_lrs2_rtype}, {stq_8_bits_uop_lrs2_rtype}, {stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_73 = {{stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}, {stq_23_bits_uop_frs3_en}, {stq_22_bits_uop_frs3_en}, {stq_21_bits_uop_frs3_en}, {stq_20_bits_uop_frs3_en}, {stq_19_bits_uop_frs3_en}, {stq_18_bits_uop_frs3_en}, {stq_17_bits_uop_frs3_en}, {stq_16_bits_uop_frs3_en}, {stq_15_bits_uop_frs3_en}, {stq_14_bits_uop_frs3_en}, {stq_13_bits_uop_frs3_en}, {stq_12_bits_uop_frs3_en}, {stq_11_bits_uop_frs3_en}, {stq_10_bits_uop_frs3_en}, {stq_9_bits_uop_frs3_en}, {stq_8_bits_uop_frs3_en}, {stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_74 = {{stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}, {stq_23_bits_uop_fp_val}, {stq_22_bits_uop_fp_val}, {stq_21_bits_uop_fp_val}, {stq_20_bits_uop_fp_val}, {stq_19_bits_uop_fp_val}, {stq_18_bits_uop_fp_val}, {stq_17_bits_uop_fp_val}, {stq_16_bits_uop_fp_val}, {stq_15_bits_uop_fp_val}, {stq_14_bits_uop_fp_val}, {stq_13_bits_uop_fp_val}, {stq_12_bits_uop_fp_val}, {stq_11_bits_uop_fp_val}, {stq_10_bits_uop_fp_val}, {stq_9_bits_uop_fp_val}, {stq_8_bits_uop_fp_val}, {stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_75 = {{stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}, {stq_23_bits_uop_fp_single}, {stq_22_bits_uop_fp_single}, {stq_21_bits_uop_fp_single}, {stq_20_bits_uop_fp_single}, {stq_19_bits_uop_fp_single}, {stq_18_bits_uop_fp_single}, {stq_17_bits_uop_fp_single}, {stq_16_bits_uop_fp_single}, {stq_15_bits_uop_fp_single}, {stq_14_bits_uop_fp_single}, {stq_13_bits_uop_fp_single}, {stq_12_bits_uop_fp_single}, {stq_11_bits_uop_fp_single}, {stq_10_bits_uop_fp_single}, {stq_9_bits_uop_fp_single}, {stq_8_bits_uop_fp_single}, {stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_76 = {{stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}, {stq_23_bits_uop_xcpt_pf_if}, {stq_22_bits_uop_xcpt_pf_if}, {stq_21_bits_uop_xcpt_pf_if}, {stq_20_bits_uop_xcpt_pf_if}, {stq_19_bits_uop_xcpt_pf_if}, {stq_18_bits_uop_xcpt_pf_if}, {stq_17_bits_uop_xcpt_pf_if}, {stq_16_bits_uop_xcpt_pf_if}, {stq_15_bits_uop_xcpt_pf_if}, {stq_14_bits_uop_xcpt_pf_if}, {stq_13_bits_uop_xcpt_pf_if}, {stq_12_bits_uop_xcpt_pf_if}, {stq_11_bits_uop_xcpt_pf_if}, {stq_10_bits_uop_xcpt_pf_if}, {stq_9_bits_uop_xcpt_pf_if}, {stq_8_bits_uop_xcpt_pf_if}, {stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_77 = {{stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}, {stq_23_bits_uop_xcpt_ae_if}, {stq_22_bits_uop_xcpt_ae_if}, {stq_21_bits_uop_xcpt_ae_if}, {stq_20_bits_uop_xcpt_ae_if}, {stq_19_bits_uop_xcpt_ae_if}, {stq_18_bits_uop_xcpt_ae_if}, {stq_17_bits_uop_xcpt_ae_if}, {stq_16_bits_uop_xcpt_ae_if}, {stq_15_bits_uop_xcpt_ae_if}, {stq_14_bits_uop_xcpt_ae_if}, {stq_13_bits_uop_xcpt_ae_if}, {stq_12_bits_uop_xcpt_ae_if}, {stq_11_bits_uop_xcpt_ae_if}, {stq_10_bits_uop_xcpt_ae_if}, {stq_9_bits_uop_xcpt_ae_if}, {stq_8_bits_uop_xcpt_ae_if}, {stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_78 = {{stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}, {stq_23_bits_uop_xcpt_ma_if}, {stq_22_bits_uop_xcpt_ma_if}, {stq_21_bits_uop_xcpt_ma_if}, {stq_20_bits_uop_xcpt_ma_if}, {stq_19_bits_uop_xcpt_ma_if}, {stq_18_bits_uop_xcpt_ma_if}, {stq_17_bits_uop_xcpt_ma_if}, {stq_16_bits_uop_xcpt_ma_if}, {stq_15_bits_uop_xcpt_ma_if}, {stq_14_bits_uop_xcpt_ma_if}, {stq_13_bits_uop_xcpt_ma_if}, {stq_12_bits_uop_xcpt_ma_if}, {stq_11_bits_uop_xcpt_ma_if}, {stq_10_bits_uop_xcpt_ma_if}, {stq_9_bits_uop_xcpt_ma_if}, {stq_8_bits_uop_xcpt_ma_if}, {stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_79 = {{stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}, {stq_23_bits_uop_bp_debug_if}, {stq_22_bits_uop_bp_debug_if}, {stq_21_bits_uop_bp_debug_if}, {stq_20_bits_uop_bp_debug_if}, {stq_19_bits_uop_bp_debug_if}, {stq_18_bits_uop_bp_debug_if}, {stq_17_bits_uop_bp_debug_if}, {stq_16_bits_uop_bp_debug_if}, {stq_15_bits_uop_bp_debug_if}, {stq_14_bits_uop_bp_debug_if}, {stq_13_bits_uop_bp_debug_if}, {stq_12_bits_uop_bp_debug_if}, {stq_11_bits_uop_bp_debug_if}, {stq_10_bits_uop_bp_debug_if}, {stq_9_bits_uop_bp_debug_if}, {stq_8_bits_uop_bp_debug_if}, {stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_80 = {{stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}, {stq_23_bits_uop_bp_xcpt_if}, {stq_22_bits_uop_bp_xcpt_if}, {stq_21_bits_uop_bp_xcpt_if}, {stq_20_bits_uop_bp_xcpt_if}, {stq_19_bits_uop_bp_xcpt_if}, {stq_18_bits_uop_bp_xcpt_if}, {stq_17_bits_uop_bp_xcpt_if}, {stq_16_bits_uop_bp_xcpt_if}, {stq_15_bits_uop_bp_xcpt_if}, {stq_14_bits_uop_bp_xcpt_if}, {stq_13_bits_uop_bp_xcpt_if}, {stq_12_bits_uop_bp_xcpt_if}, {stq_11_bits_uop_bp_xcpt_if}, {stq_10_bits_uop_bp_xcpt_if}, {stq_9_bits_uop_bp_xcpt_if}, {stq_8_bits_uop_bp_xcpt_if}, {stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_81 = {{stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}, {stq_23_bits_uop_debug_fsrc}, {stq_22_bits_uop_debug_fsrc}, {stq_21_bits_uop_debug_fsrc}, {stq_20_bits_uop_debug_fsrc}, {stq_19_bits_uop_debug_fsrc}, {stq_18_bits_uop_debug_fsrc}, {stq_17_bits_uop_debug_fsrc}, {stq_16_bits_uop_debug_fsrc}, {stq_15_bits_uop_debug_fsrc}, {stq_14_bits_uop_debug_fsrc}, {stq_13_bits_uop_debug_fsrc}, {stq_12_bits_uop_debug_fsrc}, {stq_11_bits_uop_debug_fsrc}, {stq_10_bits_uop_debug_fsrc}, {stq_9_bits_uop_debug_fsrc}, {stq_8_bits_uop_debug_fsrc}, {stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:209:16, :222:42] wire [31:0][1:0] _GEN_82 = {{stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}, {stq_23_bits_uop_debug_tsrc}, {stq_22_bits_uop_debug_tsrc}, {stq_21_bits_uop_debug_tsrc}, {stq_20_bits_uop_debug_tsrc}, {stq_19_bits_uop_debug_tsrc}, {stq_18_bits_uop_debug_tsrc}, {stq_17_bits_uop_debug_tsrc}, {stq_16_bits_uop_debug_tsrc}, {stq_15_bits_uop_debug_tsrc}, {stq_14_bits_uop_debug_tsrc}, {stq_13_bits_uop_debug_tsrc}, {stq_12_bits_uop_debug_tsrc}, {stq_11_bits_uop_debug_tsrc}, {stq_10_bits_uop_debug_tsrc}, {stq_9_bits_uop_debug_tsrc}, {stq_8_bits_uop_debug_tsrc}, {stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_83 = {{stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_0_bits_addr_valid}, {stq_23_bits_addr_valid}, {stq_22_bits_addr_valid}, {stq_21_bits_addr_valid}, {stq_20_bits_addr_valid}, {stq_19_bits_addr_valid}, {stq_18_bits_addr_valid}, {stq_17_bits_addr_valid}, {stq_16_bits_addr_valid}, {stq_15_bits_addr_valid}, {stq_14_bits_addr_valid}, {stq_13_bits_addr_valid}, {stq_12_bits_addr_valid}, {stq_11_bits_addr_valid}, {stq_10_bits_addr_valid}, {stq_9_bits_addr_valid}, {stq_8_bits_addr_valid}, {stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}}; // @[lsu.scala:209:16, :222:42] wire [31:0][39:0] _GEN_84 = {{stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_0_bits_addr_bits}, {stq_23_bits_addr_bits}, {stq_22_bits_addr_bits}, {stq_21_bits_addr_bits}, {stq_20_bits_addr_bits}, {stq_19_bits_addr_bits}, {stq_18_bits_addr_bits}, {stq_17_bits_addr_bits}, {stq_16_bits_addr_bits}, {stq_15_bits_addr_bits}, {stq_14_bits_addr_bits}, {stq_13_bits_addr_bits}, {stq_12_bits_addr_bits}, {stq_11_bits_addr_bits}, {stq_10_bits_addr_bits}, {stq_9_bits_addr_bits}, {stq_8_bits_addr_bits}, {stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_85 = {{stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}, {stq_23_bits_addr_is_virtual}, {stq_22_bits_addr_is_virtual}, {stq_21_bits_addr_is_virtual}, {stq_20_bits_addr_is_virtual}, {stq_19_bits_addr_is_virtual}, {stq_18_bits_addr_is_virtual}, {stq_17_bits_addr_is_virtual}, {stq_16_bits_addr_is_virtual}, {stq_15_bits_addr_is_virtual}, {stq_14_bits_addr_is_virtual}, {stq_13_bits_addr_is_virtual}, {stq_12_bits_addr_is_virtual}, {stq_11_bits_addr_is_virtual}, {stq_10_bits_addr_is_virtual}, {stq_9_bits_addr_is_virtual}, {stq_8_bits_addr_is_virtual}, {stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}}; // @[lsu.scala:209:16, :222:42] wire [31:0] _GEN_86 = {{stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_0_bits_data_valid}, {stq_23_bits_data_valid}, {stq_22_bits_data_valid}, {stq_21_bits_data_valid}, {stq_20_bits_data_valid}, {stq_19_bits_data_valid}, {stq_18_bits_data_valid}, {stq_17_bits_data_valid}, {stq_16_bits_data_valid}, {stq_15_bits_data_valid}, {stq_14_bits_data_valid}, {stq_13_bits_data_valid}, {stq_12_bits_data_valid}, {stq_11_bits_data_valid}, {stq_10_bits_data_valid}, {stq_9_bits_data_valid}, {stq_8_bits_data_valid}, {stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}}; // @[lsu.scala:209:16, :222:42] wire [31:0][63:0] _GEN_87 = {{stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_0_bits_data_bits}, {stq_23_bits_data_bits}, {stq_22_bits_data_bits}, {stq_21_bits_data_bits}, {stq_20_bits_data_bits}, {stq_19_bits_data_bits}, {stq_18_bits_data_bits}, {stq_17_bits_data_bits}, {stq_16_bits_data_bits}, {stq_15_bits_data_bits}, {stq_14_bits_data_bits}, {stq_13_bits_data_bits}, {stq_12_bits_data_bits}, {stq_11_bits_data_bits}, {stq_10_bits_data_bits}, {stq_9_bits_data_bits}, {stq_8_bits_data_bits}, {stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}}; // @[lsu.scala:209:16, :222:42] wire [63:0] _GEN_88 = _GEN_87[stq_execute_head]; // @[lsu.scala:218:29, :222:42] wire [31:0] _GEN_89 = {{stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_0_bits_committed}, {stq_23_bits_committed}, {stq_22_bits_committed}, {stq_21_bits_committed}, {stq_20_bits_committed}, {stq_19_bits_committed}, {stq_18_bits_committed}, {stq_17_bits_committed}, {stq_16_bits_committed}, {stq_15_bits_committed}, {stq_14_bits_committed}, {stq_13_bits_committed}, {stq_12_bits_committed}, {stq_11_bits_committed}, {stq_10_bits_committed}, {stq_9_bits_committed}, {stq_8_bits_committed}, {stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}}; // @[lsu.scala:209:16, :222:42] reg [2:0] hella_state; // @[lsu.scala:240:38] reg [39:0] hella_req_addr; // @[lsu.scala:241:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:201:7, :241:34] reg hella_req_dv; // @[lsu.scala:241:34] reg [63:0] hella_data_data; // @[lsu.scala:242:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:242:34] reg [31:0] hella_paddr; // @[lsu.scala:243:34] reg hella_xcpt_ma_ld; // @[lsu.scala:244:34] reg hella_xcpt_ma_st; // @[lsu.scala:244:34] reg hella_xcpt_pf_ld; // @[lsu.scala:244:34] reg hella_xcpt_pf_st; // @[lsu.scala:244:34] reg hella_xcpt_gf_ld; // @[lsu.scala:244:34] reg hella_xcpt_gf_st; // @[lsu.scala:244:34] reg hella_xcpt_ae_ld; // @[lsu.scala:244:34] reg hella_xcpt_ae_st; // @[lsu.scala:244:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:257:33] reg [23:0] live_store_mask; // @[lsu.scala:258:32] wire [31:0] _GEN_90 = 32'h1 << stq_head; // @[lsu.scala:215:29, :259:71] wire [31:0] _next_live_store_mask_T; // @[lsu.scala:259:71] assign _next_live_store_mask_T = _GEN_90; // @[lsu.scala:259:71] wire [31:0] _ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_0_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_1_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_2_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_3_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_4_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_5_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_6_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_7_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_8_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_8_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_9_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_9_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_10_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_10_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_11_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_11_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_12_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_12_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_13_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_13_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_14_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_14_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_15_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_15_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_16_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_16_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_17_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_17_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_18_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_18_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_19_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_19_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_20_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_20_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_21_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_21_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_22_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_22_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _ldq_23_bits_st_dep_mask_T; // @[lsu.scala:277:66] assign _ldq_23_bits_st_dep_mask_T = _GEN_90; // @[lsu.scala:259:71, :277:66] wire [31:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:259:{65,71}] wire [31:0] _next_live_store_mask_T_2 = {8'h0, _next_live_store_mask_T_1[23:0] & live_store_mask}; // @[lsu.scala:258:32, :259:{63,65}] wire [31:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : {8'h0, live_store_mask}; // @[lsu.scala:257:33, :258:32, :259:{33,63}] wire [31:0] _ldq_0_bits_st_dep_mask_T_1 = ~_ldq_0_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_0_bits_st_dep_mask_T_2 = {8'h0, _ldq_0_bits_st_dep_mask_T_1[23:0] & ldq_0_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_1_bits_st_dep_mask_T_1 = ~_ldq_1_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_1_bits_st_dep_mask_T_2 = {8'h0, _ldq_1_bits_st_dep_mask_T_1[23:0] & ldq_1_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_2_bits_st_dep_mask_T_1 = ~_ldq_2_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_2_bits_st_dep_mask_T_2 = {8'h0, _ldq_2_bits_st_dep_mask_T_1[23:0] & ldq_2_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_3_bits_st_dep_mask_T_1 = ~_ldq_3_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_3_bits_st_dep_mask_T_2 = {8'h0, _ldq_3_bits_st_dep_mask_T_1[23:0] & ldq_3_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_4_bits_st_dep_mask_T_1 = ~_ldq_4_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_4_bits_st_dep_mask_T_2 = {8'h0, _ldq_4_bits_st_dep_mask_T_1[23:0] & ldq_4_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_5_bits_st_dep_mask_T_1 = ~_ldq_5_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_5_bits_st_dep_mask_T_2 = {8'h0, _ldq_5_bits_st_dep_mask_T_1[23:0] & ldq_5_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_6_bits_st_dep_mask_T_1 = ~_ldq_6_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_6_bits_st_dep_mask_T_2 = {8'h0, _ldq_6_bits_st_dep_mask_T_1[23:0] & ldq_6_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_7_bits_st_dep_mask_T_1 = ~_ldq_7_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_7_bits_st_dep_mask_T_2 = {8'h0, _ldq_7_bits_st_dep_mask_T_1[23:0] & ldq_7_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_8_bits_st_dep_mask_T_1 = ~_ldq_8_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_8_bits_st_dep_mask_T_2 = {8'h0, _ldq_8_bits_st_dep_mask_T_1[23:0] & ldq_8_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_9_bits_st_dep_mask_T_1 = ~_ldq_9_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_9_bits_st_dep_mask_T_2 = {8'h0, _ldq_9_bits_st_dep_mask_T_1[23:0] & ldq_9_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_10_bits_st_dep_mask_T_1 = ~_ldq_10_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_10_bits_st_dep_mask_T_2 = {8'h0, _ldq_10_bits_st_dep_mask_T_1[23:0] & ldq_10_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_11_bits_st_dep_mask_T_1 = ~_ldq_11_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_11_bits_st_dep_mask_T_2 = {8'h0, _ldq_11_bits_st_dep_mask_T_1[23:0] & ldq_11_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_12_bits_st_dep_mask_T_1 = ~_ldq_12_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_12_bits_st_dep_mask_T_2 = {8'h0, _ldq_12_bits_st_dep_mask_T_1[23:0] & ldq_12_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_13_bits_st_dep_mask_T_1 = ~_ldq_13_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_13_bits_st_dep_mask_T_2 = {8'h0, _ldq_13_bits_st_dep_mask_T_1[23:0] & ldq_13_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_14_bits_st_dep_mask_T_1 = ~_ldq_14_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_14_bits_st_dep_mask_T_2 = {8'h0, _ldq_14_bits_st_dep_mask_T_1[23:0] & ldq_14_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_15_bits_st_dep_mask_T_1 = ~_ldq_15_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_15_bits_st_dep_mask_T_2 = {8'h0, _ldq_15_bits_st_dep_mask_T_1[23:0] & ldq_15_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_16_bits_st_dep_mask_T_1 = ~_ldq_16_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_16_bits_st_dep_mask_T_2 = {8'h0, _ldq_16_bits_st_dep_mask_T_1[23:0] & ldq_16_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_17_bits_st_dep_mask_T_1 = ~_ldq_17_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_17_bits_st_dep_mask_T_2 = {8'h0, _ldq_17_bits_st_dep_mask_T_1[23:0] & ldq_17_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_18_bits_st_dep_mask_T_1 = ~_ldq_18_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_18_bits_st_dep_mask_T_2 = {8'h0, _ldq_18_bits_st_dep_mask_T_1[23:0] & ldq_18_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_19_bits_st_dep_mask_T_1 = ~_ldq_19_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_19_bits_st_dep_mask_T_2 = {8'h0, _ldq_19_bits_st_dep_mask_T_1[23:0] & ldq_19_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_20_bits_st_dep_mask_T_1 = ~_ldq_20_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_20_bits_st_dep_mask_T_2 = {8'h0, _ldq_20_bits_st_dep_mask_T_1[23:0] & ldq_20_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_21_bits_st_dep_mask_T_1 = ~_ldq_21_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_21_bits_st_dep_mask_T_2 = {8'h0, _ldq_21_bits_st_dep_mask_T_1[23:0] & ldq_21_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_22_bits_st_dep_mask_T_1 = ~_ldq_22_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_22_bits_st_dep_mask_T_2 = {8'h0, _ldq_22_bits_st_dep_mask_T_1[23:0] & ldq_22_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire [31:0] _ldq_23_bits_st_dep_mask_T_1 = ~_ldq_23_bits_st_dep_mask_T; // @[lsu.scala:277:{60,66}] wire [31:0] _ldq_23_bits_st_dep_mask_T_2 = {8'h0, _ldq_23_bits_st_dep_mask_T_1[23:0] & ldq_23_bits_st_dep_mask}; // @[lsu.scala:208:16, :277:{58,60}] wire _GEN_91 = stq_0_valid | stq_1_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T; // @[lsu.scala:285:79] assign _stq_nonempty_T = _GEN_91; // @[lsu.scala:285:79] wire _io_hellacache_store_pending_T; // @[lsu.scala:1530:59] assign _io_hellacache_store_pending_T = _GEN_91; // @[lsu.scala:285:79, :1530:59] wire _stq_nonempty_T_1 = _stq_nonempty_T | stq_2_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 | stq_3_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 | stq_4_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 | stq_5_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 | stq_6_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 | stq_7_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_7 = _stq_nonempty_T_6 | stq_8_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_8 = _stq_nonempty_T_7 | stq_9_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_9 = _stq_nonempty_T_8 | stq_10_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_10 = _stq_nonempty_T_9 | stq_11_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_11 = _stq_nonempty_T_10 | stq_12_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_12 = _stq_nonempty_T_11 | stq_13_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_13 = _stq_nonempty_T_12 | stq_14_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_14 = _stq_nonempty_T_13 | stq_15_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_15 = _stq_nonempty_T_14 | stq_16_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_16 = _stq_nonempty_T_15 | stq_17_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_17 = _stq_nonempty_T_16 | stq_18_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_18 = _stq_nonempty_T_17 | stq_19_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_19 = _stq_nonempty_T_18 | stq_20_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_20 = _stq_nonempty_T_19 | stq_21_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_21 = _stq_nonempty_T_20 | stq_22_valid; // @[lsu.scala:209:16, :285:79] wire _stq_nonempty_T_22 = _stq_nonempty_T_21 | stq_23_valid; // @[lsu.scala:209:16, :285:79] wire stq_nonempty = _stq_nonempty_T_22; // @[lsu.scala:285:{79,84}] wire _GEN_92 = ldq_tail == 5'h17; // @[util.scala:205:25] wire wrap; // @[util.scala:205:25] assign wrap = _GEN_92; // @[util.scala:205:25] wire wrap_2; // @[util.scala:205:25] assign wrap_2 = _GEN_92; // @[util.scala:205:25] wire [4:0] _T_32 = ldq_tail + 5'h1; // @[util.scala:206:28] assign io_core_ldq_full_0_0 = (wrap ? 5'h0 : _T_32) == ldq_head; // @[util.scala:205:25, :206:{10,28}] wire _GEN_93 = stq_tail == 5'h17; // @[util.scala:205:25] wire wrap_1; // @[util.scala:205:25] assign wrap_1 = _GEN_93; // @[util.scala:205:25] wire wrap_3; // @[util.scala:205:25] assign wrap_3 = _GEN_93; // @[util.scala:205:25] wire [4:0] _T_39 = stq_tail + 5'h1; // @[util.scala:206:28] assign io_core_stq_full_0_0 = (wrap_1 ? 5'h0 : _T_39) == stq_head; // @[util.scala:205:25, :206:{10,28}] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:300:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:301:{48,85,88}] wire [31:0] _GEN_94 = {{ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_0_valid}, {ldq_23_valid}, {ldq_22_valid}, {ldq_21_valid}, {ldq_20_valid}, {ldq_19_valid}, {ldq_18_valid}, {ldq_17_valid}, {ldq_16_valid}, {ldq_15_valid}, {ldq_14_valid}, {ldq_13_valid}, {ldq_12_valid}, {ldq_11_valid}, {ldq_10_valid}, {ldq_9_valid}, {ldq_8_valid}, {ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}}; // @[lsu.scala:208:16, :304:44] wire [4:0] _T_34 = wrap_2 ? 5'h0 : _T_32; // @[util.scala:205:25, :206:{10,28}] assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_34 : ldq_tail; // @[util.scala:206:10] wire [31:0] _T_36 = 32'h1 << stq_tail; // @[lsu.scala:216:29, :335:72] wire [23:0] _T_38 = {24{dis_st_val}} & _T_36[23:0] | next_live_store_mask[23:0]; // @[lsu.scala:259:33, :301:85, :307:44, :335:{31,72}] wire [4:0] _T_41 = wrap_3 ? 5'h0 : _T_39; // @[util.scala:205:25, :206:{10,28}] assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_41 : stq_tail; // @[util.scala:206:10] wire _GEN_95 = io_core_dis_ldq_idx_1_0 == 5'h17; // @[util.scala:205:25] wire wrap_4; // @[util.scala:205:25] assign wrap_4 = _GEN_95; // @[util.scala:205:25] wire wrap_6; // @[util.scala:205:25] assign wrap_6 = _GEN_95; // @[util.scala:205:25] wire [4:0] _T_72 = io_core_dis_ldq_idx_1_0 + 5'h1; // @[util.scala:206:28] assign io_core_ldq_full_1_0 = (wrap_4 ? 5'h0 : _T_72) == ldq_head; // @[util.scala:205:25, :206:{10,28}] wire _GEN_96 = io_core_dis_stq_idx_1_0 == 5'h17; // @[util.scala:205:25] wire wrap_5; // @[util.scala:205:25] assign wrap_5 = _GEN_96; // @[util.scala:205:25] wire wrap_7; // @[util.scala:205:25] assign wrap_7 = _GEN_96; // @[util.scala:205:25] wire [4:0] _T_79 = io_core_dis_stq_idx_1_0 + 5'h1; // @[util.scala:206:28] assign io_core_stq_full_1_0 = (wrap_5 ? 5'h0 : _T_79) == stq_head; // @[util.scala:205:25, :206:{10,28}] wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48] wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:201:7, :300:88] wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:300:{48,85,88}] wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48] wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88] wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:301:{48,85,88}] wire [4:0] _T_74 = wrap_6 ? 5'h0 : _T_72; // @[util.scala:205:25, :206:{10,28}] assign io_core_dis_ldq_idx_2_0 = dis_ld_val_1 ? _T_74 : io_core_dis_ldq_idx_1_0; // @[util.scala:206:10] wire [31:0] _T_76 = 32'h1 << io_core_dis_stq_idx_1_0; // @[lsu.scala:201:7, :335:72] wire [23:0] _T_78 = {24{dis_st_val_1}} & _T_76[23:0] | _T_38; // @[lsu.scala:301:85, :335:{31,72}] wire [4:0] _T_81 = wrap_7 ? 5'h0 : _T_79; // @[util.scala:205:25, :206:{10,28}] assign io_core_dis_stq_idx_2_0 = dis_st_val_1 ? _T_81 : io_core_dis_stq_idx_1_0; // @[util.scala:206:10] wire _GEN_97 = io_core_dis_ldq_idx_2_0 == 5'h17; // @[util.scala:205:25] wire wrap_8; // @[util.scala:205:25] assign wrap_8 = _GEN_97; // @[util.scala:205:25] wire wrap_10; // @[util.scala:205:25] assign wrap_10 = _GEN_97; // @[util.scala:205:25] wire [4:0] _T_112 = io_core_dis_ldq_idx_2_0 + 5'h1; // @[util.scala:206:28] assign io_core_ldq_full_2_0 = (wrap_8 ? 5'h0 : _T_112) == ldq_head; // @[util.scala:205:25, :206:{10,28}] wire _GEN_98 = io_core_dis_stq_idx_2_0 == 5'h17; // @[util.scala:205:25] wire wrap_9; // @[util.scala:205:25] assign wrap_9 = _GEN_98; // @[util.scala:205:25] wire wrap_11; // @[util.scala:205:25] assign wrap_11 = _GEN_98; // @[util.scala:205:25] wire [4:0] _T_119 = io_core_dis_stq_idx_2_0 + 5'h1; // @[util.scala:206:28] assign io_core_stq_full_2_0 = (wrap_9 ? 5'h0 : _T_119) == stq_head; // @[util.scala:205:25, :206:{10,28}] wire _dis_ld_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_ldq_0; // @[lsu.scala:201:7, :300:48] wire _dis_ld_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:201:7, :300:88] wire dis_ld_val_2 = _dis_ld_val_T_4 & _dis_ld_val_T_5; // @[lsu.scala:300:{48,85,88}] wire _dis_st_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_stq_0; // @[lsu.scala:201:7, :301:48] wire _dis_st_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:201:7, :300:88, :301:88] wire dis_st_val_2 = _dis_st_val_T_4 & _dis_st_val_T_5; // @[lsu.scala:301:{48,85,88}] wire [31:0] _T_116 = 32'h1 << io_core_dis_stq_idx_2_0; // @[lsu.scala:201:7, :335:72] wire [4:0] _T_121 = wrap_11 ? 5'h0 : _T_119; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _T_122 = dis_st_val_2 ? _T_121 : io_core_dis_stq_idx_2_0; // @[util.scala:206:10] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:285:84, :347:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:201:7, :347:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:201:7, :347:42] wire mem_xcpt_valid; // @[lsu.scala:358:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:359:29] wire [3:0] mem_xcpt_uop_ctrl_br_type; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_load; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_sta; // @[lsu.scala:360:29] wire mem_xcpt_uop_ctrl_is_std; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_uopc; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:360:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:360:29] wire [2:0] mem_xcpt_uop_iq_type; // @[lsu.scala:360:29] wire [9:0] mem_xcpt_uop_fu_code; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_iw_state; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_br; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jalr; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_jal; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:360:29] wire [15:0] mem_xcpt_uop_br_mask; // @[lsu.scala:360:29] wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:360:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:360:29] wire mem_xcpt_uop_taken; // @[lsu.scala:360:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:360:29] wire [11:0] mem_xcpt_uop_csr_addr; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:360:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29] wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:360:29] wire mem_xcpt_uop_exception; // @[lsu.scala:360:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:360:29] wire mem_xcpt_uop_bypassable; // @[lsu.scala:360:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:360:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:360:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:360:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:360:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:360:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:360:29] wire mem_xcpt_uop_ldst_val; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:360:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:360:29] wire mem_xcpt_uop_fp_single; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:360:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:360:29] wire [1:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:360:29] wire [39:0] mem_xcpt_vaddr; // @[lsu.scala:361:29] wire will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_incoming_0; // @[lsu.scala:370:38] wire will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_stad_incoming_0; // @[lsu.scala:371:38] wire will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_incoming_0; // @[lsu.scala:372:38] wire will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_std_incoming_0; // @[lsu.scala:373:38] wire will_fire_sfence_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sfence_0; // @[lsu.scala:374:38] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_incoming_0; // @[lsu.scala:375:38] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:375:38, :642:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_hella_wakeup_0; // @[lsu.scala:376:38] wire will_fire_release_0_will_fire; // @[lsu.scala:535:61] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:201:7, :377:38] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_retry_0; // @[lsu.scala:378:38] wire will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61] wire will_fire_sta_retry_0; // @[lsu.scala:379:38] wire will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61] wire will_fire_store_commit_0; // @[lsu.scala:380:38] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61] wire will_fire_load_wakeup_0; // @[lsu.scala:381:38] wire [6:0] mem_incoming_uop_out_uopc = exe_req_0_bits_uop_uopc; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_inst = exe_req_0_bits_uop_inst; // @[util.scala:96:23] wire [31:0] mem_incoming_uop_out_debug_inst = exe_req_0_bits_uop_debug_inst; // @[util.scala:96:23] wire mem_incoming_uop_out_is_rvc = exe_req_0_bits_uop_is_rvc; // @[util.scala:96:23] wire [39:0] mem_incoming_uop_out_debug_pc = exe_req_0_bits_uop_debug_pc; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_iq_type = exe_req_0_bits_uop_iq_type; // @[util.scala:96:23] wire [9:0] mem_incoming_uop_out_fu_code = exe_req_0_bits_uop_fu_code; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_ctrl_br_type = exe_req_0_bits_uop_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_ctrl_op1_sel = exe_req_0_bits_uop_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_op2_sel = exe_req_0_bits_uop_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_imm_sel = exe_req_0_bits_uop_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_ctrl_op_fcn = exe_req_0_bits_uop_ctrl_op_fcn; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_fcn_dw = exe_req_0_bits_uop_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_incoming_uop_out_ctrl_csr_cmd = exe_req_0_bits_uop_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_load = exe_req_0_bits_uop_ctrl_is_load; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_sta = exe_req_0_bits_uop_ctrl_is_sta; // @[util.scala:96:23] wire mem_incoming_uop_out_ctrl_is_std = exe_req_0_bits_uop_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_iw_state = exe_req_0_bits_uop_iw_state; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p1_poisoned = exe_req_0_bits_uop_iw_p1_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_iw_p2_poisoned = exe_req_0_bits_uop_iw_p2_poisoned; // @[util.scala:96:23] wire mem_incoming_uop_out_is_br = exe_req_0_bits_uop_is_br; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jalr = exe_req_0_bits_uop_is_jalr; // @[util.scala:96:23] wire mem_incoming_uop_out_is_jal = exe_req_0_bits_uop_is_jal; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sfb = exe_req_0_bits_uop_is_sfb; // @[util.scala:96:23] wire [3:0] mem_incoming_uop_out_br_tag = exe_req_0_bits_uop_br_tag; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_ftq_idx = exe_req_0_bits_uop_ftq_idx; // @[util.scala:96:23] wire mem_incoming_uop_out_edge_inst = exe_req_0_bits_uop_edge_inst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_pc_lob = exe_req_0_bits_uop_pc_lob; // @[util.scala:96:23] wire mem_incoming_uop_out_taken = exe_req_0_bits_uop_taken; // @[util.scala:96:23] wire [19:0] mem_incoming_uop_out_imm_packed = exe_req_0_bits_uop_imm_packed; // @[util.scala:96:23] wire [11:0] mem_incoming_uop_out_csr_addr = exe_req_0_bits_uop_csr_addr; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_rob_idx = exe_req_0_bits_uop_rob_idx; // @[util.scala:96:23] wire [4:0] ldq_incoming_idx_0 = exe_req_0_bits_uop_ldq_idx; // @[lsu.scala:263:49, :383:25] wire [4:0] mem_incoming_uop_out_ldq_idx = exe_req_0_bits_uop_ldq_idx; // @[util.scala:96:23] wire [4:0] stq_incoming_idx_0 = exe_req_0_bits_uop_stq_idx; // @[lsu.scala:263:49, :383:25] wire [4:0] mem_incoming_uop_out_stq_idx = exe_req_0_bits_uop_stq_idx; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_rxq_idx = exe_req_0_bits_uop_rxq_idx; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_pdst = exe_req_0_bits_uop_pdst; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_prs1 = exe_req_0_bits_uop_prs1; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_prs2 = exe_req_0_bits_uop_prs2; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_prs3 = exe_req_0_bits_uop_prs3; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_ppred = exe_req_0_bits_uop_ppred; // @[util.scala:96:23] wire mem_incoming_uop_out_prs1_busy = exe_req_0_bits_uop_prs1_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs2_busy = exe_req_0_bits_uop_prs2_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_prs3_busy = exe_req_0_bits_uop_prs3_busy; // @[util.scala:96:23] wire mem_incoming_uop_out_ppred_busy = exe_req_0_bits_uop_ppred_busy; // @[util.scala:96:23] wire [6:0] mem_incoming_uop_out_stale_pdst = exe_req_0_bits_uop_stale_pdst; // @[util.scala:96:23] wire mem_incoming_uop_out_exception = exe_req_0_bits_uop_exception; // @[util.scala:96:23] wire [63:0] mem_incoming_uop_out_exc_cause = exe_req_0_bits_uop_exc_cause; // @[util.scala:96:23] wire mem_incoming_uop_out_bypassable = exe_req_0_bits_uop_bypassable; // @[util.scala:96:23] wire [4:0] mem_incoming_uop_out_mem_cmd = exe_req_0_bits_uop_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_mem_size = exe_req_0_bits_uop_mem_size; // @[util.scala:96:23] wire mem_incoming_uop_out_mem_signed = exe_req_0_bits_uop_mem_signed; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fence = exe_req_0_bits_uop_is_fence; // @[util.scala:96:23] wire mem_incoming_uop_out_is_fencei = exe_req_0_bits_uop_is_fencei; // @[util.scala:96:23] wire mem_incoming_uop_out_is_amo = exe_req_0_bits_uop_is_amo; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_ldq = exe_req_0_bits_uop_uses_ldq; // @[util.scala:96:23] wire mem_incoming_uop_out_uses_stq = exe_req_0_bits_uop_uses_stq; // @[util.scala:96:23] wire mem_incoming_uop_out_is_sys_pc2epc = exe_req_0_bits_uop_is_sys_pc2epc; // @[util.scala:96:23] wire mem_incoming_uop_out_is_unique = exe_req_0_bits_uop_is_unique; // @[util.scala:96:23] wire mem_incoming_uop_out_flush_on_commit = exe_req_0_bits_uop_flush_on_commit; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_is_rs1 = exe_req_0_bits_uop_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_ldst = exe_req_0_bits_uop_ldst; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs1 = exe_req_0_bits_uop_lrs1; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs2 = exe_req_0_bits_uop_lrs2; // @[util.scala:96:23] wire [5:0] mem_incoming_uop_out_lrs3 = exe_req_0_bits_uop_lrs3; // @[util.scala:96:23] wire mem_incoming_uop_out_ldst_val = exe_req_0_bits_uop_ldst_val; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_dst_rtype = exe_req_0_bits_uop_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = exe_req_0_bits_uop_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = exe_req_0_bits_uop_lrs2_rtype; // @[util.scala:96:23] wire mem_incoming_uop_out_frs3_en = exe_req_0_bits_uop_frs3_en; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_val = exe_req_0_bits_uop_fp_val; // @[util.scala:96:23] wire mem_incoming_uop_out_fp_single = exe_req_0_bits_uop_fp_single; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_pf_if = exe_req_0_bits_uop_xcpt_pf_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ae_if = exe_req_0_bits_uop_xcpt_ae_if; // @[util.scala:96:23] wire mem_incoming_uop_out_xcpt_ma_if = exe_req_0_bits_uop_xcpt_ma_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_debug_if = exe_req_0_bits_uop_bp_debug_if; // @[util.scala:96:23] wire mem_incoming_uop_out_bp_xcpt_if = exe_req_0_bits_uop_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_fsrc = exe_req_0_bits_uop_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_incoming_uop_out_debug_tsrc = exe_req_0_bits_uop_debug_tsrc; // @[util.scala:96:23] wire [15:0] exe_req_0_bits_uop_br_mask; // @[lsu.scala:383:25] wire exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25] wire [24:0] exe_req_0_bits_mxcpt_bits; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:383:25] wire [38:0] exe_req_0_bits_sfence_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:383:25] wire exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25] wire [63:0] exe_req_0_bits_data; // @[lsu.scala:383:25] wire [39:0] exe_req_0_bits_addr; // @[lsu.scala:383:25] wire exe_req_0_valid; // @[lsu.scala:383:25] assign exe_req_0_bits_sfence_bits_asid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_asid_0 : _exe_req_WIRE_0_bits_sfence_bits_asid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_addr_0 : _exe_req_WIRE_0_bits_sfence_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs2_0 : _exe_req_WIRE_0_bits_sfence_bits_rs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_bits_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_bits_rs1_0 : _exe_req_WIRE_0_bits_sfence_bits_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_sfence_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_sfence_valid_0 : _exe_req_WIRE_0_bits_sfence_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_bits = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_bits_0 : _exe_req_WIRE_0_bits_mxcpt_bits; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_mxcpt_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_mxcpt_valid_0 : _exe_req_WIRE_0_bits_mxcpt_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_addr_0 : _exe_req_WIRE_0_bits_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_data = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_data_0 : _exe_req_WIRE_0_bits_data; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_tsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_tsrc_0 : _exe_req_WIRE_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_fsrc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_fsrc_0 : _exe_req_WIRE_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_xcpt_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_xcpt_if_0 : _exe_req_WIRE_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bp_debug_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bp_debug_if_0 : _exe_req_WIRE_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ma_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ma_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_ae_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_ae_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_xcpt_pf_if = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_xcpt_pf_if_0 : _exe_req_WIRE_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_single = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_single_0 : _exe_req_WIRE_0_bits_uop_fp_single; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fp_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fp_val_0 : _exe_req_WIRE_0_bits_uop_fp_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_frs3_en = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_frs3_en_0 : _exe_req_WIRE_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_rtype_0 : _exe_req_WIRE_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_dst_rtype = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_dst_rtype_0 : _exe_req_WIRE_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_val = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_val_0 : _exe_req_WIRE_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs3_0 : _exe_req_WIRE_0_bits_uop_lrs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs2_0 : _exe_req_WIRE_0_bits_uop_lrs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_lrs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_lrs1_0 : _exe_req_WIRE_0_bits_uop_lrs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_0 : _exe_req_WIRE_0_bits_uop_ldst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldst_is_rs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldst_is_rs1_0 : _exe_req_WIRE_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_flush_on_commit = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_flush_on_commit_0 : _exe_req_WIRE_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_unique = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_unique_0 : _exe_req_WIRE_0_bits_uop_is_unique; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sys_pc2epc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc_0 : _exe_req_WIRE_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_stq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_stq_0 : _exe_req_WIRE_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uses_ldq = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uses_ldq_0 : _exe_req_WIRE_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_amo = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_amo_0 : _exe_req_WIRE_0_bits_uop_is_amo; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fencei = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fencei_0 : _exe_req_WIRE_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_fence = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_fence_0 : _exe_req_WIRE_0_bits_uop_is_fence; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_signed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_signed_0 : _exe_req_WIRE_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_size = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_size_0 : _exe_req_WIRE_0_bits_uop_mem_size; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_mem_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_mem_cmd_0 : _exe_req_WIRE_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_bypassable = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_bypassable_0 : _exe_req_WIRE_0_bits_uop_bypassable; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exc_cause = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exc_cause_0 : _exe_req_WIRE_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_exception = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_exception_0 : _exe_req_WIRE_0_bits_uop_exception; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stale_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stale_pdst_0 : _exe_req_WIRE_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_busy_0 : _exe_req_WIRE_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_busy_0 : _exe_req_WIRE_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_busy_0 : _exe_req_WIRE_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1_busy = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_busy_0 : _exe_req_WIRE_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ppred = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ppred_0 : _exe_req_WIRE_0_bits_uop_ppred; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs3 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs3_0 : _exe_req_WIRE_0_bits_uop_prs3; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs2 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs2_0 : _exe_req_WIRE_0_bits_uop_prs2; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_prs1 = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_prs1_0 : _exe_req_WIRE_0_bits_uop_prs1; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pdst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pdst_0 : _exe_req_WIRE_0_bits_uop_pdst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rxq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rxq_idx_0 : _exe_req_WIRE_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_stq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_stq_idx_0 : _exe_req_WIRE_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ldq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ldq_idx_0 : _exe_req_WIRE_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_rob_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_rob_idx_0 : _exe_req_WIRE_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_csr_addr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_csr_addr_0 : _exe_req_WIRE_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_imm_packed = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_imm_packed_0 : _exe_req_WIRE_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_taken = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_taken_0 : _exe_req_WIRE_0_bits_uop_taken; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_pc_lob = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_pc_lob_0 : _exe_req_WIRE_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_edge_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_edge_inst_0 : _exe_req_WIRE_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ftq_idx = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ftq_idx_0 : _exe_req_WIRE_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_tag = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_tag_0 : _exe_req_WIRE_0_bits_uop_br_tag; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_br_mask = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_br_mask_0 : _exe_req_WIRE_0_bits_uop_br_mask; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_sfb = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_sfb_0 : _exe_req_WIRE_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jal = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jal_0 : _exe_req_WIRE_0_bits_uop_is_jal; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_jalr = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_jalr_0 : _exe_req_WIRE_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_br = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_br_0 : _exe_req_WIRE_0_bits_uop_is_br; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p2_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p2_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_p1_poisoned = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_p1_poisoned_0 : _exe_req_WIRE_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iw_state = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iw_state_0 : _exe_req_WIRE_0_bits_uop_iw_state; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_std = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_std_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_sta = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_sta_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_is_load = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_is_load_0 : _exe_req_WIRE_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_csr_cmd = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd_0 : _exe_req_WIRE_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_fcn_dw = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw_0 : _exe_req_WIRE_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op_fcn = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn_0 : _exe_req_WIRE_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_imm_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op2_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_op1_sel = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel_0 : _exe_req_WIRE_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_ctrl_br_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_ctrl_br_type_0 : _exe_req_WIRE_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_fu_code = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_fu_code_0 : _exe_req_WIRE_0_bits_uop_fu_code; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_iq_type = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_iq_type_0 : _exe_req_WIRE_0_bits_uop_iq_type; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_pc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_pc_0 : _exe_req_WIRE_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_is_rvc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_is_rvc_0 : _exe_req_WIRE_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_debug_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_debug_inst_0 : _exe_req_WIRE_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_inst = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_inst_0 : _exe_req_WIRE_0_bits_uop_inst; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_bits_uop_uopc = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_bits_uop_uopc_0 : _exe_req_WIRE_0_bits_uop_uopc; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] assign exe_req_0_valid = io_core_exe_0_req_bits_sfence_valid_0 ? io_core_exe_0_req_valid_0 : _exe_req_WIRE_0_valid; // @[lsu.scala:201:7, :383:{25,33}, :386:49, :387:15] wire block_load_mask_0; // @[lsu.scala:396:36] wire block_load_mask_1; // @[lsu.scala:396:36] wire block_load_mask_2; // @[lsu.scala:396:36] wire block_load_mask_3; // @[lsu.scala:396:36] wire block_load_mask_4; // @[lsu.scala:396:36] wire block_load_mask_5; // @[lsu.scala:396:36] wire block_load_mask_6; // @[lsu.scala:396:36] wire block_load_mask_7; // @[lsu.scala:396:36] wire block_load_mask_8; // @[lsu.scala:396:36] wire block_load_mask_9; // @[lsu.scala:396:36] wire block_load_mask_10; // @[lsu.scala:396:36] wire block_load_mask_11; // @[lsu.scala:396:36] wire block_load_mask_12; // @[lsu.scala:396:36] wire block_load_mask_13; // @[lsu.scala:396:36] wire block_load_mask_14; // @[lsu.scala:396:36] wire block_load_mask_15; // @[lsu.scala:396:36] wire block_load_mask_16; // @[lsu.scala:396:36] wire block_load_mask_17; // @[lsu.scala:396:36] wire block_load_mask_18; // @[lsu.scala:396:36] wire block_load_mask_19; // @[lsu.scala:396:36] wire block_load_mask_20; // @[lsu.scala:396:36] wire block_load_mask_21; // @[lsu.scala:396:36] wire block_load_mask_22; // @[lsu.scala:396:36] wire block_load_mask_23; // @[lsu.scala:396:36] reg p1_block_load_mask_0; // @[lsu.scala:397:35] reg p1_block_load_mask_1; // @[lsu.scala:397:35] reg p1_block_load_mask_2; // @[lsu.scala:397:35] reg p1_block_load_mask_3; // @[lsu.scala:397:35] reg p1_block_load_mask_4; // @[lsu.scala:397:35] reg p1_block_load_mask_5; // @[lsu.scala:397:35] reg p1_block_load_mask_6; // @[lsu.scala:397:35] reg p1_block_load_mask_7; // @[lsu.scala:397:35] reg p1_block_load_mask_8; // @[lsu.scala:397:35] reg p1_block_load_mask_9; // @[lsu.scala:397:35] reg p1_block_load_mask_10; // @[lsu.scala:397:35] reg p1_block_load_mask_11; // @[lsu.scala:397:35] reg p1_block_load_mask_12; // @[lsu.scala:397:35] reg p1_block_load_mask_13; // @[lsu.scala:397:35] reg p1_block_load_mask_14; // @[lsu.scala:397:35] reg p1_block_load_mask_15; // @[lsu.scala:397:35] reg p1_block_load_mask_16; // @[lsu.scala:397:35] reg p1_block_load_mask_17; // @[lsu.scala:397:35] reg p1_block_load_mask_18; // @[lsu.scala:397:35] reg p1_block_load_mask_19; // @[lsu.scala:397:35] reg p1_block_load_mask_20; // @[lsu.scala:397:35] reg p1_block_load_mask_21; // @[lsu.scala:397:35] reg p1_block_load_mask_22; // @[lsu.scala:397:35] reg p1_block_load_mask_23; // @[lsu.scala:397:35] reg p2_block_load_mask_0; // @[lsu.scala:398:35] reg p2_block_load_mask_1; // @[lsu.scala:398:35] reg p2_block_load_mask_2; // @[lsu.scala:398:35] reg p2_block_load_mask_3; // @[lsu.scala:398:35] reg p2_block_load_mask_4; // @[lsu.scala:398:35] reg p2_block_load_mask_5; // @[lsu.scala:398:35] reg p2_block_load_mask_6; // @[lsu.scala:398:35] reg p2_block_load_mask_7; // @[lsu.scala:398:35] reg p2_block_load_mask_8; // @[lsu.scala:398:35] reg p2_block_load_mask_9; // @[lsu.scala:398:35] reg p2_block_load_mask_10; // @[lsu.scala:398:35] reg p2_block_load_mask_11; // @[lsu.scala:398:35] reg p2_block_load_mask_12; // @[lsu.scala:398:35] reg p2_block_load_mask_13; // @[lsu.scala:398:35] reg p2_block_load_mask_14; // @[lsu.scala:398:35] reg p2_block_load_mask_15; // @[lsu.scala:398:35] reg p2_block_load_mask_16; // @[lsu.scala:398:35] reg p2_block_load_mask_17; // @[lsu.scala:398:35] reg p2_block_load_mask_18; // @[lsu.scala:398:35] reg p2_block_load_mask_19; // @[lsu.scala:398:35] reg p2_block_load_mask_20; // @[lsu.scala:398:35] reg p2_block_load_mask_21; // @[lsu.scala:398:35] reg p2_block_load_mask_22; // @[lsu.scala:398:35] reg p2_block_load_mask_23; // @[lsu.scala:398:35] wire _GEN_99 = _T_122 == 5'h17; // @[util.scala:205:25] wire stq_almost_full_wrap; // @[util.scala:205:25] assign stq_almost_full_wrap = _GEN_99; // @[util.scala:205:25] wire stq_almost_full_wrap_2; // @[util.scala:205:25] assign stq_almost_full_wrap_2 = _GEN_99; // @[util.scala:205:25] wire [5:0] _GEN_100 = {1'h0, _T_122} + 6'h1; // @[util.scala:206:28] wire [5:0] _stq_almost_full_T; // @[util.scala:206:28] assign _stq_almost_full_T = _GEN_100; // @[util.scala:206:28] wire [5:0] _stq_almost_full_T_7; // @[util.scala:206:28] assign _stq_almost_full_T_7 = _GEN_100; // @[util.scala:206:28] wire [4:0] _stq_almost_full_T_1 = _stq_almost_full_T[4:0]; // @[util.scala:206:28] wire [4:0] _stq_almost_full_T_2 = stq_almost_full_wrap ? 5'h0 : _stq_almost_full_T_1; // @[util.scala:205:25, :206:{10,28}] wire stq_almost_full_wrap_1 = _stq_almost_full_T_2 == 5'h17; // @[util.scala:205:25, :206:10] wire [5:0] _stq_almost_full_T_3 = {1'h0, _stq_almost_full_T_2} + 6'h1; // @[util.scala:206:{10,28}] wire [4:0] _stq_almost_full_T_4 = _stq_almost_full_T_3[4:0]; // @[util.scala:206:28] wire [4:0] _stq_almost_full_T_5 = stq_almost_full_wrap_1 ? 5'h0 : _stq_almost_full_T_4; // @[util.scala:205:25, :206:{10,28}] wire _stq_almost_full_T_6 = _stq_almost_full_T_5 == stq_head; // @[util.scala:206:10] wire [4:0] _stq_almost_full_T_8 = _stq_almost_full_T_7[4:0]; // @[util.scala:206:28] wire [4:0] _stq_almost_full_T_9 = stq_almost_full_wrap_2 ? 5'h0 : _stq_almost_full_T_8; // @[util.scala:205:25, :206:{10,28}] wire _stq_almost_full_T_10 = _stq_almost_full_T_9 == stq_head; // @[util.scala:206:10] wire _stq_almost_full_T_11 = _stq_almost_full_T_6 | _stq_almost_full_T_10; // @[lsu.scala:401:{92,105}, :402:68] reg stq_almost_full; // @[lsu.scala:401:32] wire store_needs_order; // @[lsu.scala:406:35] wire [6:0] mem_ldq_incoming_e_out_bits_uop_uopc = ldq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iq_type = ldq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_ldq_incoming_e_out_bits_uop_fu_code = ldq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_ctrl_br_type = ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel = ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel = ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel = ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn = ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw = ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd = ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_load = ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta = ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ctrl_is_std = ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_iw_state = ldq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned = ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned = ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_br = ldq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jalr = ldq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_jal = ldq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_ldq_incoming_e_out_bits_uop_csr_addr = ldq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bypassable = ldq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_val = ldq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_fp_single = ldq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:106:23] wire [23:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_youngest_stq_idx = ldq_incoming_e_0_bits_youngest_stq_idx; // @[util.scala:106:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:106:23] wire [4:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [15:0] ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire ldq_incoming_e_0_valid; // @[lsu.scala:263:49] assign ldq_incoming_e_0_valid = _GEN_94[ldq_incoming_idx_0]; // @[lsu.scala:263:49, :304:44] wire [31:0][6:0] _GEN_101 = {{ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_0_bits_uop_uopc}, {ldq_23_bits_uop_uopc}, {ldq_22_bits_uop_uopc}, {ldq_21_bits_uop_uopc}, {ldq_20_bits_uop_uopc}, {ldq_19_bits_uop_uopc}, {ldq_18_bits_uop_uopc}, {ldq_17_bits_uop_uopc}, {ldq_16_bits_uop_uopc}, {ldq_15_bits_uop_uopc}, {ldq_14_bits_uop_uopc}, {ldq_13_bits_uop_uopc}, {ldq_12_bits_uop_uopc}, {ldq_11_bits_uop_uopc}, {ldq_10_bits_uop_uopc}, {ldq_9_bits_uop_uopc}, {ldq_8_bits_uop_uopc}, {ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uopc = _GEN_101[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][31:0] _GEN_102 = {{ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_0_bits_uop_inst}, {ldq_23_bits_uop_inst}, {ldq_22_bits_uop_inst}, {ldq_21_bits_uop_inst}, {ldq_20_bits_uop_inst}, {ldq_19_bits_uop_inst}, {ldq_18_bits_uop_inst}, {ldq_17_bits_uop_inst}, {ldq_16_bits_uop_inst}, {ldq_15_bits_uop_inst}, {ldq_14_bits_uop_inst}, {ldq_13_bits_uop_inst}, {ldq_12_bits_uop_inst}, {ldq_11_bits_uop_inst}, {ldq_10_bits_uop_inst}, {ldq_9_bits_uop_inst}, {ldq_8_bits_uop_inst}, {ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_inst = _GEN_102[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][31:0] _GEN_103 = {{ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}, {ldq_23_bits_uop_debug_inst}, {ldq_22_bits_uop_debug_inst}, {ldq_21_bits_uop_debug_inst}, {ldq_20_bits_uop_debug_inst}, {ldq_19_bits_uop_debug_inst}, {ldq_18_bits_uop_debug_inst}, {ldq_17_bits_uop_debug_inst}, {ldq_16_bits_uop_debug_inst}, {ldq_15_bits_uop_debug_inst}, {ldq_14_bits_uop_debug_inst}, {ldq_13_bits_uop_debug_inst}, {ldq_12_bits_uop_debug_inst}, {ldq_11_bits_uop_debug_inst}, {ldq_10_bits_uop_debug_inst}, {ldq_9_bits_uop_debug_inst}, {ldq_8_bits_uop_debug_inst}, {ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_inst = _GEN_103[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_104 = {{ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}, {ldq_23_bits_uop_is_rvc}, {ldq_22_bits_uop_is_rvc}, {ldq_21_bits_uop_is_rvc}, {ldq_20_bits_uop_is_rvc}, {ldq_19_bits_uop_is_rvc}, {ldq_18_bits_uop_is_rvc}, {ldq_17_bits_uop_is_rvc}, {ldq_16_bits_uop_is_rvc}, {ldq_15_bits_uop_is_rvc}, {ldq_14_bits_uop_is_rvc}, {ldq_13_bits_uop_is_rvc}, {ldq_12_bits_uop_is_rvc}, {ldq_11_bits_uop_is_rvc}, {ldq_10_bits_uop_is_rvc}, {ldq_9_bits_uop_is_rvc}, {ldq_8_bits_uop_is_rvc}, {ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_rvc = _GEN_104[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][39:0] _GEN_105 = {{ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}, {ldq_23_bits_uop_debug_pc}, {ldq_22_bits_uop_debug_pc}, {ldq_21_bits_uop_debug_pc}, {ldq_20_bits_uop_debug_pc}, {ldq_19_bits_uop_debug_pc}, {ldq_18_bits_uop_debug_pc}, {ldq_17_bits_uop_debug_pc}, {ldq_16_bits_uop_debug_pc}, {ldq_15_bits_uop_debug_pc}, {ldq_14_bits_uop_debug_pc}, {ldq_13_bits_uop_debug_pc}, {ldq_12_bits_uop_debug_pc}, {ldq_11_bits_uop_debug_pc}, {ldq_10_bits_uop_debug_pc}, {ldq_9_bits_uop_debug_pc}, {ldq_8_bits_uop_debug_pc}, {ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_pc = _GEN_105[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][2:0] _GEN_106 = {{ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}, {ldq_23_bits_uop_iq_type}, {ldq_22_bits_uop_iq_type}, {ldq_21_bits_uop_iq_type}, {ldq_20_bits_uop_iq_type}, {ldq_19_bits_uop_iq_type}, {ldq_18_bits_uop_iq_type}, {ldq_17_bits_uop_iq_type}, {ldq_16_bits_uop_iq_type}, {ldq_15_bits_uop_iq_type}, {ldq_14_bits_uop_iq_type}, {ldq_13_bits_uop_iq_type}, {ldq_12_bits_uop_iq_type}, {ldq_11_bits_uop_iq_type}, {ldq_10_bits_uop_iq_type}, {ldq_9_bits_uop_iq_type}, {ldq_8_bits_uop_iq_type}, {ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iq_type = _GEN_106[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][9:0] _GEN_107 = {{ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}, {ldq_23_bits_uop_fu_code}, {ldq_22_bits_uop_fu_code}, {ldq_21_bits_uop_fu_code}, {ldq_20_bits_uop_fu_code}, {ldq_19_bits_uop_fu_code}, {ldq_18_bits_uop_fu_code}, {ldq_17_bits_uop_fu_code}, {ldq_16_bits_uop_fu_code}, {ldq_15_bits_uop_fu_code}, {ldq_14_bits_uop_fu_code}, {ldq_13_bits_uop_fu_code}, {ldq_12_bits_uop_fu_code}, {ldq_11_bits_uop_fu_code}, {ldq_10_bits_uop_fu_code}, {ldq_9_bits_uop_fu_code}, {ldq_8_bits_uop_fu_code}, {ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fu_code = _GEN_107[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][3:0] _GEN_108 = {{ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}, {ldq_23_bits_uop_ctrl_br_type}, {ldq_22_bits_uop_ctrl_br_type}, {ldq_21_bits_uop_ctrl_br_type}, {ldq_20_bits_uop_ctrl_br_type}, {ldq_19_bits_uop_ctrl_br_type}, {ldq_18_bits_uop_ctrl_br_type}, {ldq_17_bits_uop_ctrl_br_type}, {ldq_16_bits_uop_ctrl_br_type}, {ldq_15_bits_uop_ctrl_br_type}, {ldq_14_bits_uop_ctrl_br_type}, {ldq_13_bits_uop_ctrl_br_type}, {ldq_12_bits_uop_ctrl_br_type}, {ldq_11_bits_uop_ctrl_br_type}, {ldq_10_bits_uop_ctrl_br_type}, {ldq_9_bits_uop_ctrl_br_type}, {ldq_8_bits_uop_ctrl_br_type}, {ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_108[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_109 = {{ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}, {ldq_23_bits_uop_ctrl_op1_sel}, {ldq_22_bits_uop_ctrl_op1_sel}, {ldq_21_bits_uop_ctrl_op1_sel}, {ldq_20_bits_uop_ctrl_op1_sel}, {ldq_19_bits_uop_ctrl_op1_sel}, {ldq_18_bits_uop_ctrl_op1_sel}, {ldq_17_bits_uop_ctrl_op1_sel}, {ldq_16_bits_uop_ctrl_op1_sel}, {ldq_15_bits_uop_ctrl_op1_sel}, {ldq_14_bits_uop_ctrl_op1_sel}, {ldq_13_bits_uop_ctrl_op1_sel}, {ldq_12_bits_uop_ctrl_op1_sel}, {ldq_11_bits_uop_ctrl_op1_sel}, {ldq_10_bits_uop_ctrl_op1_sel}, {ldq_9_bits_uop_ctrl_op1_sel}, {ldq_8_bits_uop_ctrl_op1_sel}, {ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_109[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][2:0] _GEN_110 = {{ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}, {ldq_23_bits_uop_ctrl_op2_sel}, {ldq_22_bits_uop_ctrl_op2_sel}, {ldq_21_bits_uop_ctrl_op2_sel}, {ldq_20_bits_uop_ctrl_op2_sel}, {ldq_19_bits_uop_ctrl_op2_sel}, {ldq_18_bits_uop_ctrl_op2_sel}, {ldq_17_bits_uop_ctrl_op2_sel}, {ldq_16_bits_uop_ctrl_op2_sel}, {ldq_15_bits_uop_ctrl_op2_sel}, {ldq_14_bits_uop_ctrl_op2_sel}, {ldq_13_bits_uop_ctrl_op2_sel}, {ldq_12_bits_uop_ctrl_op2_sel}, {ldq_11_bits_uop_ctrl_op2_sel}, {ldq_10_bits_uop_ctrl_op2_sel}, {ldq_9_bits_uop_ctrl_op2_sel}, {ldq_8_bits_uop_ctrl_op2_sel}, {ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_110[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][2:0] _GEN_111 = {{ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}, {ldq_23_bits_uop_ctrl_imm_sel}, {ldq_22_bits_uop_ctrl_imm_sel}, {ldq_21_bits_uop_ctrl_imm_sel}, {ldq_20_bits_uop_ctrl_imm_sel}, {ldq_19_bits_uop_ctrl_imm_sel}, {ldq_18_bits_uop_ctrl_imm_sel}, {ldq_17_bits_uop_ctrl_imm_sel}, {ldq_16_bits_uop_ctrl_imm_sel}, {ldq_15_bits_uop_ctrl_imm_sel}, {ldq_14_bits_uop_ctrl_imm_sel}, {ldq_13_bits_uop_ctrl_imm_sel}, {ldq_12_bits_uop_ctrl_imm_sel}, {ldq_11_bits_uop_ctrl_imm_sel}, {ldq_10_bits_uop_ctrl_imm_sel}, {ldq_9_bits_uop_ctrl_imm_sel}, {ldq_8_bits_uop_ctrl_imm_sel}, {ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_111[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_112 = {{ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}, {ldq_23_bits_uop_ctrl_op_fcn}, {ldq_22_bits_uop_ctrl_op_fcn}, {ldq_21_bits_uop_ctrl_op_fcn}, {ldq_20_bits_uop_ctrl_op_fcn}, {ldq_19_bits_uop_ctrl_op_fcn}, {ldq_18_bits_uop_ctrl_op_fcn}, {ldq_17_bits_uop_ctrl_op_fcn}, {ldq_16_bits_uop_ctrl_op_fcn}, {ldq_15_bits_uop_ctrl_op_fcn}, {ldq_14_bits_uop_ctrl_op_fcn}, {ldq_13_bits_uop_ctrl_op_fcn}, {ldq_12_bits_uop_ctrl_op_fcn}, {ldq_11_bits_uop_ctrl_op_fcn}, {ldq_10_bits_uop_ctrl_op_fcn}, {ldq_9_bits_uop_ctrl_op_fcn}, {ldq_8_bits_uop_ctrl_op_fcn}, {ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_112[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_113 = {{ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}, {ldq_23_bits_uop_ctrl_fcn_dw}, {ldq_22_bits_uop_ctrl_fcn_dw}, {ldq_21_bits_uop_ctrl_fcn_dw}, {ldq_20_bits_uop_ctrl_fcn_dw}, {ldq_19_bits_uop_ctrl_fcn_dw}, {ldq_18_bits_uop_ctrl_fcn_dw}, {ldq_17_bits_uop_ctrl_fcn_dw}, {ldq_16_bits_uop_ctrl_fcn_dw}, {ldq_15_bits_uop_ctrl_fcn_dw}, {ldq_14_bits_uop_ctrl_fcn_dw}, {ldq_13_bits_uop_ctrl_fcn_dw}, {ldq_12_bits_uop_ctrl_fcn_dw}, {ldq_11_bits_uop_ctrl_fcn_dw}, {ldq_10_bits_uop_ctrl_fcn_dw}, {ldq_9_bits_uop_ctrl_fcn_dw}, {ldq_8_bits_uop_ctrl_fcn_dw}, {ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_113[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][2:0] _GEN_114 = {{ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}, {ldq_23_bits_uop_ctrl_csr_cmd}, {ldq_22_bits_uop_ctrl_csr_cmd}, {ldq_21_bits_uop_ctrl_csr_cmd}, {ldq_20_bits_uop_ctrl_csr_cmd}, {ldq_19_bits_uop_ctrl_csr_cmd}, {ldq_18_bits_uop_ctrl_csr_cmd}, {ldq_17_bits_uop_ctrl_csr_cmd}, {ldq_16_bits_uop_ctrl_csr_cmd}, {ldq_15_bits_uop_ctrl_csr_cmd}, {ldq_14_bits_uop_ctrl_csr_cmd}, {ldq_13_bits_uop_ctrl_csr_cmd}, {ldq_12_bits_uop_ctrl_csr_cmd}, {ldq_11_bits_uop_ctrl_csr_cmd}, {ldq_10_bits_uop_ctrl_csr_cmd}, {ldq_9_bits_uop_ctrl_csr_cmd}, {ldq_8_bits_uop_ctrl_csr_cmd}, {ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_114[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_115 = {{ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}, {ldq_23_bits_uop_ctrl_is_load}, {ldq_22_bits_uop_ctrl_is_load}, {ldq_21_bits_uop_ctrl_is_load}, {ldq_20_bits_uop_ctrl_is_load}, {ldq_19_bits_uop_ctrl_is_load}, {ldq_18_bits_uop_ctrl_is_load}, {ldq_17_bits_uop_ctrl_is_load}, {ldq_16_bits_uop_ctrl_is_load}, {ldq_15_bits_uop_ctrl_is_load}, {ldq_14_bits_uop_ctrl_is_load}, {ldq_13_bits_uop_ctrl_is_load}, {ldq_12_bits_uop_ctrl_is_load}, {ldq_11_bits_uop_ctrl_is_load}, {ldq_10_bits_uop_ctrl_is_load}, {ldq_9_bits_uop_ctrl_is_load}, {ldq_8_bits_uop_ctrl_is_load}, {ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_115[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_116 = {{ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}, {ldq_23_bits_uop_ctrl_is_sta}, {ldq_22_bits_uop_ctrl_is_sta}, {ldq_21_bits_uop_ctrl_is_sta}, {ldq_20_bits_uop_ctrl_is_sta}, {ldq_19_bits_uop_ctrl_is_sta}, {ldq_18_bits_uop_ctrl_is_sta}, {ldq_17_bits_uop_ctrl_is_sta}, {ldq_16_bits_uop_ctrl_is_sta}, {ldq_15_bits_uop_ctrl_is_sta}, {ldq_14_bits_uop_ctrl_is_sta}, {ldq_13_bits_uop_ctrl_is_sta}, {ldq_12_bits_uop_ctrl_is_sta}, {ldq_11_bits_uop_ctrl_is_sta}, {ldq_10_bits_uop_ctrl_is_sta}, {ldq_9_bits_uop_ctrl_is_sta}, {ldq_8_bits_uop_ctrl_is_sta}, {ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_116[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_117 = {{ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}, {ldq_23_bits_uop_ctrl_is_std}, {ldq_22_bits_uop_ctrl_is_std}, {ldq_21_bits_uop_ctrl_is_std}, {ldq_20_bits_uop_ctrl_is_std}, {ldq_19_bits_uop_ctrl_is_std}, {ldq_18_bits_uop_ctrl_is_std}, {ldq_17_bits_uop_ctrl_is_std}, {ldq_16_bits_uop_ctrl_is_std}, {ldq_15_bits_uop_ctrl_is_std}, {ldq_14_bits_uop_ctrl_is_std}, {ldq_13_bits_uop_ctrl_is_std}, {ldq_12_bits_uop_ctrl_is_std}, {ldq_11_bits_uop_ctrl_is_std}, {ldq_10_bits_uop_ctrl_is_std}, {ldq_9_bits_uop_ctrl_is_std}, {ldq_8_bits_uop_ctrl_is_std}, {ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_117[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_118 = {{ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}, {ldq_23_bits_uop_iw_state}, {ldq_22_bits_uop_iw_state}, {ldq_21_bits_uop_iw_state}, {ldq_20_bits_uop_iw_state}, {ldq_19_bits_uop_iw_state}, {ldq_18_bits_uop_iw_state}, {ldq_17_bits_uop_iw_state}, {ldq_16_bits_uop_iw_state}, {ldq_15_bits_uop_iw_state}, {ldq_14_bits_uop_iw_state}, {ldq_13_bits_uop_iw_state}, {ldq_12_bits_uop_iw_state}, {ldq_11_bits_uop_iw_state}, {ldq_10_bits_uop_iw_state}, {ldq_9_bits_uop_iw_state}, {ldq_8_bits_uop_iw_state}, {ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_state = _GEN_118[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_119 = {{ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}, {ldq_23_bits_uop_iw_p1_poisoned}, {ldq_22_bits_uop_iw_p1_poisoned}, {ldq_21_bits_uop_iw_p1_poisoned}, {ldq_20_bits_uop_iw_p1_poisoned}, {ldq_19_bits_uop_iw_p1_poisoned}, {ldq_18_bits_uop_iw_p1_poisoned}, {ldq_17_bits_uop_iw_p1_poisoned}, {ldq_16_bits_uop_iw_p1_poisoned}, {ldq_15_bits_uop_iw_p1_poisoned}, {ldq_14_bits_uop_iw_p1_poisoned}, {ldq_13_bits_uop_iw_p1_poisoned}, {ldq_12_bits_uop_iw_p1_poisoned}, {ldq_11_bits_uop_iw_p1_poisoned}, {ldq_10_bits_uop_iw_p1_poisoned}, {ldq_9_bits_uop_iw_p1_poisoned}, {ldq_8_bits_uop_iw_p1_poisoned}, {ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_119[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_120 = {{ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}, {ldq_23_bits_uop_iw_p2_poisoned}, {ldq_22_bits_uop_iw_p2_poisoned}, {ldq_21_bits_uop_iw_p2_poisoned}, {ldq_20_bits_uop_iw_p2_poisoned}, {ldq_19_bits_uop_iw_p2_poisoned}, {ldq_18_bits_uop_iw_p2_poisoned}, {ldq_17_bits_uop_iw_p2_poisoned}, {ldq_16_bits_uop_iw_p2_poisoned}, {ldq_15_bits_uop_iw_p2_poisoned}, {ldq_14_bits_uop_iw_p2_poisoned}, {ldq_13_bits_uop_iw_p2_poisoned}, {ldq_12_bits_uop_iw_p2_poisoned}, {ldq_11_bits_uop_iw_p2_poisoned}, {ldq_10_bits_uop_iw_p2_poisoned}, {ldq_9_bits_uop_iw_p2_poisoned}, {ldq_8_bits_uop_iw_p2_poisoned}, {ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_120[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_121 = {{ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_0_bits_uop_is_br}, {ldq_23_bits_uop_is_br}, {ldq_22_bits_uop_is_br}, {ldq_21_bits_uop_is_br}, {ldq_20_bits_uop_is_br}, {ldq_19_bits_uop_is_br}, {ldq_18_bits_uop_is_br}, {ldq_17_bits_uop_is_br}, {ldq_16_bits_uop_is_br}, {ldq_15_bits_uop_is_br}, {ldq_14_bits_uop_is_br}, {ldq_13_bits_uop_is_br}, {ldq_12_bits_uop_is_br}, {ldq_11_bits_uop_is_br}, {ldq_10_bits_uop_is_br}, {ldq_9_bits_uop_is_br}, {ldq_8_bits_uop_is_br}, {ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_br = _GEN_121[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_122 = {{ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}, {ldq_23_bits_uop_is_jalr}, {ldq_22_bits_uop_is_jalr}, {ldq_21_bits_uop_is_jalr}, {ldq_20_bits_uop_is_jalr}, {ldq_19_bits_uop_is_jalr}, {ldq_18_bits_uop_is_jalr}, {ldq_17_bits_uop_is_jalr}, {ldq_16_bits_uop_is_jalr}, {ldq_15_bits_uop_is_jalr}, {ldq_14_bits_uop_is_jalr}, {ldq_13_bits_uop_is_jalr}, {ldq_12_bits_uop_is_jalr}, {ldq_11_bits_uop_is_jalr}, {ldq_10_bits_uop_is_jalr}, {ldq_9_bits_uop_is_jalr}, {ldq_8_bits_uop_is_jalr}, {ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jalr = _GEN_122[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_123 = {{ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}, {ldq_23_bits_uop_is_jal}, {ldq_22_bits_uop_is_jal}, {ldq_21_bits_uop_is_jal}, {ldq_20_bits_uop_is_jal}, {ldq_19_bits_uop_is_jal}, {ldq_18_bits_uop_is_jal}, {ldq_17_bits_uop_is_jal}, {ldq_16_bits_uop_is_jal}, {ldq_15_bits_uop_is_jal}, {ldq_14_bits_uop_is_jal}, {ldq_13_bits_uop_is_jal}, {ldq_12_bits_uop_is_jal}, {ldq_11_bits_uop_is_jal}, {ldq_10_bits_uop_is_jal}, {ldq_9_bits_uop_is_jal}, {ldq_8_bits_uop_is_jal}, {ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_jal = _GEN_123[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_124 = {{ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}, {ldq_23_bits_uop_is_sfb}, {ldq_22_bits_uop_is_sfb}, {ldq_21_bits_uop_is_sfb}, {ldq_20_bits_uop_is_sfb}, {ldq_19_bits_uop_is_sfb}, {ldq_18_bits_uop_is_sfb}, {ldq_17_bits_uop_is_sfb}, {ldq_16_bits_uop_is_sfb}, {ldq_15_bits_uop_is_sfb}, {ldq_14_bits_uop_is_sfb}, {ldq_13_bits_uop_is_sfb}, {ldq_12_bits_uop_is_sfb}, {ldq_11_bits_uop_is_sfb}, {ldq_10_bits_uop_is_sfb}, {ldq_9_bits_uop_is_sfb}, {ldq_8_bits_uop_is_sfb}, {ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sfb = _GEN_124[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][15:0] _GEN_125 = {{ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}, {ldq_23_bits_uop_br_mask}, {ldq_22_bits_uop_br_mask}, {ldq_21_bits_uop_br_mask}, {ldq_20_bits_uop_br_mask}, {ldq_19_bits_uop_br_mask}, {ldq_18_bits_uop_br_mask}, {ldq_17_bits_uop_br_mask}, {ldq_16_bits_uop_br_mask}, {ldq_15_bits_uop_br_mask}, {ldq_14_bits_uop_br_mask}, {ldq_13_bits_uop_br_mask}, {ldq_12_bits_uop_br_mask}, {ldq_11_bits_uop_br_mask}, {ldq_10_bits_uop_br_mask}, {ldq_9_bits_uop_br_mask}, {ldq_8_bits_uop_br_mask}, {ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_mask = _GEN_125[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][3:0] _GEN_126 = {{ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}, {ldq_23_bits_uop_br_tag}, {ldq_22_bits_uop_br_tag}, {ldq_21_bits_uop_br_tag}, {ldq_20_bits_uop_br_tag}, {ldq_19_bits_uop_br_tag}, {ldq_18_bits_uop_br_tag}, {ldq_17_bits_uop_br_tag}, {ldq_16_bits_uop_br_tag}, {ldq_15_bits_uop_br_tag}, {ldq_14_bits_uop_br_tag}, {ldq_13_bits_uop_br_tag}, {ldq_12_bits_uop_br_tag}, {ldq_11_bits_uop_br_tag}, {ldq_10_bits_uop_br_tag}, {ldq_9_bits_uop_br_tag}, {ldq_8_bits_uop_br_tag}, {ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_br_tag = _GEN_126[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_127 = {{ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}, {ldq_23_bits_uop_ftq_idx}, {ldq_22_bits_uop_ftq_idx}, {ldq_21_bits_uop_ftq_idx}, {ldq_20_bits_uop_ftq_idx}, {ldq_19_bits_uop_ftq_idx}, {ldq_18_bits_uop_ftq_idx}, {ldq_17_bits_uop_ftq_idx}, {ldq_16_bits_uop_ftq_idx}, {ldq_15_bits_uop_ftq_idx}, {ldq_14_bits_uop_ftq_idx}, {ldq_13_bits_uop_ftq_idx}, {ldq_12_bits_uop_ftq_idx}, {ldq_11_bits_uop_ftq_idx}, {ldq_10_bits_uop_ftq_idx}, {ldq_9_bits_uop_ftq_idx}, {ldq_8_bits_uop_ftq_idx}, {ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ftq_idx = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_128 = {{ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}, {ldq_23_bits_uop_edge_inst}, {ldq_22_bits_uop_edge_inst}, {ldq_21_bits_uop_edge_inst}, {ldq_20_bits_uop_edge_inst}, {ldq_19_bits_uop_edge_inst}, {ldq_18_bits_uop_edge_inst}, {ldq_17_bits_uop_edge_inst}, {ldq_16_bits_uop_edge_inst}, {ldq_15_bits_uop_edge_inst}, {ldq_14_bits_uop_edge_inst}, {ldq_13_bits_uop_edge_inst}, {ldq_12_bits_uop_edge_inst}, {ldq_11_bits_uop_edge_inst}, {ldq_10_bits_uop_edge_inst}, {ldq_9_bits_uop_edge_inst}, {ldq_8_bits_uop_edge_inst}, {ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_edge_inst = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][5:0] _GEN_129 = {{ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}, {ldq_23_bits_uop_pc_lob}, {ldq_22_bits_uop_pc_lob}, {ldq_21_bits_uop_pc_lob}, {ldq_20_bits_uop_pc_lob}, {ldq_19_bits_uop_pc_lob}, {ldq_18_bits_uop_pc_lob}, {ldq_17_bits_uop_pc_lob}, {ldq_16_bits_uop_pc_lob}, {ldq_15_bits_uop_pc_lob}, {ldq_14_bits_uop_pc_lob}, {ldq_13_bits_uop_pc_lob}, {ldq_12_bits_uop_pc_lob}, {ldq_11_bits_uop_pc_lob}, {ldq_10_bits_uop_pc_lob}, {ldq_9_bits_uop_pc_lob}, {ldq_8_bits_uop_pc_lob}, {ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pc_lob = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_130 = {{ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_0_bits_uop_taken}, {ldq_23_bits_uop_taken}, {ldq_22_bits_uop_taken}, {ldq_21_bits_uop_taken}, {ldq_20_bits_uop_taken}, {ldq_19_bits_uop_taken}, {ldq_18_bits_uop_taken}, {ldq_17_bits_uop_taken}, {ldq_16_bits_uop_taken}, {ldq_15_bits_uop_taken}, {ldq_14_bits_uop_taken}, {ldq_13_bits_uop_taken}, {ldq_12_bits_uop_taken}, {ldq_11_bits_uop_taken}, {ldq_10_bits_uop_taken}, {ldq_9_bits_uop_taken}, {ldq_8_bits_uop_taken}, {ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_taken = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][19:0] _GEN_131 = {{ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}, {ldq_23_bits_uop_imm_packed}, {ldq_22_bits_uop_imm_packed}, {ldq_21_bits_uop_imm_packed}, {ldq_20_bits_uop_imm_packed}, {ldq_19_bits_uop_imm_packed}, {ldq_18_bits_uop_imm_packed}, {ldq_17_bits_uop_imm_packed}, {ldq_16_bits_uop_imm_packed}, {ldq_15_bits_uop_imm_packed}, {ldq_14_bits_uop_imm_packed}, {ldq_13_bits_uop_imm_packed}, {ldq_12_bits_uop_imm_packed}, {ldq_11_bits_uop_imm_packed}, {ldq_10_bits_uop_imm_packed}, {ldq_9_bits_uop_imm_packed}, {ldq_8_bits_uop_imm_packed}, {ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_imm_packed = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][11:0] _GEN_132 = {{ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}, {ldq_23_bits_uop_csr_addr}, {ldq_22_bits_uop_csr_addr}, {ldq_21_bits_uop_csr_addr}, {ldq_20_bits_uop_csr_addr}, {ldq_19_bits_uop_csr_addr}, {ldq_18_bits_uop_csr_addr}, {ldq_17_bits_uop_csr_addr}, {ldq_16_bits_uop_csr_addr}, {ldq_15_bits_uop_csr_addr}, {ldq_14_bits_uop_csr_addr}, {ldq_13_bits_uop_csr_addr}, {ldq_12_bits_uop_csr_addr}, {ldq_11_bits_uop_csr_addr}, {ldq_10_bits_uop_csr_addr}, {ldq_9_bits_uop_csr_addr}, {ldq_8_bits_uop_csr_addr}, {ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_csr_addr = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_133 = {{ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}, {ldq_23_bits_uop_rob_idx}, {ldq_22_bits_uop_rob_idx}, {ldq_21_bits_uop_rob_idx}, {ldq_20_bits_uop_rob_idx}, {ldq_19_bits_uop_rob_idx}, {ldq_18_bits_uop_rob_idx}, {ldq_17_bits_uop_rob_idx}, {ldq_16_bits_uop_rob_idx}, {ldq_15_bits_uop_rob_idx}, {ldq_14_bits_uop_rob_idx}, {ldq_13_bits_uop_rob_idx}, {ldq_12_bits_uop_rob_idx}, {ldq_11_bits_uop_rob_idx}, {ldq_10_bits_uop_rob_idx}, {ldq_9_bits_uop_rob_idx}, {ldq_8_bits_uop_rob_idx}, {ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rob_idx = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_134 = {{ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}, {ldq_23_bits_uop_ldq_idx}, {ldq_22_bits_uop_ldq_idx}, {ldq_21_bits_uop_ldq_idx}, {ldq_20_bits_uop_ldq_idx}, {ldq_19_bits_uop_ldq_idx}, {ldq_18_bits_uop_ldq_idx}, {ldq_17_bits_uop_ldq_idx}, {ldq_16_bits_uop_ldq_idx}, {ldq_15_bits_uop_ldq_idx}, {ldq_14_bits_uop_ldq_idx}, {ldq_13_bits_uop_ldq_idx}, {ldq_12_bits_uop_ldq_idx}, {ldq_11_bits_uop_ldq_idx}, {ldq_10_bits_uop_ldq_idx}, {ldq_9_bits_uop_ldq_idx}, {ldq_8_bits_uop_ldq_idx}, {ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldq_idx = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_135 = {{ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}, {ldq_23_bits_uop_stq_idx}, {ldq_22_bits_uop_stq_idx}, {ldq_21_bits_uop_stq_idx}, {ldq_20_bits_uop_stq_idx}, {ldq_19_bits_uop_stq_idx}, {ldq_18_bits_uop_stq_idx}, {ldq_17_bits_uop_stq_idx}, {ldq_16_bits_uop_stq_idx}, {ldq_15_bits_uop_stq_idx}, {ldq_14_bits_uop_stq_idx}, {ldq_13_bits_uop_stq_idx}, {ldq_12_bits_uop_stq_idx}, {ldq_11_bits_uop_stq_idx}, {ldq_10_bits_uop_stq_idx}, {ldq_9_bits_uop_stq_idx}, {ldq_8_bits_uop_stq_idx}, {ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stq_idx = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_136 = {{ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}, {ldq_23_bits_uop_rxq_idx}, {ldq_22_bits_uop_rxq_idx}, {ldq_21_bits_uop_rxq_idx}, {ldq_20_bits_uop_rxq_idx}, {ldq_19_bits_uop_rxq_idx}, {ldq_18_bits_uop_rxq_idx}, {ldq_17_bits_uop_rxq_idx}, {ldq_16_bits_uop_rxq_idx}, {ldq_15_bits_uop_rxq_idx}, {ldq_14_bits_uop_rxq_idx}, {ldq_13_bits_uop_rxq_idx}, {ldq_12_bits_uop_rxq_idx}, {ldq_11_bits_uop_rxq_idx}, {ldq_10_bits_uop_rxq_idx}, {ldq_9_bits_uop_rxq_idx}, {ldq_8_bits_uop_rxq_idx}, {ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_rxq_idx = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_137 = {{ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_0_bits_uop_pdst}, {ldq_23_bits_uop_pdst}, {ldq_22_bits_uop_pdst}, {ldq_21_bits_uop_pdst}, {ldq_20_bits_uop_pdst}, {ldq_19_bits_uop_pdst}, {ldq_18_bits_uop_pdst}, {ldq_17_bits_uop_pdst}, {ldq_16_bits_uop_pdst}, {ldq_15_bits_uop_pdst}, {ldq_14_bits_uop_pdst}, {ldq_13_bits_uop_pdst}, {ldq_12_bits_uop_pdst}, {ldq_11_bits_uop_pdst}, {ldq_10_bits_uop_pdst}, {ldq_9_bits_uop_pdst}, {ldq_8_bits_uop_pdst}, {ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_pdst = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_138 = {{ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_0_bits_uop_prs1}, {ldq_23_bits_uop_prs1}, {ldq_22_bits_uop_prs1}, {ldq_21_bits_uop_prs1}, {ldq_20_bits_uop_prs1}, {ldq_19_bits_uop_prs1}, {ldq_18_bits_uop_prs1}, {ldq_17_bits_uop_prs1}, {ldq_16_bits_uop_prs1}, {ldq_15_bits_uop_prs1}, {ldq_14_bits_uop_prs1}, {ldq_13_bits_uop_prs1}, {ldq_12_bits_uop_prs1}, {ldq_11_bits_uop_prs1}, {ldq_10_bits_uop_prs1}, {ldq_9_bits_uop_prs1}, {ldq_8_bits_uop_prs1}, {ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1 = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_139 = {{ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_0_bits_uop_prs2}, {ldq_23_bits_uop_prs2}, {ldq_22_bits_uop_prs2}, {ldq_21_bits_uop_prs2}, {ldq_20_bits_uop_prs2}, {ldq_19_bits_uop_prs2}, {ldq_18_bits_uop_prs2}, {ldq_17_bits_uop_prs2}, {ldq_16_bits_uop_prs2}, {ldq_15_bits_uop_prs2}, {ldq_14_bits_uop_prs2}, {ldq_13_bits_uop_prs2}, {ldq_12_bits_uop_prs2}, {ldq_11_bits_uop_prs2}, {ldq_10_bits_uop_prs2}, {ldq_9_bits_uop_prs2}, {ldq_8_bits_uop_prs2}, {ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2 = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_140 = {{ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_0_bits_uop_prs3}, {ldq_23_bits_uop_prs3}, {ldq_22_bits_uop_prs3}, {ldq_21_bits_uop_prs3}, {ldq_20_bits_uop_prs3}, {ldq_19_bits_uop_prs3}, {ldq_18_bits_uop_prs3}, {ldq_17_bits_uop_prs3}, {ldq_16_bits_uop_prs3}, {ldq_15_bits_uop_prs3}, {ldq_14_bits_uop_prs3}, {ldq_13_bits_uop_prs3}, {ldq_12_bits_uop_prs3}, {ldq_11_bits_uop_prs3}, {ldq_10_bits_uop_prs3}, {ldq_9_bits_uop_prs3}, {ldq_8_bits_uop_prs3}, {ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3 = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_141 = {{ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}, {ldq_23_bits_uop_prs1_busy}, {ldq_22_bits_uop_prs1_busy}, {ldq_21_bits_uop_prs1_busy}, {ldq_20_bits_uop_prs1_busy}, {ldq_19_bits_uop_prs1_busy}, {ldq_18_bits_uop_prs1_busy}, {ldq_17_bits_uop_prs1_busy}, {ldq_16_bits_uop_prs1_busy}, {ldq_15_bits_uop_prs1_busy}, {ldq_14_bits_uop_prs1_busy}, {ldq_13_bits_uop_prs1_busy}, {ldq_12_bits_uop_prs1_busy}, {ldq_11_bits_uop_prs1_busy}, {ldq_10_bits_uop_prs1_busy}, {ldq_9_bits_uop_prs1_busy}, {ldq_8_bits_uop_prs1_busy}, {ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs1_busy = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_142 = {{ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}, {ldq_23_bits_uop_prs2_busy}, {ldq_22_bits_uop_prs2_busy}, {ldq_21_bits_uop_prs2_busy}, {ldq_20_bits_uop_prs2_busy}, {ldq_19_bits_uop_prs2_busy}, {ldq_18_bits_uop_prs2_busy}, {ldq_17_bits_uop_prs2_busy}, {ldq_16_bits_uop_prs2_busy}, {ldq_15_bits_uop_prs2_busy}, {ldq_14_bits_uop_prs2_busy}, {ldq_13_bits_uop_prs2_busy}, {ldq_12_bits_uop_prs2_busy}, {ldq_11_bits_uop_prs2_busy}, {ldq_10_bits_uop_prs2_busy}, {ldq_9_bits_uop_prs2_busy}, {ldq_8_bits_uop_prs2_busy}, {ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs2_busy = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_143 = {{ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}, {ldq_23_bits_uop_prs3_busy}, {ldq_22_bits_uop_prs3_busy}, {ldq_21_bits_uop_prs3_busy}, {ldq_20_bits_uop_prs3_busy}, {ldq_19_bits_uop_prs3_busy}, {ldq_18_bits_uop_prs3_busy}, {ldq_17_bits_uop_prs3_busy}, {ldq_16_bits_uop_prs3_busy}, {ldq_15_bits_uop_prs3_busy}, {ldq_14_bits_uop_prs3_busy}, {ldq_13_bits_uop_prs3_busy}, {ldq_12_bits_uop_prs3_busy}, {ldq_11_bits_uop_prs3_busy}, {ldq_10_bits_uop_prs3_busy}, {ldq_9_bits_uop_prs3_busy}, {ldq_8_bits_uop_prs3_busy}, {ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_prs3_busy = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][6:0] _GEN_144 = {{ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}, {ldq_23_bits_uop_stale_pdst}, {ldq_22_bits_uop_stale_pdst}, {ldq_21_bits_uop_stale_pdst}, {ldq_20_bits_uop_stale_pdst}, {ldq_19_bits_uop_stale_pdst}, {ldq_18_bits_uop_stale_pdst}, {ldq_17_bits_uop_stale_pdst}, {ldq_16_bits_uop_stale_pdst}, {ldq_15_bits_uop_stale_pdst}, {ldq_14_bits_uop_stale_pdst}, {ldq_13_bits_uop_stale_pdst}, {ldq_12_bits_uop_stale_pdst}, {ldq_11_bits_uop_stale_pdst}, {ldq_10_bits_uop_stale_pdst}, {ldq_9_bits_uop_stale_pdst}, {ldq_8_bits_uop_stale_pdst}, {ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_stale_pdst = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_145 = {{ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_0_bits_uop_exception}, {ldq_23_bits_uop_exception}, {ldq_22_bits_uop_exception}, {ldq_21_bits_uop_exception}, {ldq_20_bits_uop_exception}, {ldq_19_bits_uop_exception}, {ldq_18_bits_uop_exception}, {ldq_17_bits_uop_exception}, {ldq_16_bits_uop_exception}, {ldq_15_bits_uop_exception}, {ldq_14_bits_uop_exception}, {ldq_13_bits_uop_exception}, {ldq_12_bits_uop_exception}, {ldq_11_bits_uop_exception}, {ldq_10_bits_uop_exception}, {ldq_9_bits_uop_exception}, {ldq_8_bits_uop_exception}, {ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exception = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][63:0] _GEN_146 = {{ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}, {ldq_23_bits_uop_exc_cause}, {ldq_22_bits_uop_exc_cause}, {ldq_21_bits_uop_exc_cause}, {ldq_20_bits_uop_exc_cause}, {ldq_19_bits_uop_exc_cause}, {ldq_18_bits_uop_exc_cause}, {ldq_17_bits_uop_exc_cause}, {ldq_16_bits_uop_exc_cause}, {ldq_15_bits_uop_exc_cause}, {ldq_14_bits_uop_exc_cause}, {ldq_13_bits_uop_exc_cause}, {ldq_12_bits_uop_exc_cause}, {ldq_11_bits_uop_exc_cause}, {ldq_10_bits_uop_exc_cause}, {ldq_9_bits_uop_exc_cause}, {ldq_8_bits_uop_exc_cause}, {ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_exc_cause = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_147 = {{ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}, {ldq_23_bits_uop_bypassable}, {ldq_22_bits_uop_bypassable}, {ldq_21_bits_uop_bypassable}, {ldq_20_bits_uop_bypassable}, {ldq_19_bits_uop_bypassable}, {ldq_18_bits_uop_bypassable}, {ldq_17_bits_uop_bypassable}, {ldq_16_bits_uop_bypassable}, {ldq_15_bits_uop_bypassable}, {ldq_14_bits_uop_bypassable}, {ldq_13_bits_uop_bypassable}, {ldq_12_bits_uop_bypassable}, {ldq_11_bits_uop_bypassable}, {ldq_10_bits_uop_bypassable}, {ldq_9_bits_uop_bypassable}, {ldq_8_bits_uop_bypassable}, {ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bypassable = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_148 = {{ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}, {ldq_23_bits_uop_mem_cmd}, {ldq_22_bits_uop_mem_cmd}, {ldq_21_bits_uop_mem_cmd}, {ldq_20_bits_uop_mem_cmd}, {ldq_19_bits_uop_mem_cmd}, {ldq_18_bits_uop_mem_cmd}, {ldq_17_bits_uop_mem_cmd}, {ldq_16_bits_uop_mem_cmd}, {ldq_15_bits_uop_mem_cmd}, {ldq_14_bits_uop_mem_cmd}, {ldq_13_bits_uop_mem_cmd}, {ldq_12_bits_uop_mem_cmd}, {ldq_11_bits_uop_mem_cmd}, {ldq_10_bits_uop_mem_cmd}, {ldq_9_bits_uop_mem_cmd}, {ldq_8_bits_uop_mem_cmd}, {ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_cmd = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_149 = {{ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}, {ldq_23_bits_uop_mem_size}, {ldq_22_bits_uop_mem_size}, {ldq_21_bits_uop_mem_size}, {ldq_20_bits_uop_mem_size}, {ldq_19_bits_uop_mem_size}, {ldq_18_bits_uop_mem_size}, {ldq_17_bits_uop_mem_size}, {ldq_16_bits_uop_mem_size}, {ldq_15_bits_uop_mem_size}, {ldq_14_bits_uop_mem_size}, {ldq_13_bits_uop_mem_size}, {ldq_12_bits_uop_mem_size}, {ldq_11_bits_uop_mem_size}, {ldq_10_bits_uop_mem_size}, {ldq_9_bits_uop_mem_size}, {ldq_8_bits_uop_mem_size}, {ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_size = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_150 = {{ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}, {ldq_23_bits_uop_mem_signed}, {ldq_22_bits_uop_mem_signed}, {ldq_21_bits_uop_mem_signed}, {ldq_20_bits_uop_mem_signed}, {ldq_19_bits_uop_mem_signed}, {ldq_18_bits_uop_mem_signed}, {ldq_17_bits_uop_mem_signed}, {ldq_16_bits_uop_mem_signed}, {ldq_15_bits_uop_mem_signed}, {ldq_14_bits_uop_mem_signed}, {ldq_13_bits_uop_mem_signed}, {ldq_12_bits_uop_mem_signed}, {ldq_11_bits_uop_mem_signed}, {ldq_10_bits_uop_mem_signed}, {ldq_9_bits_uop_mem_signed}, {ldq_8_bits_uop_mem_signed}, {ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_mem_signed = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_151 = {{ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}, {ldq_23_bits_uop_is_fence}, {ldq_22_bits_uop_is_fence}, {ldq_21_bits_uop_is_fence}, {ldq_20_bits_uop_is_fence}, {ldq_19_bits_uop_is_fence}, {ldq_18_bits_uop_is_fence}, {ldq_17_bits_uop_is_fence}, {ldq_16_bits_uop_is_fence}, {ldq_15_bits_uop_is_fence}, {ldq_14_bits_uop_is_fence}, {ldq_13_bits_uop_is_fence}, {ldq_12_bits_uop_is_fence}, {ldq_11_bits_uop_is_fence}, {ldq_10_bits_uop_is_fence}, {ldq_9_bits_uop_is_fence}, {ldq_8_bits_uop_is_fence}, {ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fence = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_152 = {{ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}, {ldq_23_bits_uop_is_fencei}, {ldq_22_bits_uop_is_fencei}, {ldq_21_bits_uop_is_fencei}, {ldq_20_bits_uop_is_fencei}, {ldq_19_bits_uop_is_fencei}, {ldq_18_bits_uop_is_fencei}, {ldq_17_bits_uop_is_fencei}, {ldq_16_bits_uop_is_fencei}, {ldq_15_bits_uop_is_fencei}, {ldq_14_bits_uop_is_fencei}, {ldq_13_bits_uop_is_fencei}, {ldq_12_bits_uop_is_fencei}, {ldq_11_bits_uop_is_fencei}, {ldq_10_bits_uop_is_fencei}, {ldq_9_bits_uop_is_fencei}, {ldq_8_bits_uop_is_fencei}, {ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_fencei = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_153 = {{ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}, {ldq_23_bits_uop_is_amo}, {ldq_22_bits_uop_is_amo}, {ldq_21_bits_uop_is_amo}, {ldq_20_bits_uop_is_amo}, {ldq_19_bits_uop_is_amo}, {ldq_18_bits_uop_is_amo}, {ldq_17_bits_uop_is_amo}, {ldq_16_bits_uop_is_amo}, {ldq_15_bits_uop_is_amo}, {ldq_14_bits_uop_is_amo}, {ldq_13_bits_uop_is_amo}, {ldq_12_bits_uop_is_amo}, {ldq_11_bits_uop_is_amo}, {ldq_10_bits_uop_is_amo}, {ldq_9_bits_uop_is_amo}, {ldq_8_bits_uop_is_amo}, {ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_amo = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_154 = {{ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}, {ldq_23_bits_uop_uses_ldq}, {ldq_22_bits_uop_uses_ldq}, {ldq_21_bits_uop_uses_ldq}, {ldq_20_bits_uop_uses_ldq}, {ldq_19_bits_uop_uses_ldq}, {ldq_18_bits_uop_uses_ldq}, {ldq_17_bits_uop_uses_ldq}, {ldq_16_bits_uop_uses_ldq}, {ldq_15_bits_uop_uses_ldq}, {ldq_14_bits_uop_uses_ldq}, {ldq_13_bits_uop_uses_ldq}, {ldq_12_bits_uop_uses_ldq}, {ldq_11_bits_uop_uses_ldq}, {ldq_10_bits_uop_uses_ldq}, {ldq_9_bits_uop_uses_ldq}, {ldq_8_bits_uop_uses_ldq}, {ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_ldq = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_155 = {{ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}, {ldq_23_bits_uop_uses_stq}, {ldq_22_bits_uop_uses_stq}, {ldq_21_bits_uop_uses_stq}, {ldq_20_bits_uop_uses_stq}, {ldq_19_bits_uop_uses_stq}, {ldq_18_bits_uop_uses_stq}, {ldq_17_bits_uop_uses_stq}, {ldq_16_bits_uop_uses_stq}, {ldq_15_bits_uop_uses_stq}, {ldq_14_bits_uop_uses_stq}, {ldq_13_bits_uop_uses_stq}, {ldq_12_bits_uop_uses_stq}, {ldq_11_bits_uop_uses_stq}, {ldq_10_bits_uop_uses_stq}, {ldq_9_bits_uop_uses_stq}, {ldq_8_bits_uop_uses_stq}, {ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_uses_stq = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_156 = {{ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}, {ldq_23_bits_uop_is_sys_pc2epc}, {ldq_22_bits_uop_is_sys_pc2epc}, {ldq_21_bits_uop_is_sys_pc2epc}, {ldq_20_bits_uop_is_sys_pc2epc}, {ldq_19_bits_uop_is_sys_pc2epc}, {ldq_18_bits_uop_is_sys_pc2epc}, {ldq_17_bits_uop_is_sys_pc2epc}, {ldq_16_bits_uop_is_sys_pc2epc}, {ldq_15_bits_uop_is_sys_pc2epc}, {ldq_14_bits_uop_is_sys_pc2epc}, {ldq_13_bits_uop_is_sys_pc2epc}, {ldq_12_bits_uop_is_sys_pc2epc}, {ldq_11_bits_uop_is_sys_pc2epc}, {ldq_10_bits_uop_is_sys_pc2epc}, {ldq_9_bits_uop_is_sys_pc2epc}, {ldq_8_bits_uop_is_sys_pc2epc}, {ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_157 = {{ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}, {ldq_23_bits_uop_is_unique}, {ldq_22_bits_uop_is_unique}, {ldq_21_bits_uop_is_unique}, {ldq_20_bits_uop_is_unique}, {ldq_19_bits_uop_is_unique}, {ldq_18_bits_uop_is_unique}, {ldq_17_bits_uop_is_unique}, {ldq_16_bits_uop_is_unique}, {ldq_15_bits_uop_is_unique}, {ldq_14_bits_uop_is_unique}, {ldq_13_bits_uop_is_unique}, {ldq_12_bits_uop_is_unique}, {ldq_11_bits_uop_is_unique}, {ldq_10_bits_uop_is_unique}, {ldq_9_bits_uop_is_unique}, {ldq_8_bits_uop_is_unique}, {ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_is_unique = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_158 = {{ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}, {ldq_23_bits_uop_flush_on_commit}, {ldq_22_bits_uop_flush_on_commit}, {ldq_21_bits_uop_flush_on_commit}, {ldq_20_bits_uop_flush_on_commit}, {ldq_19_bits_uop_flush_on_commit}, {ldq_18_bits_uop_flush_on_commit}, {ldq_17_bits_uop_flush_on_commit}, {ldq_16_bits_uop_flush_on_commit}, {ldq_15_bits_uop_flush_on_commit}, {ldq_14_bits_uop_flush_on_commit}, {ldq_13_bits_uop_flush_on_commit}, {ldq_12_bits_uop_flush_on_commit}, {ldq_11_bits_uop_flush_on_commit}, {ldq_10_bits_uop_flush_on_commit}, {ldq_9_bits_uop_flush_on_commit}, {ldq_8_bits_uop_flush_on_commit}, {ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_flush_on_commit = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_159 = {{ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}, {ldq_23_bits_uop_ldst_is_rs1}, {ldq_22_bits_uop_ldst_is_rs1}, {ldq_21_bits_uop_ldst_is_rs1}, {ldq_20_bits_uop_ldst_is_rs1}, {ldq_19_bits_uop_ldst_is_rs1}, {ldq_18_bits_uop_ldst_is_rs1}, {ldq_17_bits_uop_ldst_is_rs1}, {ldq_16_bits_uop_ldst_is_rs1}, {ldq_15_bits_uop_ldst_is_rs1}, {ldq_14_bits_uop_ldst_is_rs1}, {ldq_13_bits_uop_ldst_is_rs1}, {ldq_12_bits_uop_ldst_is_rs1}, {ldq_11_bits_uop_ldst_is_rs1}, {ldq_10_bits_uop_ldst_is_rs1}, {ldq_9_bits_uop_ldst_is_rs1}, {ldq_8_bits_uop_ldst_is_rs1}, {ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][5:0] _GEN_160 = {{ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_0_bits_uop_ldst}, {ldq_23_bits_uop_ldst}, {ldq_22_bits_uop_ldst}, {ldq_21_bits_uop_ldst}, {ldq_20_bits_uop_ldst}, {ldq_19_bits_uop_ldst}, {ldq_18_bits_uop_ldst}, {ldq_17_bits_uop_ldst}, {ldq_16_bits_uop_ldst}, {ldq_15_bits_uop_ldst}, {ldq_14_bits_uop_ldst}, {ldq_13_bits_uop_ldst}, {ldq_12_bits_uop_ldst}, {ldq_11_bits_uop_ldst}, {ldq_10_bits_uop_ldst}, {ldq_9_bits_uop_ldst}, {ldq_8_bits_uop_ldst}, {ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][5:0] _GEN_161 = {{ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}, {ldq_23_bits_uop_lrs1}, {ldq_22_bits_uop_lrs1}, {ldq_21_bits_uop_lrs1}, {ldq_20_bits_uop_lrs1}, {ldq_19_bits_uop_lrs1}, {ldq_18_bits_uop_lrs1}, {ldq_17_bits_uop_lrs1}, {ldq_16_bits_uop_lrs1}, {ldq_15_bits_uop_lrs1}, {ldq_14_bits_uop_lrs1}, {ldq_13_bits_uop_lrs1}, {ldq_12_bits_uop_lrs1}, {ldq_11_bits_uop_lrs1}, {ldq_10_bits_uop_lrs1}, {ldq_9_bits_uop_lrs1}, {ldq_8_bits_uop_lrs1}, {ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1 = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][5:0] _GEN_162 = {{ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}, {ldq_23_bits_uop_lrs2}, {ldq_22_bits_uop_lrs2}, {ldq_21_bits_uop_lrs2}, {ldq_20_bits_uop_lrs2}, {ldq_19_bits_uop_lrs2}, {ldq_18_bits_uop_lrs2}, {ldq_17_bits_uop_lrs2}, {ldq_16_bits_uop_lrs2}, {ldq_15_bits_uop_lrs2}, {ldq_14_bits_uop_lrs2}, {ldq_13_bits_uop_lrs2}, {ldq_12_bits_uop_lrs2}, {ldq_11_bits_uop_lrs2}, {ldq_10_bits_uop_lrs2}, {ldq_9_bits_uop_lrs2}, {ldq_8_bits_uop_lrs2}, {ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2 = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][5:0] _GEN_163 = {{ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}, {ldq_23_bits_uop_lrs3}, {ldq_22_bits_uop_lrs3}, {ldq_21_bits_uop_lrs3}, {ldq_20_bits_uop_lrs3}, {ldq_19_bits_uop_lrs3}, {ldq_18_bits_uop_lrs3}, {ldq_17_bits_uop_lrs3}, {ldq_16_bits_uop_lrs3}, {ldq_15_bits_uop_lrs3}, {ldq_14_bits_uop_lrs3}, {ldq_13_bits_uop_lrs3}, {ldq_12_bits_uop_lrs3}, {ldq_11_bits_uop_lrs3}, {ldq_10_bits_uop_lrs3}, {ldq_9_bits_uop_lrs3}, {ldq_8_bits_uop_lrs3}, {ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs3 = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_164 = {{ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}, {ldq_23_bits_uop_ldst_val}, {ldq_22_bits_uop_ldst_val}, {ldq_21_bits_uop_ldst_val}, {ldq_20_bits_uop_ldst_val}, {ldq_19_bits_uop_ldst_val}, {ldq_18_bits_uop_ldst_val}, {ldq_17_bits_uop_ldst_val}, {ldq_16_bits_uop_ldst_val}, {ldq_15_bits_uop_ldst_val}, {ldq_14_bits_uop_ldst_val}, {ldq_13_bits_uop_ldst_val}, {ldq_12_bits_uop_ldst_val}, {ldq_11_bits_uop_ldst_val}, {ldq_10_bits_uop_ldst_val}, {ldq_9_bits_uop_ldst_val}, {ldq_8_bits_uop_ldst_val}, {ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_ldst_val = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_165 = {{ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}, {ldq_23_bits_uop_dst_rtype}, {ldq_22_bits_uop_dst_rtype}, {ldq_21_bits_uop_dst_rtype}, {ldq_20_bits_uop_dst_rtype}, {ldq_19_bits_uop_dst_rtype}, {ldq_18_bits_uop_dst_rtype}, {ldq_17_bits_uop_dst_rtype}, {ldq_16_bits_uop_dst_rtype}, {ldq_15_bits_uop_dst_rtype}, {ldq_14_bits_uop_dst_rtype}, {ldq_13_bits_uop_dst_rtype}, {ldq_12_bits_uop_dst_rtype}, {ldq_11_bits_uop_dst_rtype}, {ldq_10_bits_uop_dst_rtype}, {ldq_9_bits_uop_dst_rtype}, {ldq_8_bits_uop_dst_rtype}, {ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_dst_rtype = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_166 = {{ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}, {ldq_23_bits_uop_lrs1_rtype}, {ldq_22_bits_uop_lrs1_rtype}, {ldq_21_bits_uop_lrs1_rtype}, {ldq_20_bits_uop_lrs1_rtype}, {ldq_19_bits_uop_lrs1_rtype}, {ldq_18_bits_uop_lrs1_rtype}, {ldq_17_bits_uop_lrs1_rtype}, {ldq_16_bits_uop_lrs1_rtype}, {ldq_15_bits_uop_lrs1_rtype}, {ldq_14_bits_uop_lrs1_rtype}, {ldq_13_bits_uop_lrs1_rtype}, {ldq_12_bits_uop_lrs1_rtype}, {ldq_11_bits_uop_lrs1_rtype}, {ldq_10_bits_uop_lrs1_rtype}, {ldq_9_bits_uop_lrs1_rtype}, {ldq_8_bits_uop_lrs1_rtype}, {ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_167 = {{ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}, {ldq_23_bits_uop_lrs2_rtype}, {ldq_22_bits_uop_lrs2_rtype}, {ldq_21_bits_uop_lrs2_rtype}, {ldq_20_bits_uop_lrs2_rtype}, {ldq_19_bits_uop_lrs2_rtype}, {ldq_18_bits_uop_lrs2_rtype}, {ldq_17_bits_uop_lrs2_rtype}, {ldq_16_bits_uop_lrs2_rtype}, {ldq_15_bits_uop_lrs2_rtype}, {ldq_14_bits_uop_lrs2_rtype}, {ldq_13_bits_uop_lrs2_rtype}, {ldq_12_bits_uop_lrs2_rtype}, {ldq_11_bits_uop_lrs2_rtype}, {ldq_10_bits_uop_lrs2_rtype}, {ldq_9_bits_uop_lrs2_rtype}, {ldq_8_bits_uop_lrs2_rtype}, {ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_168 = {{ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}, {ldq_23_bits_uop_frs3_en}, {ldq_22_bits_uop_frs3_en}, {ldq_21_bits_uop_frs3_en}, {ldq_20_bits_uop_frs3_en}, {ldq_19_bits_uop_frs3_en}, {ldq_18_bits_uop_frs3_en}, {ldq_17_bits_uop_frs3_en}, {ldq_16_bits_uop_frs3_en}, {ldq_15_bits_uop_frs3_en}, {ldq_14_bits_uop_frs3_en}, {ldq_13_bits_uop_frs3_en}, {ldq_12_bits_uop_frs3_en}, {ldq_11_bits_uop_frs3_en}, {ldq_10_bits_uop_frs3_en}, {ldq_9_bits_uop_frs3_en}, {ldq_8_bits_uop_frs3_en}, {ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_frs3_en = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_169 = {{ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}, {ldq_23_bits_uop_fp_val}, {ldq_22_bits_uop_fp_val}, {ldq_21_bits_uop_fp_val}, {ldq_20_bits_uop_fp_val}, {ldq_19_bits_uop_fp_val}, {ldq_18_bits_uop_fp_val}, {ldq_17_bits_uop_fp_val}, {ldq_16_bits_uop_fp_val}, {ldq_15_bits_uop_fp_val}, {ldq_14_bits_uop_fp_val}, {ldq_13_bits_uop_fp_val}, {ldq_12_bits_uop_fp_val}, {ldq_11_bits_uop_fp_val}, {ldq_10_bits_uop_fp_val}, {ldq_9_bits_uop_fp_val}, {ldq_8_bits_uop_fp_val}, {ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_val = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_170 = {{ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}, {ldq_23_bits_uop_fp_single}, {ldq_22_bits_uop_fp_single}, {ldq_21_bits_uop_fp_single}, {ldq_20_bits_uop_fp_single}, {ldq_19_bits_uop_fp_single}, {ldq_18_bits_uop_fp_single}, {ldq_17_bits_uop_fp_single}, {ldq_16_bits_uop_fp_single}, {ldq_15_bits_uop_fp_single}, {ldq_14_bits_uop_fp_single}, {ldq_13_bits_uop_fp_single}, {ldq_12_bits_uop_fp_single}, {ldq_11_bits_uop_fp_single}, {ldq_10_bits_uop_fp_single}, {ldq_9_bits_uop_fp_single}, {ldq_8_bits_uop_fp_single}, {ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_fp_single = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_171 = {{ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}, {ldq_23_bits_uop_xcpt_pf_if}, {ldq_22_bits_uop_xcpt_pf_if}, {ldq_21_bits_uop_xcpt_pf_if}, {ldq_20_bits_uop_xcpt_pf_if}, {ldq_19_bits_uop_xcpt_pf_if}, {ldq_18_bits_uop_xcpt_pf_if}, {ldq_17_bits_uop_xcpt_pf_if}, {ldq_16_bits_uop_xcpt_pf_if}, {ldq_15_bits_uop_xcpt_pf_if}, {ldq_14_bits_uop_xcpt_pf_if}, {ldq_13_bits_uop_xcpt_pf_if}, {ldq_12_bits_uop_xcpt_pf_if}, {ldq_11_bits_uop_xcpt_pf_if}, {ldq_10_bits_uop_xcpt_pf_if}, {ldq_9_bits_uop_xcpt_pf_if}, {ldq_8_bits_uop_xcpt_pf_if}, {ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_172 = {{ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}, {ldq_23_bits_uop_xcpt_ae_if}, {ldq_22_bits_uop_xcpt_ae_if}, {ldq_21_bits_uop_xcpt_ae_if}, {ldq_20_bits_uop_xcpt_ae_if}, {ldq_19_bits_uop_xcpt_ae_if}, {ldq_18_bits_uop_xcpt_ae_if}, {ldq_17_bits_uop_xcpt_ae_if}, {ldq_16_bits_uop_xcpt_ae_if}, {ldq_15_bits_uop_xcpt_ae_if}, {ldq_14_bits_uop_xcpt_ae_if}, {ldq_13_bits_uop_xcpt_ae_if}, {ldq_12_bits_uop_xcpt_ae_if}, {ldq_11_bits_uop_xcpt_ae_if}, {ldq_10_bits_uop_xcpt_ae_if}, {ldq_9_bits_uop_xcpt_ae_if}, {ldq_8_bits_uop_xcpt_ae_if}, {ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_173 = {{ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}, {ldq_23_bits_uop_xcpt_ma_if}, {ldq_22_bits_uop_xcpt_ma_if}, {ldq_21_bits_uop_xcpt_ma_if}, {ldq_20_bits_uop_xcpt_ma_if}, {ldq_19_bits_uop_xcpt_ma_if}, {ldq_18_bits_uop_xcpt_ma_if}, {ldq_17_bits_uop_xcpt_ma_if}, {ldq_16_bits_uop_xcpt_ma_if}, {ldq_15_bits_uop_xcpt_ma_if}, {ldq_14_bits_uop_xcpt_ma_if}, {ldq_13_bits_uop_xcpt_ma_if}, {ldq_12_bits_uop_xcpt_ma_if}, {ldq_11_bits_uop_xcpt_ma_if}, {ldq_10_bits_uop_xcpt_ma_if}, {ldq_9_bits_uop_xcpt_ma_if}, {ldq_8_bits_uop_xcpt_ma_if}, {ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_174 = {{ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}, {ldq_23_bits_uop_bp_debug_if}, {ldq_22_bits_uop_bp_debug_if}, {ldq_21_bits_uop_bp_debug_if}, {ldq_20_bits_uop_bp_debug_if}, {ldq_19_bits_uop_bp_debug_if}, {ldq_18_bits_uop_bp_debug_if}, {ldq_17_bits_uop_bp_debug_if}, {ldq_16_bits_uop_bp_debug_if}, {ldq_15_bits_uop_bp_debug_if}, {ldq_14_bits_uop_bp_debug_if}, {ldq_13_bits_uop_bp_debug_if}, {ldq_12_bits_uop_bp_debug_if}, {ldq_11_bits_uop_bp_debug_if}, {ldq_10_bits_uop_bp_debug_if}, {ldq_9_bits_uop_bp_debug_if}, {ldq_8_bits_uop_bp_debug_if}, {ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_debug_if = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_175 = {{ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}, {ldq_23_bits_uop_bp_xcpt_if}, {ldq_22_bits_uop_bp_xcpt_if}, {ldq_21_bits_uop_bp_xcpt_if}, {ldq_20_bits_uop_bp_xcpt_if}, {ldq_19_bits_uop_bp_xcpt_if}, {ldq_18_bits_uop_bp_xcpt_if}, {ldq_17_bits_uop_bp_xcpt_if}, {ldq_16_bits_uop_bp_xcpt_if}, {ldq_15_bits_uop_bp_xcpt_if}, {ldq_14_bits_uop_bp_xcpt_if}, {ldq_13_bits_uop_bp_xcpt_if}, {ldq_12_bits_uop_bp_xcpt_if}, {ldq_11_bits_uop_bp_xcpt_if}, {ldq_10_bits_uop_bp_xcpt_if}, {ldq_9_bits_uop_bp_xcpt_if}, {ldq_8_bits_uop_bp_xcpt_if}, {ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_176 = {{ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}, {ldq_23_bits_uop_debug_fsrc}, {ldq_22_bits_uop_debug_fsrc}, {ldq_21_bits_uop_debug_fsrc}, {ldq_20_bits_uop_debug_fsrc}, {ldq_19_bits_uop_debug_fsrc}, {ldq_18_bits_uop_debug_fsrc}, {ldq_17_bits_uop_debug_fsrc}, {ldq_16_bits_uop_debug_fsrc}, {ldq_15_bits_uop_debug_fsrc}, {ldq_14_bits_uop_debug_fsrc}, {ldq_13_bits_uop_debug_fsrc}, {ldq_12_bits_uop_debug_fsrc}, {ldq_11_bits_uop_debug_fsrc}, {ldq_10_bits_uop_debug_fsrc}, {ldq_9_bits_uop_debug_fsrc}, {ldq_8_bits_uop_debug_fsrc}, {ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_fsrc = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][1:0] _GEN_177 = {{ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}, {ldq_23_bits_uop_debug_tsrc}, {ldq_22_bits_uop_debug_tsrc}, {ldq_21_bits_uop_debug_tsrc}, {ldq_20_bits_uop_debug_tsrc}, {ldq_19_bits_uop_debug_tsrc}, {ldq_18_bits_uop_debug_tsrc}, {ldq_17_bits_uop_debug_tsrc}, {ldq_16_bits_uop_debug_tsrc}, {ldq_15_bits_uop_debug_tsrc}, {ldq_14_bits_uop_debug_tsrc}, {ldq_13_bits_uop_debug_tsrc}, {ldq_12_bits_uop_debug_tsrc}, {ldq_11_bits_uop_debug_tsrc}, {ldq_10_bits_uop_debug_tsrc}, {ldq_9_bits_uop_debug_tsrc}, {ldq_8_bits_uop_debug_tsrc}, {ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_uop_debug_tsrc = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_178 = {{ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_0_bits_addr_valid}, {ldq_23_bits_addr_valid}, {ldq_22_bits_addr_valid}, {ldq_21_bits_addr_valid}, {ldq_20_bits_addr_valid}, {ldq_19_bits_addr_valid}, {ldq_18_bits_addr_valid}, {ldq_17_bits_addr_valid}, {ldq_16_bits_addr_valid}, {ldq_15_bits_addr_valid}, {ldq_14_bits_addr_valid}, {ldq_13_bits_addr_valid}, {ldq_12_bits_addr_valid}, {ldq_11_bits_addr_valid}, {ldq_10_bits_addr_valid}, {ldq_9_bits_addr_valid}, {ldq_8_bits_addr_valid}, {ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_valid = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][39:0] _GEN_179 = {{ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_0_bits_addr_bits}, {ldq_23_bits_addr_bits}, {ldq_22_bits_addr_bits}, {ldq_21_bits_addr_bits}, {ldq_20_bits_addr_bits}, {ldq_19_bits_addr_bits}, {ldq_18_bits_addr_bits}, {ldq_17_bits_addr_bits}, {ldq_16_bits_addr_bits}, {ldq_15_bits_addr_bits}, {ldq_14_bits_addr_bits}, {ldq_13_bits_addr_bits}, {ldq_12_bits_addr_bits}, {ldq_11_bits_addr_bits}, {ldq_10_bits_addr_bits}, {ldq_9_bits_addr_bits}, {ldq_8_bits_addr_bits}, {ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_bits = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_180 = {{ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}, {ldq_23_bits_addr_is_virtual}, {ldq_22_bits_addr_is_virtual}, {ldq_21_bits_addr_is_virtual}, {ldq_20_bits_addr_is_virtual}, {ldq_19_bits_addr_is_virtual}, {ldq_18_bits_addr_is_virtual}, {ldq_17_bits_addr_is_virtual}, {ldq_16_bits_addr_is_virtual}, {ldq_15_bits_addr_is_virtual}, {ldq_14_bits_addr_is_virtual}, {ldq_13_bits_addr_is_virtual}, {ldq_12_bits_addr_is_virtual}, {ldq_11_bits_addr_is_virtual}, {ldq_10_bits_addr_is_virtual}, {ldq_9_bits_addr_is_virtual}, {ldq_8_bits_addr_is_virtual}, {ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_virtual = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_181 = {{ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}, {ldq_23_bits_addr_is_uncacheable}, {ldq_22_bits_addr_is_uncacheable}, {ldq_21_bits_addr_is_uncacheable}, {ldq_20_bits_addr_is_uncacheable}, {ldq_19_bits_addr_is_uncacheable}, {ldq_18_bits_addr_is_uncacheable}, {ldq_17_bits_addr_is_uncacheable}, {ldq_16_bits_addr_is_uncacheable}, {ldq_15_bits_addr_is_uncacheable}, {ldq_14_bits_addr_is_uncacheable}, {ldq_13_bits_addr_is_uncacheable}, {ldq_12_bits_addr_is_uncacheable}, {ldq_11_bits_addr_is_uncacheable}, {ldq_10_bits_addr_is_uncacheable}, {ldq_9_bits_addr_is_uncacheable}, {ldq_8_bits_addr_is_uncacheable}, {ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_addr_is_uncacheable = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_182 = {{ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_0_bits_executed}, {ldq_23_bits_executed}, {ldq_22_bits_executed}, {ldq_21_bits_executed}, {ldq_20_bits_executed}, {ldq_19_bits_executed}, {ldq_18_bits_executed}, {ldq_17_bits_executed}, {ldq_16_bits_executed}, {ldq_15_bits_executed}, {ldq_14_bits_executed}, {ldq_13_bits_executed}, {ldq_12_bits_executed}, {ldq_11_bits_executed}, {ldq_10_bits_executed}, {ldq_9_bits_executed}, {ldq_8_bits_executed}, {ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_executed = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_183 = {{ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_0_bits_succeeded}, {ldq_23_bits_succeeded}, {ldq_22_bits_succeeded}, {ldq_21_bits_succeeded}, {ldq_20_bits_succeeded}, {ldq_19_bits_succeeded}, {ldq_18_bits_succeeded}, {ldq_17_bits_succeeded}, {ldq_16_bits_succeeded}, {ldq_15_bits_succeeded}, {ldq_14_bits_succeeded}, {ldq_13_bits_succeeded}, {ldq_12_bits_succeeded}, {ldq_11_bits_succeeded}, {ldq_10_bits_succeeded}, {ldq_9_bits_succeeded}, {ldq_8_bits_succeeded}, {ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_succeeded = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_184 = {{ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_0_bits_order_fail}, {ldq_23_bits_order_fail}, {ldq_22_bits_order_fail}, {ldq_21_bits_order_fail}, {ldq_20_bits_order_fail}, {ldq_19_bits_order_fail}, {ldq_18_bits_order_fail}, {ldq_17_bits_order_fail}, {ldq_16_bits_order_fail}, {ldq_15_bits_order_fail}, {ldq_14_bits_order_fail}, {ldq_13_bits_order_fail}, {ldq_12_bits_order_fail}, {ldq_11_bits_order_fail}, {ldq_10_bits_order_fail}, {ldq_9_bits_order_fail}, {ldq_8_bits_order_fail}, {ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_order_fail = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_185 = {{ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_0_bits_observed}, {ldq_23_bits_observed}, {ldq_22_bits_observed}, {ldq_21_bits_observed}, {ldq_20_bits_observed}, {ldq_19_bits_observed}, {ldq_18_bits_observed}, {ldq_17_bits_observed}, {ldq_16_bits_observed}, {ldq_15_bits_observed}, {ldq_14_bits_observed}, {ldq_13_bits_observed}, {ldq_12_bits_observed}, {ldq_11_bits_observed}, {ldq_10_bits_observed}, {ldq_9_bits_observed}, {ldq_8_bits_observed}, {ldq_7_bits_observed}, {ldq_6_bits_observed}, {ldq_5_bits_observed}, {ldq_4_bits_observed}, {ldq_3_bits_observed}, {ldq_2_bits_observed}, {ldq_1_bits_observed}, {ldq_0_bits_observed}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_observed = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][23:0] _GEN_186 = {{ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}, {ldq_23_bits_st_dep_mask}, {ldq_22_bits_st_dep_mask}, {ldq_21_bits_st_dep_mask}, {ldq_20_bits_st_dep_mask}, {ldq_19_bits_st_dep_mask}, {ldq_18_bits_st_dep_mask}, {ldq_17_bits_st_dep_mask}, {ldq_16_bits_st_dep_mask}, {ldq_15_bits_st_dep_mask}, {ldq_14_bits_st_dep_mask}, {ldq_13_bits_st_dep_mask}, {ldq_12_bits_st_dep_mask}, {ldq_11_bits_st_dep_mask}, {ldq_10_bits_st_dep_mask}, {ldq_9_bits_st_dep_mask}, {ldq_8_bits_st_dep_mask}, {ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_st_dep_mask = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_187 = {{ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}, {ldq_23_bits_youngest_stq_idx}, {ldq_22_bits_youngest_stq_idx}, {ldq_21_bits_youngest_stq_idx}, {ldq_20_bits_youngest_stq_idx}, {ldq_19_bits_youngest_stq_idx}, {ldq_18_bits_youngest_stq_idx}, {ldq_17_bits_youngest_stq_idx}, {ldq_16_bits_youngest_stq_idx}, {ldq_15_bits_youngest_stq_idx}, {ldq_14_bits_youngest_stq_idx}, {ldq_13_bits_youngest_stq_idx}, {ldq_12_bits_youngest_stq_idx}, {ldq_11_bits_youngest_stq_idx}, {ldq_10_bits_youngest_stq_idx}, {ldq_9_bits_youngest_stq_idx}, {ldq_8_bits_youngest_stq_idx}, {ldq_7_bits_youngest_stq_idx}, {ldq_6_bits_youngest_stq_idx}, {ldq_5_bits_youngest_stq_idx}, {ldq_4_bits_youngest_stq_idx}, {ldq_3_bits_youngest_stq_idx}, {ldq_2_bits_youngest_stq_idx}, {ldq_1_bits_youngest_stq_idx}, {ldq_0_bits_youngest_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_youngest_stq_idx = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0] _GEN_188 = {{ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_0_bits_forward_std_val}, {ldq_23_bits_forward_std_val}, {ldq_22_bits_forward_std_val}, {ldq_21_bits_forward_std_val}, {ldq_20_bits_forward_std_val}, {ldq_19_bits_forward_std_val}, {ldq_18_bits_forward_std_val}, {ldq_17_bits_forward_std_val}, {ldq_16_bits_forward_std_val}, {ldq_15_bits_forward_std_val}, {ldq_14_bits_forward_std_val}, {ldq_13_bits_forward_std_val}, {ldq_12_bits_forward_std_val}, {ldq_11_bits_forward_std_val}, {ldq_10_bits_forward_std_val}, {ldq_9_bits_forward_std_val}, {ldq_8_bits_forward_std_val}, {ldq_7_bits_forward_std_val}, {ldq_6_bits_forward_std_val}, {ldq_5_bits_forward_std_val}, {ldq_4_bits_forward_std_val}, {ldq_3_bits_forward_std_val}, {ldq_2_bits_forward_std_val}, {ldq_1_bits_forward_std_val}, {ldq_0_bits_forward_std_val}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_std_val = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][4:0] _GEN_189 = {{ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}, {ldq_23_bits_forward_stq_idx}, {ldq_22_bits_forward_stq_idx}, {ldq_21_bits_forward_stq_idx}, {ldq_20_bits_forward_stq_idx}, {ldq_19_bits_forward_stq_idx}, {ldq_18_bits_forward_stq_idx}, {ldq_17_bits_forward_stq_idx}, {ldq_16_bits_forward_stq_idx}, {ldq_15_bits_forward_stq_idx}, {ldq_14_bits_forward_stq_idx}, {ldq_13_bits_forward_stq_idx}, {ldq_12_bits_forward_stq_idx}, {ldq_11_bits_forward_stq_idx}, {ldq_10_bits_forward_stq_idx}, {ldq_9_bits_forward_stq_idx}, {ldq_8_bits_forward_stq_idx}, {ldq_7_bits_forward_stq_idx}, {ldq_6_bits_forward_stq_idx}, {ldq_5_bits_forward_stq_idx}, {ldq_4_bits_forward_stq_idx}, {ldq_3_bits_forward_stq_idx}, {ldq_2_bits_forward_stq_idx}, {ldq_1_bits_forward_stq_idx}, {ldq_0_bits_forward_stq_idx}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_forward_stq_idx = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][63:0] _GEN_190 = {{ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}, {ldq_23_bits_debug_wb_data}, {ldq_22_bits_debug_wb_data}, {ldq_21_bits_debug_wb_data}, {ldq_20_bits_debug_wb_data}, {ldq_19_bits_debug_wb_data}, {ldq_18_bits_debug_wb_data}, {ldq_17_bits_debug_wb_data}, {ldq_16_bits_debug_wb_data}, {ldq_15_bits_debug_wb_data}, {ldq_14_bits_debug_wb_data}, {ldq_13_bits_debug_wb_data}, {ldq_12_bits_debug_wb_data}, {ldq_11_bits_debug_wb_data}, {ldq_10_bits_debug_wb_data}, {ldq_9_bits_debug_wb_data}, {ldq_8_bits_debug_wb_data}, {ldq_7_bits_debug_wb_data}, {ldq_6_bits_debug_wb_data}, {ldq_5_bits_debug_wb_data}, {ldq_4_bits_debug_wb_data}, {ldq_3_bits_debug_wb_data}, {ldq_2_bits_debug_wb_data}, {ldq_1_bits_debug_wb_data}, {ldq_0_bits_debug_wb_data}}; // @[lsu.scala:208:16, :263:49] assign ldq_incoming_e_0_bits_debug_wb_data = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:263:49] wire [6:0] mem_stq_incoming_e_out_bits_uop_uopc = stq_incoming_e_0_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:106:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iq_type = stq_incoming_e_0_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] mem_stq_incoming_e_out_bits_uop_fu_code = stq_incoming_e_0_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_ctrl_br_type = stq_incoming_e_0_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel = stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel = stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel = stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn = stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw = stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd = stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_load = stq_incoming_e_0_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_sta = stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ctrl_is_std = stq_incoming_e_0_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_iw_state = stq_incoming_e_0_bits_uop_iw_state; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned = stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned = stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_br = stq_incoming_e_0_bits_uop_is_br; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jalr = stq_incoming_e_0_bits_uop_is_jalr; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_jal = stq_incoming_e_0_bits_uop_is_jal; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:106:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:106:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] mem_stq_incoming_e_out_bits_uop_csr_addr = stq_incoming_e_0_bits_uop_csr_addr; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:106:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bypassable = stq_incoming_e_0_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_ldst_val = stq_incoming_e_0_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_fp_single = stq_incoming_e_0_bits_uop_fp_single; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:106:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:106:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:106:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:106:23] wire [15:0] stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:263:49] wire stq_incoming_e_0_valid; // @[lsu.scala:263:49] assign stq_incoming_e_0_valid = _GEN[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uopc = _GEN_1[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_inst = _GEN_2[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_inst = _GEN_3[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_rvc = _GEN_4[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_pc = _GEN_5[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iq_type = _GEN_6[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fu_code = _GEN_7[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_br_type = _GEN_8[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op1_sel = _GEN_9[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op2_sel = _GEN_10[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_imm_sel = _GEN_11[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_op_fcn = _GEN_12[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_fcn_dw = _GEN_13[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_csr_cmd = _GEN_14[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_load = _GEN_15[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_sta = _GEN_16[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ctrl_is_std = _GEN_17[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_state = _GEN_18[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p1_poisoned = _GEN_19[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_iw_p2_poisoned = _GEN_20[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_br = _GEN_21[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jalr = _GEN_22[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_jal = _GEN_23[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sfb = _GEN_24[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_mask = _GEN_25[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_br_tag = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ftq_idx = _GEN_27[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_edge_inst = _GEN_28[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pc_lob = _GEN_29[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_taken = _GEN_30[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_imm_packed = _GEN_31[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_csr_addr = _GEN_32[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rob_idx = _GEN_33[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldq_idx = _GEN_34[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stq_idx = _GEN_35[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_rxq_idx = _GEN_36[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_pdst = _GEN_37[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1 = _GEN_38[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2 = _GEN_39[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3 = _GEN_40[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred = _GEN_41[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs1_busy = _GEN_42[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs2_busy = _GEN_43[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_prs3_busy = _GEN_44[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ppred_busy = _GEN_45[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_stale_pdst = _GEN_46[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exception = _GEN_47[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_exc_cause = _GEN_49[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bypassable = _GEN_50[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_cmd = _GEN_51[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_size = _GEN_52[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_mem_signed = _GEN_53[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fence = _GEN_54[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_fencei = _GEN_56[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_amo = _GEN_57[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_ldq = _GEN_59[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_uses_stq = _GEN_60[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_sys_pc2epc = _GEN_61[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_is_unique = _GEN_62[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_flush_on_commit = _GEN_63[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_is_rs1 = _GEN_64[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst = _GEN_65[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1 = _GEN_66[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2 = _GEN_67[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs3 = _GEN_68[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_ldst_val = _GEN_69[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_dst_rtype = _GEN_70[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs1_rtype = _GEN_71[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_lrs2_rtype = _GEN_72[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_frs3_en = _GEN_73[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_val = _GEN_74[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_fp_single = _GEN_75[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_pf_if = _GEN_76[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ae_if = _GEN_77[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_xcpt_ma_if = _GEN_78[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_debug_if = _GEN_79[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_bp_xcpt_if = _GEN_80[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_fsrc = _GEN_81[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_uop_debug_tsrc = _GEN_82[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_valid = _GEN_83[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_bits = _GEN_84[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_addr_is_virtual = _GEN_85[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_valid = _GEN_86[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_data_bits = _GEN_87[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] assign stq_incoming_e_0_bits_committed = _GEN_89[stq_incoming_idx_0]; // @[lsu.scala:222:42, :263:49] wire [31:0] _GEN_191 = {{stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_0_bits_succeeded}, {stq_23_bits_succeeded}, {stq_22_bits_succeeded}, {stq_21_bits_succeeded}, {stq_20_bits_succeeded}, {stq_19_bits_succeeded}, {stq_18_bits_succeeded}, {stq_17_bits_succeeded}, {stq_16_bits_succeeded}, {stq_15_bits_succeeded}, {stq_14_bits_succeeded}, {stq_13_bits_succeeded}, {stq_12_bits_succeeded}, {stq_11_bits_succeeded}, {stq_10_bits_succeeded}, {stq_9_bits_succeeded}, {stq_8_bits_succeeded}, {stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_succeeded = _GEN_191[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire [31:0][63:0] _GEN_192 = {{stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}, {stq_23_bits_debug_wb_data}, {stq_22_bits_debug_wb_data}, {stq_21_bits_debug_wb_data}, {stq_20_bits_debug_wb_data}, {stq_19_bits_debug_wb_data}, {stq_18_bits_debug_wb_data}, {stq_17_bits_debug_wb_data}, {stq_16_bits_debug_wb_data}, {stq_15_bits_debug_wb_data}, {stq_14_bits_debug_wb_data}, {stq_13_bits_debug_wb_data}, {stq_12_bits_debug_wb_data}, {stq_11_bits_debug_wb_data}, {stq_10_bits_debug_wb_data}, {stq_9_bits_debug_wb_data}, {stq_8_bits_debug_wb_data}, {stq_7_bits_debug_wb_data}, {stq_6_bits_debug_wb_data}, {stq_5_bits_debug_wb_data}, {stq_4_bits_debug_wb_data}, {stq_3_bits_debug_wb_data}, {stq_2_bits_debug_wb_data}, {stq_1_bits_debug_wb_data}, {stq_0_bits_debug_wb_data}}; // @[lsu.scala:209:16, :263:49] assign stq_incoming_e_0_bits_debug_wb_data = _GEN_192[stq_incoming_idx_0]; // @[lsu.scala:263:49] wire _GEN_193 = block_load_mask_0 | p1_block_load_mask_0; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block; // @[lsu.scala:416:36] assign ldq_retry_idx_block = _GEN_193; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block = _GEN_193; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_1 = ~ldq_retry_idx_block; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_2 = _ldq_retry_idx_T & _ldq_retry_idx_T_1; // @[lsu.scala:417:{18,39,42}] wire _GEN_194 = block_load_mask_1 | p1_block_load_mask_1; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_1; // @[lsu.scala:416:36] assign ldq_retry_idx_block_1 = _GEN_194; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_1; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_1 = _GEN_194; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_3 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_4 = ~ldq_retry_idx_block_1; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_5 = _ldq_retry_idx_T_3 & _ldq_retry_idx_T_4; // @[lsu.scala:417:{18,39,42}] wire _GEN_195 = block_load_mask_2 | p1_block_load_mask_2; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_2; // @[lsu.scala:416:36] assign ldq_retry_idx_block_2 = _GEN_195; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_2; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_2 = _GEN_195; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_6 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_7 = ~ldq_retry_idx_block_2; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_8 = _ldq_retry_idx_T_6 & _ldq_retry_idx_T_7; // @[lsu.scala:417:{18,39,42}] wire _GEN_196 = block_load_mask_3 | p1_block_load_mask_3; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_3; // @[lsu.scala:416:36] assign ldq_retry_idx_block_3 = _GEN_196; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_3; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_3 = _GEN_196; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_9 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_10 = ~ldq_retry_idx_block_3; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_11 = _ldq_retry_idx_T_9 & _ldq_retry_idx_T_10; // @[lsu.scala:417:{18,39,42}] wire _GEN_197 = block_load_mask_4 | p1_block_load_mask_4; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_4; // @[lsu.scala:416:36] assign ldq_retry_idx_block_4 = _GEN_197; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_4; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_4 = _GEN_197; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_12 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_13 = ~ldq_retry_idx_block_4; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_14 = _ldq_retry_idx_T_12 & _ldq_retry_idx_T_13; // @[lsu.scala:417:{18,39,42}] wire _GEN_198 = block_load_mask_5 | p1_block_load_mask_5; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_5; // @[lsu.scala:416:36] assign ldq_retry_idx_block_5 = _GEN_198; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_5; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_5 = _GEN_198; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_15 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_16 = ~ldq_retry_idx_block_5; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_17 = _ldq_retry_idx_T_15 & _ldq_retry_idx_T_16; // @[lsu.scala:417:{18,39,42}] wire _GEN_199 = block_load_mask_6 | p1_block_load_mask_6; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_6; // @[lsu.scala:416:36] assign ldq_retry_idx_block_6 = _GEN_199; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_6; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_6 = _GEN_199; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_18 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_19 = ~ldq_retry_idx_block_6; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_20 = _ldq_retry_idx_T_18 & _ldq_retry_idx_T_19; // @[lsu.scala:417:{18,39,42}] wire _GEN_200 = block_load_mask_7 | p1_block_load_mask_7; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_7; // @[lsu.scala:416:36] assign ldq_retry_idx_block_7 = _GEN_200; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_7; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_7 = _GEN_200; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_21 = ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_22 = ~ldq_retry_idx_block_7; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_23 = _ldq_retry_idx_T_21 & _ldq_retry_idx_T_22; // @[lsu.scala:417:{18,39,42}] wire _GEN_201 = block_load_mask_8 | p1_block_load_mask_8; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_8; // @[lsu.scala:416:36] assign ldq_retry_idx_block_8 = _GEN_201; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_8; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_8 = _GEN_201; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_24 = ldq_8_bits_addr_valid & ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_25 = ~ldq_retry_idx_block_8; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_26 = _ldq_retry_idx_T_24 & _ldq_retry_idx_T_25; // @[lsu.scala:417:{18,39,42}] wire _GEN_202 = block_load_mask_9 | p1_block_load_mask_9; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_9; // @[lsu.scala:416:36] assign ldq_retry_idx_block_9 = _GEN_202; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_9; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_9 = _GEN_202; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_27 = ldq_9_bits_addr_valid & ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_28 = ~ldq_retry_idx_block_9; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_29 = _ldq_retry_idx_T_27 & _ldq_retry_idx_T_28; // @[lsu.scala:417:{18,39,42}] wire _GEN_203 = block_load_mask_10 | p1_block_load_mask_10; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_10; // @[lsu.scala:416:36] assign ldq_retry_idx_block_10 = _GEN_203; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_10; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_10 = _GEN_203; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_30 = ldq_10_bits_addr_valid & ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_31 = ~ldq_retry_idx_block_10; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_32 = _ldq_retry_idx_T_30 & _ldq_retry_idx_T_31; // @[lsu.scala:417:{18,39,42}] wire _GEN_204 = block_load_mask_11 | p1_block_load_mask_11; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_11; // @[lsu.scala:416:36] assign ldq_retry_idx_block_11 = _GEN_204; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_11; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_11 = _GEN_204; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_33 = ldq_11_bits_addr_valid & ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_34 = ~ldq_retry_idx_block_11; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_35 = _ldq_retry_idx_T_33 & _ldq_retry_idx_T_34; // @[lsu.scala:417:{18,39,42}] wire _GEN_205 = block_load_mask_12 | p1_block_load_mask_12; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_12; // @[lsu.scala:416:36] assign ldq_retry_idx_block_12 = _GEN_205; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_12; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_12 = _GEN_205; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_36 = ldq_12_bits_addr_valid & ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_37 = ~ldq_retry_idx_block_12; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_38 = _ldq_retry_idx_T_36 & _ldq_retry_idx_T_37; // @[lsu.scala:417:{18,39,42}] wire _GEN_206 = block_load_mask_13 | p1_block_load_mask_13; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_13; // @[lsu.scala:416:36] assign ldq_retry_idx_block_13 = _GEN_206; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_13; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_13 = _GEN_206; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_39 = ldq_13_bits_addr_valid & ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_40 = ~ldq_retry_idx_block_13; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_41 = _ldq_retry_idx_T_39 & _ldq_retry_idx_T_40; // @[lsu.scala:417:{18,39,42}] wire _GEN_207 = block_load_mask_14 | p1_block_load_mask_14; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_14; // @[lsu.scala:416:36] assign ldq_retry_idx_block_14 = _GEN_207; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_14; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_14 = _GEN_207; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_42 = ldq_14_bits_addr_valid & ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_43 = ~ldq_retry_idx_block_14; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_44 = _ldq_retry_idx_T_42 & _ldq_retry_idx_T_43; // @[lsu.scala:417:{18,39,42}] wire _GEN_208 = block_load_mask_15 | p1_block_load_mask_15; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_15; // @[lsu.scala:416:36] assign ldq_retry_idx_block_15 = _GEN_208; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_15; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_15 = _GEN_208; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_45 = ldq_15_bits_addr_valid & ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_46 = ~ldq_retry_idx_block_15; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_47 = _ldq_retry_idx_T_45 & _ldq_retry_idx_T_46; // @[lsu.scala:417:{18,39,42}] wire _GEN_209 = block_load_mask_16 | p1_block_load_mask_16; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_16; // @[lsu.scala:416:36] assign ldq_retry_idx_block_16 = _GEN_209; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_16; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_16 = _GEN_209; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_48 = ldq_16_bits_addr_valid & ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_49 = ~ldq_retry_idx_block_16; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_50 = _ldq_retry_idx_T_48 & _ldq_retry_idx_T_49; // @[lsu.scala:417:{18,39,42}] wire _GEN_210 = block_load_mask_17 | p1_block_load_mask_17; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_17; // @[lsu.scala:416:36] assign ldq_retry_idx_block_17 = _GEN_210; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_17; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_17 = _GEN_210; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_51 = ldq_17_bits_addr_valid & ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_52 = ~ldq_retry_idx_block_17; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_53 = _ldq_retry_idx_T_51 & _ldq_retry_idx_T_52; // @[lsu.scala:417:{18,39,42}] wire _GEN_211 = block_load_mask_18 | p1_block_load_mask_18; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_18; // @[lsu.scala:416:36] assign ldq_retry_idx_block_18 = _GEN_211; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_18; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_18 = _GEN_211; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_54 = ldq_18_bits_addr_valid & ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_55 = ~ldq_retry_idx_block_18; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_56 = _ldq_retry_idx_T_54 & _ldq_retry_idx_T_55; // @[lsu.scala:417:{18,39,42}] wire _GEN_212 = block_load_mask_19 | p1_block_load_mask_19; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_19; // @[lsu.scala:416:36] assign ldq_retry_idx_block_19 = _GEN_212; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_19; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_19 = _GEN_212; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_57 = ldq_19_bits_addr_valid & ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_58 = ~ldq_retry_idx_block_19; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_59 = _ldq_retry_idx_T_57 & _ldq_retry_idx_T_58; // @[lsu.scala:417:{18,39,42}] wire _GEN_213 = block_load_mask_20 | p1_block_load_mask_20; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_20; // @[lsu.scala:416:36] assign ldq_retry_idx_block_20 = _GEN_213; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_20; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_20 = _GEN_213; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_60 = ldq_20_bits_addr_valid & ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_61 = ~ldq_retry_idx_block_20; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_62 = _ldq_retry_idx_T_60 & _ldq_retry_idx_T_61; // @[lsu.scala:417:{18,39,42}] wire _GEN_214 = block_load_mask_21 | p1_block_load_mask_21; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_21; // @[lsu.scala:416:36] assign ldq_retry_idx_block_21 = _GEN_214; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_21; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_21 = _GEN_214; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_63 = ldq_21_bits_addr_valid & ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_64 = ~ldq_retry_idx_block_21; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_65 = _ldq_retry_idx_T_63 & _ldq_retry_idx_T_64; // @[lsu.scala:417:{18,39,42}] wire _GEN_215 = block_load_mask_22 | p1_block_load_mask_22; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_22; // @[lsu.scala:416:36] assign ldq_retry_idx_block_22 = _GEN_215; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_22; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_22 = _GEN_215; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_66 = ldq_22_bits_addr_valid & ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_67 = ~ldq_retry_idx_block_22; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_68 = _ldq_retry_idx_T_66 & _ldq_retry_idx_T_67; // @[lsu.scala:417:{18,39,42}] wire _GEN_216 = block_load_mask_23 | p1_block_load_mask_23; // @[lsu.scala:396:36, :397:35, :416:36] wire ldq_retry_idx_block_23; // @[lsu.scala:416:36] assign ldq_retry_idx_block_23 = _GEN_216; // @[lsu.scala:416:36] wire ldq_wakeup_idx_block_23; // @[lsu.scala:431:36] assign ldq_wakeup_idx_block_23 = _GEN_216; // @[lsu.scala:416:36, :431:36] wire _ldq_retry_idx_T_69 = ldq_23_bits_addr_valid & ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16, :417:18] wire _ldq_retry_idx_T_70 = ~ldq_retry_idx_block_23; // @[lsu.scala:416:36, :417:42] wire _ldq_retry_idx_T_71 = _ldq_retry_idx_T_69 & _ldq_retry_idx_T_70; // @[lsu.scala:417:{18,39,42}] wire _GEN_217 = ldq_head == 5'h0; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T = _GEN_217; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_217; // @[util.scala:351:72] wire _temp_bits_T; // @[lsu.scala:1230:28] assign _temp_bits_T = _GEN_217; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_0 = _ldq_retry_idx_T_2 & _ldq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _GEN_218 = ldq_head < 5'h2; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_1 = _GEN_218; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_218; // @[util.scala:351:72] wire _temp_bits_T_2; // @[lsu.scala:1230:28] assign _temp_bits_T_2 = _GEN_218; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_1 = _ldq_retry_idx_T_5 & _ldq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _GEN_219 = ldq_head < 5'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_2 = _GEN_219; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_219; // @[util.scala:351:72] wire _temp_bits_T_4; // @[lsu.scala:1230:28] assign _temp_bits_T_4 = _GEN_219; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_2 = _ldq_retry_idx_T_8 & _ldq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _GEN_220 = ldq_head < 5'h4; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_3 = _GEN_220; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_220; // @[util.scala:351:72] wire _temp_bits_T_6; // @[lsu.scala:1230:28] assign _temp_bits_T_6 = _GEN_220; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_3 = _ldq_retry_idx_T_11 & _ldq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _GEN_221 = ldq_head < 5'h5; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_4 = _GEN_221; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_221; // @[util.scala:351:72] wire _temp_bits_T_8; // @[lsu.scala:1230:28] assign _temp_bits_T_8 = _GEN_221; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_4 = _ldq_retry_idx_T_14 & _ldq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _GEN_222 = ldq_head < 5'h6; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_5 = _GEN_222; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_222; // @[util.scala:351:72] wire _temp_bits_T_10; // @[lsu.scala:1230:28] assign _temp_bits_T_10 = _GEN_222; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_5 = _ldq_retry_idx_T_17 & _ldq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _GEN_223 = ldq_head < 5'h7; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_6 = _GEN_223; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_223; // @[util.scala:351:72] wire _temp_bits_T_12; // @[lsu.scala:1230:28] assign _temp_bits_T_12 = _GEN_223; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_6 = _ldq_retry_idx_T_20 & _ldq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire _GEN_224 = ldq_head < 5'h8; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_7; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_7 = _GEN_224; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_7 = _GEN_224; // @[util.scala:351:72] wire _temp_bits_T_14; // @[lsu.scala:1230:28] assign _temp_bits_T_14 = _GEN_224; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_7 = _ldq_retry_idx_T_23 & _ldq_retry_idx_temp_vec_T_7; // @[util.scala:351:{65,72}] wire _GEN_225 = ldq_head < 5'h9; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_8; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_8 = _GEN_225; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_225; // @[util.scala:351:72] wire _temp_bits_T_16; // @[lsu.scala:1230:28] assign _temp_bits_T_16 = _GEN_225; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_8 = _ldq_retry_idx_T_26 & _ldq_retry_idx_temp_vec_T_8; // @[util.scala:351:{65,72}] wire _GEN_226 = ldq_head < 5'hA; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_9; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_9 = _GEN_226; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_226; // @[util.scala:351:72] wire _temp_bits_T_18; // @[lsu.scala:1230:28] assign _temp_bits_T_18 = _GEN_226; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_9 = _ldq_retry_idx_T_29 & _ldq_retry_idx_temp_vec_T_9; // @[util.scala:351:{65,72}] wire _GEN_227 = ldq_head < 5'hB; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_10; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_10 = _GEN_227; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_227; // @[util.scala:351:72] wire _temp_bits_T_20; // @[lsu.scala:1230:28] assign _temp_bits_T_20 = _GEN_227; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_10 = _ldq_retry_idx_T_32 & _ldq_retry_idx_temp_vec_T_10; // @[util.scala:351:{65,72}] wire _GEN_228 = ldq_head < 5'hC; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_11; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_11 = _GEN_228; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_228; // @[util.scala:351:72] wire _temp_bits_T_22; // @[lsu.scala:1230:28] assign _temp_bits_T_22 = _GEN_228; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_11 = _ldq_retry_idx_T_35 & _ldq_retry_idx_temp_vec_T_11; // @[util.scala:351:{65,72}] wire _GEN_229 = ldq_head < 5'hD; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_12; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_12 = _GEN_229; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_229; // @[util.scala:351:72] wire _temp_bits_T_24; // @[lsu.scala:1230:28] assign _temp_bits_T_24 = _GEN_229; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_12 = _ldq_retry_idx_T_38 & _ldq_retry_idx_temp_vec_T_12; // @[util.scala:351:{65,72}] wire _GEN_230 = ldq_head < 5'hE; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_13; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_13 = _GEN_230; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_230; // @[util.scala:351:72] wire _temp_bits_T_26; // @[lsu.scala:1230:28] assign _temp_bits_T_26 = _GEN_230; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_13 = _ldq_retry_idx_T_41 & _ldq_retry_idx_temp_vec_T_13; // @[util.scala:351:{65,72}] wire _GEN_231 = ldq_head < 5'hF; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_14; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_14 = _GEN_231; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_231; // @[util.scala:351:72] wire _temp_bits_T_28; // @[lsu.scala:1230:28] assign _temp_bits_T_28 = _GEN_231; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_14 = _ldq_retry_idx_T_44 & _ldq_retry_idx_temp_vec_T_14; // @[util.scala:351:{65,72}] wire _searcher_is_older_T_63 = ldq_head[4]; // @[util.scala:351:72, :363:78] wire _ldq_retry_idx_temp_vec_T_15 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78] wire ldq_retry_idx_temp_vec_15 = _ldq_retry_idx_T_47 & _ldq_retry_idx_temp_vec_T_15; // @[util.scala:351:{65,72}] wire _GEN_232 = ldq_head < 5'h11; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_16; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_16 = _GEN_232; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_16 = _GEN_232; // @[util.scala:351:72] wire _temp_bits_T_32; // @[lsu.scala:1230:28] assign _temp_bits_T_32 = _GEN_232; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_16 = _ldq_retry_idx_T_50 & _ldq_retry_idx_temp_vec_T_16; // @[util.scala:351:{65,72}] wire _GEN_233 = ldq_head < 5'h12; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_17; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_17 = _GEN_233; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_17 = _GEN_233; // @[util.scala:351:72] wire _temp_bits_T_34; // @[lsu.scala:1230:28] assign _temp_bits_T_34 = _GEN_233; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_17 = _ldq_retry_idx_T_53 & _ldq_retry_idx_temp_vec_T_17; // @[util.scala:351:{65,72}] wire _GEN_234 = ldq_head < 5'h13; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_18; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_18 = _GEN_234; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_18 = _GEN_234; // @[util.scala:351:72] wire _temp_bits_T_36; // @[lsu.scala:1230:28] assign _temp_bits_T_36 = _GEN_234; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_18 = _ldq_retry_idx_T_56 & _ldq_retry_idx_temp_vec_T_18; // @[util.scala:351:{65,72}] wire _GEN_235 = ldq_head < 5'h14; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_19; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_19 = _GEN_235; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_19 = _GEN_235; // @[util.scala:351:72] wire _temp_bits_T_38; // @[lsu.scala:1230:28] assign _temp_bits_T_38 = _GEN_235; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_19 = _ldq_retry_idx_T_59 & _ldq_retry_idx_temp_vec_T_19; // @[util.scala:351:{65,72}] wire _GEN_236 = ldq_head < 5'h15; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_20; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_20 = _GEN_236; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_20 = _GEN_236; // @[util.scala:351:72] wire _temp_bits_T_40; // @[lsu.scala:1230:28] assign _temp_bits_T_40 = _GEN_236; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_20 = _ldq_retry_idx_T_62 & _ldq_retry_idx_temp_vec_T_20; // @[util.scala:351:{65,72}] wire _GEN_237 = ldq_head < 5'h16; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_21; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_21 = _GEN_237; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_21 = _GEN_237; // @[util.scala:351:72] wire _temp_bits_T_42; // @[lsu.scala:1230:28] assign _temp_bits_T_42 = _GEN_237; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_21 = _ldq_retry_idx_T_65 & _ldq_retry_idx_temp_vec_T_21; // @[util.scala:351:{65,72}] wire _GEN_238 = ldq_head < 5'h17; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_22; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_22 = _GEN_238; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_22 = _GEN_238; // @[util.scala:351:72] wire _temp_bits_T_44; // @[lsu.scala:1230:28] assign _temp_bits_T_44 = _GEN_238; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_22 = _ldq_retry_idx_T_68 & _ldq_retry_idx_temp_vec_T_22; // @[util.scala:351:{65,72}] wire _GEN_239 = ldq_head[4:3] != 2'h3; // @[util.scala:351:72] wire _ldq_retry_idx_temp_vec_T_23; // @[util.scala:351:72] assign _ldq_retry_idx_temp_vec_T_23 = _GEN_239; // @[util.scala:351:72] wire _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:351:72] assign _ldq_wakeup_idx_temp_vec_T_23 = _GEN_239; // @[util.scala:351:72] wire _temp_bits_T_46; // @[lsu.scala:1230:28] assign _temp_bits_T_46 = _GEN_239; // @[util.scala:351:72] wire ldq_retry_idx_temp_vec_23 = _ldq_retry_idx_T_71 & _ldq_retry_idx_temp_vec_T_23; // @[util.scala:351:{65,72}] wire [5:0] _ldq_retry_idx_idx_T = {5'h1B, ~_ldq_retry_idx_T_68}; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_1 = _ldq_retry_idx_T_65 ? 6'h35 : _ldq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_2 = _ldq_retry_idx_T_62 ? 6'h34 : _ldq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_3 = _ldq_retry_idx_T_59 ? 6'h33 : _ldq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_4 = _ldq_retry_idx_T_56 ? 6'h32 : _ldq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_5 = _ldq_retry_idx_T_53 ? 6'h31 : _ldq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_6 = _ldq_retry_idx_T_50 ? 6'h30 : _ldq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_7 = _ldq_retry_idx_T_47 ? 6'h2F : _ldq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_8 = _ldq_retry_idx_T_44 ? 6'h2E : _ldq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_9 = _ldq_retry_idx_T_41 ? 6'h2D : _ldq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_10 = _ldq_retry_idx_T_38 ? 6'h2C : _ldq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_11 = _ldq_retry_idx_T_35 ? 6'h2B : _ldq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_12 = _ldq_retry_idx_T_32 ? 6'h2A : _ldq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_13 = _ldq_retry_idx_T_29 ? 6'h29 : _ldq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_14 = _ldq_retry_idx_T_26 ? 6'h28 : _ldq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_15 = _ldq_retry_idx_T_23 ? 6'h27 : _ldq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_16 = _ldq_retry_idx_T_20 ? 6'h26 : _ldq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_17 = _ldq_retry_idx_T_17 ? 6'h25 : _ldq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_18 = _ldq_retry_idx_T_14 ? 6'h24 : _ldq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_19 = _ldq_retry_idx_T_11 ? 6'h23 : _ldq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_20 = _ldq_retry_idx_T_8 ? 6'h22 : _ldq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_21 = _ldq_retry_idx_T_5 ? 6'h21 : _ldq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_22 = _ldq_retry_idx_T_2 ? 6'h20 : _ldq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_23 = _ldq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_24 = _ldq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_25 = _ldq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_26 = _ldq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_27 = _ldq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_28 = _ldq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_29 = _ldq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_30 = _ldq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_31 = ldq_retry_idx_temp_vec_23 ? 6'h17 : _ldq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_32 = ldq_retry_idx_temp_vec_22 ? 6'h16 : _ldq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_33 = ldq_retry_idx_temp_vec_21 ? 6'h15 : _ldq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_34 = ldq_retry_idx_temp_vec_20 ? 6'h14 : _ldq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_35 = ldq_retry_idx_temp_vec_19 ? 6'h13 : _ldq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_36 = ldq_retry_idx_temp_vec_18 ? 6'h12 : _ldq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_37 = ldq_retry_idx_temp_vec_17 ? 6'h11 : _ldq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_38 = ldq_retry_idx_temp_vec_16 ? 6'h10 : _ldq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_39 = ldq_retry_idx_temp_vec_15 ? 6'hF : _ldq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_40 = ldq_retry_idx_temp_vec_14 ? 6'hE : _ldq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_41 = ldq_retry_idx_temp_vec_13 ? 6'hD : _ldq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_42 = ldq_retry_idx_temp_vec_12 ? 6'hC : _ldq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_43 = ldq_retry_idx_temp_vec_11 ? 6'hB : _ldq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_44 = ldq_retry_idx_temp_vec_10 ? 6'hA : _ldq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_45 = ldq_retry_idx_temp_vec_9 ? 6'h9 : _ldq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_46 = ldq_retry_idx_temp_vec_8 ? 6'h8 : _ldq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_47 = ldq_retry_idx_temp_vec_7 ? 6'h7 : _ldq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_48 = ldq_retry_idx_temp_vec_6 ? 6'h6 : _ldq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_49 = ldq_retry_idx_temp_vec_5 ? 6'h5 : _ldq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_50 = ldq_retry_idx_temp_vec_4 ? 6'h4 : _ldq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_51 = ldq_retry_idx_temp_vec_3 ? 6'h3 : _ldq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_52 = ldq_retry_idx_temp_vec_2 ? 6'h2 : _ldq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_retry_idx_idx_T_53 = ldq_retry_idx_temp_vec_1 ? 6'h1 : _ldq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_retry_idx_idx = ldq_retry_idx_temp_vec_0 ? 6'h0 : _ldq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_retry_idx_T_72 = ldq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] ldq_retry_idx; // @[lsu.scala:414:30] wire [4:0] _ldq_retry_e_T = ldq_retry_idx; // @[lsu.scala:414:30] wire [4:0] _can_fire_load_retry_T_2 = ldq_retry_idx; // @[lsu.scala:414:30] wire [4:0] _can_fire_load_retry_T_6 = ldq_retry_idx; // @[lsu.scala:414:30] wire [4:0] _ldq_retry_e_T_1 = _ldq_retry_e_T; wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_7 = stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_8 = stq_8_bits_addr_valid & stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_9 = stq_9_bits_addr_valid & stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_10 = stq_10_bits_addr_valid & stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_11 = stq_11_bits_addr_valid & stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_12 = stq_12_bits_addr_valid & stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_13 = stq_13_bits_addr_valid & stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_14 = stq_14_bits_addr_valid & stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_15 = stq_15_bits_addr_valid & stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_16 = stq_16_bits_addr_valid & stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_17 = stq_17_bits_addr_valid & stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_18 = stq_18_bits_addr_valid & stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_19 = stq_19_bits_addr_valid & stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_20 = stq_20_bits_addr_valid & stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_21 = stq_21_bits_addr_valid & stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_22 = stq_22_bits_addr_valid & stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_T_23 = stq_23_bits_addr_valid & stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16, :423:18] wire _stq_retry_idx_temp_vec_T = stq_commit_head == 5'h0; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_0 = _stq_retry_idx_T & _stq_retry_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_1 = stq_commit_head < 5'h2; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_1 = _stq_retry_idx_T_1 & _stq_retry_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_2 = stq_commit_head < 5'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_2 = _stq_retry_idx_T_2 & _stq_retry_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_3 = stq_commit_head < 5'h4; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_3 = _stq_retry_idx_T_3 & _stq_retry_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_4 = stq_commit_head < 5'h5; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_4 = _stq_retry_idx_T_4 & _stq_retry_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_5 = stq_commit_head < 5'h6; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_5 = _stq_retry_idx_T_5 & _stq_retry_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_6 = stq_commit_head < 5'h7; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_6 = _stq_retry_idx_T_6 & _stq_retry_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_7 = stq_commit_head < 5'h8; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_7 = _stq_retry_idx_T_7 & _stq_retry_idx_temp_vec_T_7; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_8 = stq_commit_head < 5'h9; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_8 = _stq_retry_idx_T_8 & _stq_retry_idx_temp_vec_T_8; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_9 = stq_commit_head < 5'hA; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_9 = _stq_retry_idx_T_9 & _stq_retry_idx_temp_vec_T_9; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_10 = stq_commit_head < 5'hB; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_10 = _stq_retry_idx_T_10 & _stq_retry_idx_temp_vec_T_10; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_11 = stq_commit_head < 5'hC; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_11 = _stq_retry_idx_T_11 & _stq_retry_idx_temp_vec_T_11; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_12 = stq_commit_head < 5'hD; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_12 = _stq_retry_idx_T_12 & _stq_retry_idx_temp_vec_T_12; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_13 = stq_commit_head < 5'hE; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_13 = _stq_retry_idx_T_13 & _stq_retry_idx_temp_vec_T_13; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_14 = stq_commit_head < 5'hF; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_14 = _stq_retry_idx_T_14 & _stq_retry_idx_temp_vec_T_14; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:351:72] wire stq_retry_idx_temp_vec_15 = _stq_retry_idx_T_15 & _stq_retry_idx_temp_vec_T_15; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_16 = stq_commit_head < 5'h11; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_16 = _stq_retry_idx_T_16 & _stq_retry_idx_temp_vec_T_16; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_17 = stq_commit_head < 5'h12; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_17 = _stq_retry_idx_T_17 & _stq_retry_idx_temp_vec_T_17; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_18 = stq_commit_head < 5'h13; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_18 = _stq_retry_idx_T_18 & _stq_retry_idx_temp_vec_T_18; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_19 = stq_commit_head < 5'h14; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_19 = _stq_retry_idx_T_19 & _stq_retry_idx_temp_vec_T_19; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_20 = stq_commit_head < 5'h15; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_20 = _stq_retry_idx_T_20 & _stq_retry_idx_temp_vec_T_20; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_21 = stq_commit_head < 5'h16; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_21 = _stq_retry_idx_T_21 & _stq_retry_idx_temp_vec_T_21; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_22 = stq_commit_head < 5'h17; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_22 = _stq_retry_idx_T_22 & _stq_retry_idx_temp_vec_T_22; // @[util.scala:351:{65,72}] wire _stq_retry_idx_temp_vec_T_23 = stq_commit_head[4:3] != 2'h3; // @[util.scala:351:72] wire stq_retry_idx_temp_vec_23 = _stq_retry_idx_T_23 & _stq_retry_idx_temp_vec_T_23; // @[util.scala:351:{65,72}] wire [5:0] _stq_retry_idx_idx_T = {5'h1B, ~_stq_retry_idx_T_22}; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_1 = _stq_retry_idx_T_21 ? 6'h35 : _stq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_2 = _stq_retry_idx_T_20 ? 6'h34 : _stq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_3 = _stq_retry_idx_T_19 ? 6'h33 : _stq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_4 = _stq_retry_idx_T_18 ? 6'h32 : _stq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_5 = _stq_retry_idx_T_17 ? 6'h31 : _stq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_6 = _stq_retry_idx_T_16 ? 6'h30 : _stq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_7 = _stq_retry_idx_T_15 ? 6'h2F : _stq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_8 = _stq_retry_idx_T_14 ? 6'h2E : _stq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_9 = _stq_retry_idx_T_13 ? 6'h2D : _stq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_10 = _stq_retry_idx_T_12 ? 6'h2C : _stq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_11 = _stq_retry_idx_T_11 ? 6'h2B : _stq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_12 = _stq_retry_idx_T_10 ? 6'h2A : _stq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_13 = _stq_retry_idx_T_9 ? 6'h29 : _stq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_14 = _stq_retry_idx_T_8 ? 6'h28 : _stq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_15 = _stq_retry_idx_T_7 ? 6'h27 : _stq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_16 = _stq_retry_idx_T_6 ? 6'h26 : _stq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_17 = _stq_retry_idx_T_5 ? 6'h25 : _stq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_18 = _stq_retry_idx_T_4 ? 6'h24 : _stq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_19 = _stq_retry_idx_T_3 ? 6'h23 : _stq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_20 = _stq_retry_idx_T_2 ? 6'h22 : _stq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_21 = _stq_retry_idx_T_1 ? 6'h21 : _stq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_22 = _stq_retry_idx_T ? 6'h20 : _stq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_23 = _stq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_24 = _stq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_25 = _stq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_26 = _stq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_27 = _stq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_28 = _stq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_29 = _stq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_30 = _stq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_31 = stq_retry_idx_temp_vec_23 ? 6'h17 : _stq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_32 = stq_retry_idx_temp_vec_22 ? 6'h16 : _stq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_33 = stq_retry_idx_temp_vec_21 ? 6'h15 : _stq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_34 = stq_retry_idx_temp_vec_20 ? 6'h14 : _stq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_35 = stq_retry_idx_temp_vec_19 ? 6'h13 : _stq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_36 = stq_retry_idx_temp_vec_18 ? 6'h12 : _stq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_37 = stq_retry_idx_temp_vec_17 ? 6'h11 : _stq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_38 = stq_retry_idx_temp_vec_16 ? 6'h10 : _stq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_39 = stq_retry_idx_temp_vec_15 ? 6'hF : _stq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_40 = stq_retry_idx_temp_vec_14 ? 6'hE : _stq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_41 = stq_retry_idx_temp_vec_13 ? 6'hD : _stq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_42 = stq_retry_idx_temp_vec_12 ? 6'hC : _stq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_43 = stq_retry_idx_temp_vec_11 ? 6'hB : _stq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_44 = stq_retry_idx_temp_vec_10 ? 6'hA : _stq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_45 = stq_retry_idx_temp_vec_9 ? 6'h9 : _stq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_46 = stq_retry_idx_temp_vec_8 ? 6'h8 : _stq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_47 = stq_retry_idx_temp_vec_7 ? 6'h7 : _stq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_48 = stq_retry_idx_temp_vec_6 ? 6'h6 : _stq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_49 = stq_retry_idx_temp_vec_5 ? 6'h5 : _stq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_50 = stq_retry_idx_temp_vec_4 ? 6'h4 : _stq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_51 = stq_retry_idx_temp_vec_3 ? 6'h3 : _stq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_52 = stq_retry_idx_temp_vec_2 ? 6'h2 : _stq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _stq_retry_idx_idx_T_53 = stq_retry_idx_temp_vec_1 ? 6'h1 : _stq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] stq_retry_idx_idx = stq_retry_idx_temp_vec_0 ? 6'h0 : _stq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _stq_retry_idx_T_24 = stq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] stq_retry_idx; // @[lsu.scala:421:30] wire [4:0] _stq_retry_e_T = stq_retry_idx; // @[lsu.scala:421:30] wire [4:0] _stq_retry_e_T_1 = _stq_retry_e_T; wire _ldq_wakeup_idx_T = ~ldq_0_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_1 = ldq_0_bits_addr_valid & _ldq_wakeup_idx_T; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_2 = ~ldq_0_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_4 = ~ldq_0_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_8 = ~ldq_1_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_9 = ldq_1_bits_addr_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_10 = ~ldq_1_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_12 = ~ldq_1_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_16 = ~ldq_2_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_17 = ldq_2_bits_addr_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_18 = ~ldq_2_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_20 = ~ldq_2_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_24 = ~ldq_3_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_25 = ldq_3_bits_addr_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_26 = ~ldq_3_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_28 = ~ldq_3_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_32 = ~ldq_4_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_33 = ldq_4_bits_addr_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_34 = ~ldq_4_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_36 = ~ldq_4_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_40 = ~ldq_5_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_41 = ldq_5_bits_addr_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_42 = ~ldq_5_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_44 = ~ldq_5_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_48 = ~ldq_6_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_49 = ldq_6_bits_addr_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_50 = ~ldq_6_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_52 = ~ldq_6_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_56 = ~ldq_7_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_57 = ldq_7_bits_addr_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_58 = ~ldq_7_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_60 = ~ldq_7_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_64 = ~ldq_8_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_65 = ldq_8_bits_addr_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_66 = ~ldq_8_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_68 = ~ldq_8_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_72 = ~ldq_9_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_73 = ldq_9_bits_addr_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_74 = ~ldq_9_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_76 = ~ldq_9_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_80 = ~ldq_10_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_81 = ldq_10_bits_addr_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_82 = ~ldq_10_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_84 = ~ldq_10_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_88 = ~ldq_11_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_89 = ldq_11_bits_addr_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_90 = ~ldq_11_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_92 = ~ldq_11_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_96 = ~ldq_12_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_97 = ldq_12_bits_addr_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_98 = ~ldq_12_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_100 = ~ldq_12_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_104 = ~ldq_13_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_105 = ldq_13_bits_addr_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_106 = ~ldq_13_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_108 = ~ldq_13_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_112 = ~ldq_14_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_113 = ldq_14_bits_addr_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_114 = ~ldq_14_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_116 = ~ldq_14_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_120 = ~ldq_15_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_121 = ldq_15_bits_addr_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_122 = ~ldq_15_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_124 = ~ldq_15_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_128 = ~ldq_16_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_129 = ldq_16_bits_addr_valid & _ldq_wakeup_idx_T_128; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_130 = ~ldq_16_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_131 = _ldq_wakeup_idx_T_129 & _ldq_wakeup_idx_T_130; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_132 = ~ldq_16_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_133 = _ldq_wakeup_idx_T_131 & _ldq_wakeup_idx_T_132; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_134 = ~ldq_wakeup_idx_block_16; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_135 = _ldq_wakeup_idx_T_133 & _ldq_wakeup_idx_T_134; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_136 = ~ldq_17_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_137 = ldq_17_bits_addr_valid & _ldq_wakeup_idx_T_136; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_138 = ~ldq_17_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_139 = _ldq_wakeup_idx_T_137 & _ldq_wakeup_idx_T_138; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_140 = ~ldq_17_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_141 = _ldq_wakeup_idx_T_139 & _ldq_wakeup_idx_T_140; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_142 = ~ldq_wakeup_idx_block_17; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_143 = _ldq_wakeup_idx_T_141 & _ldq_wakeup_idx_T_142; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_144 = ~ldq_18_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_145 = ldq_18_bits_addr_valid & _ldq_wakeup_idx_T_144; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_146 = ~ldq_18_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_147 = _ldq_wakeup_idx_T_145 & _ldq_wakeup_idx_T_146; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_148 = ~ldq_18_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_149 = _ldq_wakeup_idx_T_147 & _ldq_wakeup_idx_T_148; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_150 = ~ldq_wakeup_idx_block_18; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_151 = _ldq_wakeup_idx_T_149 & _ldq_wakeup_idx_T_150; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_152 = ~ldq_19_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_153 = ldq_19_bits_addr_valid & _ldq_wakeup_idx_T_152; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_154 = ~ldq_19_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_155 = _ldq_wakeup_idx_T_153 & _ldq_wakeup_idx_T_154; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_156 = ~ldq_19_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_157 = _ldq_wakeup_idx_T_155 & _ldq_wakeup_idx_T_156; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_158 = ~ldq_wakeup_idx_block_19; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_159 = _ldq_wakeup_idx_T_157 & _ldq_wakeup_idx_T_158; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_160 = ~ldq_20_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_161 = ldq_20_bits_addr_valid & _ldq_wakeup_idx_T_160; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_162 = ~ldq_20_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_163 = _ldq_wakeup_idx_T_161 & _ldq_wakeup_idx_T_162; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_164 = ~ldq_20_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_165 = _ldq_wakeup_idx_T_163 & _ldq_wakeup_idx_T_164; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_166 = ~ldq_wakeup_idx_block_20; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_167 = _ldq_wakeup_idx_T_165 & _ldq_wakeup_idx_T_166; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_168 = ~ldq_21_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_169 = ldq_21_bits_addr_valid & _ldq_wakeup_idx_T_168; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_170 = ~ldq_21_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_171 = _ldq_wakeup_idx_T_169 & _ldq_wakeup_idx_T_170; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_172 = ~ldq_21_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_173 = _ldq_wakeup_idx_T_171 & _ldq_wakeup_idx_T_172; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_174 = ~ldq_wakeup_idx_block_21; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_175 = _ldq_wakeup_idx_T_173 & _ldq_wakeup_idx_T_174; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_176 = ~ldq_22_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_177 = ldq_22_bits_addr_valid & _ldq_wakeup_idx_T_176; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_178 = ~ldq_22_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_179 = _ldq_wakeup_idx_T_177 & _ldq_wakeup_idx_T_178; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_180 = ~ldq_22_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_181 = _ldq_wakeup_idx_T_179 & _ldq_wakeup_idx_T_180; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_182 = ~ldq_wakeup_idx_block_22; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_183 = _ldq_wakeup_idx_T_181 & _ldq_wakeup_idx_T_182; // @[lsu.scala:432:{49,71,74}] wire _ldq_wakeup_idx_T_184 = ~ldq_23_bits_executed; // @[lsu.scala:208:16, :432:21] wire _ldq_wakeup_idx_T_185 = ldq_23_bits_addr_valid & _ldq_wakeup_idx_T_184; // @[lsu.scala:208:16, :432:{18,21}] wire _ldq_wakeup_idx_T_186 = ~ldq_23_bits_succeeded; // @[lsu.scala:208:16, :432:36] wire _ldq_wakeup_idx_T_187 = _ldq_wakeup_idx_T_185 & _ldq_wakeup_idx_T_186; // @[lsu.scala:432:{18,33,36}] wire _ldq_wakeup_idx_T_188 = ~ldq_23_bits_addr_is_virtual; // @[lsu.scala:208:16, :432:52] wire _ldq_wakeup_idx_T_189 = _ldq_wakeup_idx_T_187 & _ldq_wakeup_idx_T_188; // @[lsu.scala:432:{33,49,52}] wire _ldq_wakeup_idx_T_190 = ~ldq_wakeup_idx_block_23; // @[lsu.scala:431:36, :432:74] wire _ldq_wakeup_idx_T_191 = _ldq_wakeup_idx_T_189 & _ldq_wakeup_idx_T_190; // @[lsu.scala:432:{49,71,74}] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:351:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_15 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78] wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127 & _ldq_wakeup_idx_temp_vec_T_15; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_16 = _ldq_wakeup_idx_T_135 & _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_17 = _ldq_wakeup_idx_T_143 & _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_18 = _ldq_wakeup_idx_T_151 & _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_19 = _ldq_wakeup_idx_T_159 & _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_20 = _ldq_wakeup_idx_T_167 & _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_21 = _ldq_wakeup_idx_T_175 & _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_22 = _ldq_wakeup_idx_T_183 & _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:351:{65,72}] wire ldq_wakeup_idx_temp_vec_23 = _ldq_wakeup_idx_T_191 & _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:351:{65,72}] wire [5:0] _ldq_wakeup_idx_idx_T = {5'h1B, ~_ldq_wakeup_idx_T_183}; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_175 ? 6'h35 : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_167 ? 6'h34 : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_159 ? 6'h33 : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_151 ? 6'h32 : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_143 ? 6'h31 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_135 ? 6'h30 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_127 ? 6'h2F : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_119 ? 6'h2E : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_111 ? 6'h2D : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_103 ? 6'h2C : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_95 ? 6'h2B : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_87 ? 6'h2A : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_79 ? 6'h29 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_71 ? 6'h28 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_15 = _ldq_wakeup_idx_T_63 ? 6'h27 : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_16 = _ldq_wakeup_idx_T_55 ? 6'h26 : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_17 = _ldq_wakeup_idx_T_47 ? 6'h25 : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_18 = _ldq_wakeup_idx_T_39 ? 6'h24 : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_19 = _ldq_wakeup_idx_T_31 ? 6'h23 : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_20 = _ldq_wakeup_idx_T_23 ? 6'h22 : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_21 = _ldq_wakeup_idx_T_15 ? 6'h21 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_22 = _ldq_wakeup_idx_T_7 ? 6'h20 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_23 = _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_24 = _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_25 = _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_26 = _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_27 = _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_28 = _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_29 = _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_30 = _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_31 = ldq_wakeup_idx_temp_vec_23 ? 6'h17 : _ldq_wakeup_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_32 = ldq_wakeup_idx_temp_vec_22 ? 6'h16 : _ldq_wakeup_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_33 = ldq_wakeup_idx_temp_vec_21 ? 6'h15 : _ldq_wakeup_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_34 = ldq_wakeup_idx_temp_vec_20 ? 6'h14 : _ldq_wakeup_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_35 = ldq_wakeup_idx_temp_vec_19 ? 6'h13 : _ldq_wakeup_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_36 = ldq_wakeup_idx_temp_vec_18 ? 6'h12 : _ldq_wakeup_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_37 = ldq_wakeup_idx_temp_vec_17 ? 6'h11 : _ldq_wakeup_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_38 = ldq_wakeup_idx_temp_vec_16 ? 6'h10 : _ldq_wakeup_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_39 = ldq_wakeup_idx_temp_vec_15 ? 6'hF : _ldq_wakeup_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_40 = ldq_wakeup_idx_temp_vec_14 ? 6'hE : _ldq_wakeup_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_41 = ldq_wakeup_idx_temp_vec_13 ? 6'hD : _ldq_wakeup_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_42 = ldq_wakeup_idx_temp_vec_12 ? 6'hC : _ldq_wakeup_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_43 = ldq_wakeup_idx_temp_vec_11 ? 6'hB : _ldq_wakeup_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_44 = ldq_wakeup_idx_temp_vec_10 ? 6'hA : _ldq_wakeup_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_45 = ldq_wakeup_idx_temp_vec_9 ? 6'h9 : _ldq_wakeup_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_46 = ldq_wakeup_idx_temp_vec_8 ? 6'h8 : _ldq_wakeup_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_47 = ldq_wakeup_idx_temp_vec_7 ? 6'h7 : _ldq_wakeup_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_48 = ldq_wakeup_idx_temp_vec_6 ? 6'h6 : _ldq_wakeup_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_49 = ldq_wakeup_idx_temp_vec_5 ? 6'h5 : _ldq_wakeup_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_50 = ldq_wakeup_idx_temp_vec_4 ? 6'h4 : _ldq_wakeup_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_51 = ldq_wakeup_idx_temp_vec_3 ? 6'h3 : _ldq_wakeup_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_52 = ldq_wakeup_idx_temp_vec_2 ? 6'h2 : _ldq_wakeup_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_53 = ldq_wakeup_idx_temp_vec_1 ? 6'h1 : _ldq_wakeup_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 6'h0 : _ldq_wakeup_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_T_192 = ldq_wakeup_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] ldq_wakeup_idx; // @[lsu.scala:429:31] wire [4:0] _ldq_wakeup_e_T = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [4:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [4:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:429:31] wire [4:0] _ldq_wakeup_e_T_1 = _ldq_wakeup_e_T; wire _can_fire_load_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:383:25, :440:63] wire can_fire_load_incoming_0 = _can_fire_load_incoming_T; // @[lsu.scala:263:49, :440:63] wire _will_fire_load_incoming_0_will_fire_T_3 = can_fire_load_incoming_0; // @[lsu.scala:263:49, :533:32] wire _GEN_240 = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :443:63] wire _can_fire_stad_incoming_T; // @[lsu.scala:443:63] assign _can_fire_stad_incoming_T = _GEN_240; // @[lsu.scala:443:63] wire _can_fire_sta_incoming_T; // @[lsu.scala:447:63] assign _can_fire_sta_incoming_T = _GEN_240; // @[lsu.scala:443:63, :447:63] wire _can_fire_stad_incoming_T_1 = _can_fire_stad_incoming_T & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :443:63, :444:63] wire can_fire_stad_incoming_0 = _can_fire_stad_incoming_T_1; // @[lsu.scala:263:49, :444:63] wire _can_fire_sta_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :448:66] wire _can_fire_sta_incoming_T_2 = _can_fire_sta_incoming_T & _can_fire_sta_incoming_T_1; // @[lsu.scala:447:63, :448:{63,66}] wire can_fire_sta_incoming_0 = _can_fire_sta_incoming_T_2; // @[lsu.scala:263:49, :448:63] wire _can_fire_std_incoming_T = exe_req_0_valid & exe_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:383:25, :451:63] wire _can_fire_std_incoming_T_1 = ~exe_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:383:25, :452:66] wire _can_fire_std_incoming_T_2 = _can_fire_std_incoming_T & _can_fire_std_incoming_T_1; // @[lsu.scala:451:63, :452:{63,66}] wire can_fire_std_incoming_0 = _can_fire_std_incoming_T_2; // @[lsu.scala:263:49, :452:63] wire _will_fire_std_incoming_0_will_fire_T_3 = can_fire_std_incoming_0; // @[lsu.scala:263:49, :533:32] wire _can_fire_sfence_T = exe_req_0_valid & exe_req_0_bits_sfence_valid; // @[lsu.scala:383:25, :455:63] wire can_fire_sfence_0 = _can_fire_sfence_T; // @[lsu.scala:263:49, :455:63] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:263:49, :459:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:263:49, :533:32] wire [6:0] mem_ldq_retry_e_out_bits_uop_uopc = _GEN_101[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = _GEN_102[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = _GEN_103[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = _GEN_104[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = _GEN_105[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iq_type = _GEN_106[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_retry_e_out_bits_uop_fu_code = _GEN_107[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_ctrl_br_type = _GEN_108[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_109[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_110[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_111[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_112[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_113[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_114[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_load = _GEN_115[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_116[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ctrl_is_std = _GEN_117[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_iw_state = _GEN_118[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_119[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_120[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_br = _GEN_121[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jalr = _GEN_122[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_jal = _GEN_123[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = _GEN_124[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = _GEN_126[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = _GEN_127[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = _GEN_128[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = _GEN_129[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_taken = _GEN_130[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = _GEN_131[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_retry_e_out_bits_uop_csr_addr = _GEN_132[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_rob_idx = _GEN_133[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = _GEN_134[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_135[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = _GEN_136[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = _GEN_137[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = _GEN_138[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = _GEN_139[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = _GEN_140[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = _GEN_141[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = _GEN_142[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = _GEN_143[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = _GEN_144[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_exception = _GEN_145[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = _GEN_146[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bypassable = _GEN_147[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = _GEN_148[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_149[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = _GEN_150[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = _GEN_151[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = _GEN_152[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = _GEN_153[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = _GEN_154[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = _GEN_155[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_156[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = _GEN_157[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = _GEN_158[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_159[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = _GEN_160[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = _GEN_161[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = _GEN_162[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = _GEN_163[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_ldst_val = _GEN_164[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = _GEN_165[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = _GEN_166[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = _GEN_167[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = _GEN_168[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = _GEN_169[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_fp_single = _GEN_170[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_171[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_172[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_173[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = _GEN_174[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_175[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = _GEN_176[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = _GEN_177[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_valid = _GEN_178[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = _GEN_179[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = _GEN_180[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = _GEN_181[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_executed = _GEN_182[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_succeeded = _GEN_183[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_order_fail = _GEN_184[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_observed = _GEN_185[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [23:0] mem_ldq_retry_e_out_bits_st_dep_mask = _GEN_186[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_youngest_stq_idx = _GEN_187[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire mem_ldq_retry_e_out_bits_forward_std_val = _GEN_188[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_retry_e_out_bits_forward_stq_idx = _GEN_189[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = _GEN_190[_ldq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_retry_T = _GEN_94[_ldq_retry_e_T_1] & mem_ldq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_retry_T_1 = _can_fire_load_retry_T & mem_ldq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire [4:0] _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; wire [31:0] _GEN_241 = {{p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_23}, {p1_block_load_mask_22}, {p1_block_load_mask_21}, {p1_block_load_mask_20}, {p1_block_load_mask_19}, {p1_block_load_mask_18}, {p1_block_load_mask_17}, {p1_block_load_mask_16}, {p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:397:35, :467:33] wire _can_fire_load_retry_T_4 = ~_GEN_241[_can_fire_load_retry_T_3]; // @[lsu.scala:467:33] wire _can_fire_load_retry_T_5 = _can_fire_load_retry_T_1 & _can_fire_load_retry_T_4; // @[lsu.scala:465:79, :466:79, :467:33] wire [4:0] _can_fire_load_retry_T_7 = _can_fire_load_retry_T_6; wire [31:0] _GEN_242 = {{p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_23}, {p2_block_load_mask_22}, {p2_block_load_mask_21}, {p2_block_load_mask_20}, {p2_block_load_mask_19}, {p2_block_load_mask_18}, {p2_block_load_mask_17}, {p2_block_load_mask_16}, {p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:398:35, :468:33] wire _can_fire_load_retry_T_8 = ~_GEN_242[_can_fire_load_retry_T_7]; // @[lsu.scala:468:33] wire _can_fire_load_retry_T_9 = _can_fire_load_retry_T_5 & _can_fire_load_retry_T_8; // @[lsu.scala:466:79, :467:79, :468:33] reg can_fire_load_retry_REG; // @[lsu.scala:469:40] wire _can_fire_load_retry_T_10 = _can_fire_load_retry_T_9 & can_fire_load_retry_REG; // @[lsu.scala:467:79, :468:79, :469:40] wire _can_fire_load_retry_T_11 = ~store_needs_order; // @[lsu.scala:406:35, :470:33] wire _can_fire_load_retry_T_12 = _can_fire_load_retry_T_10 & _can_fire_load_retry_T_11; // @[lsu.scala:468:79, :469:79, :470:33] wire _can_fire_load_retry_T_13 = _can_fire_load_retry_T_12; // @[lsu.scala:469:79, :470:79] wire _can_fire_load_retry_T_14 = ~mem_ldq_retry_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_retry_T_15 = _can_fire_load_retry_T_13 & _can_fire_load_retry_T_14; // @[lsu.scala:470:79, :471:79, :472:33] wire can_fire_load_retry_0 = _can_fire_load_retry_T_15; // @[lsu.scala:263:49, :471:79] wire [6:0] mem_stq_retry_e_out_bits_uop_uopc = _GEN_1[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = _GEN_2[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = _GEN_3[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = _GEN_4[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = _GEN_5[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iq_type = _GEN_6[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_stq_retry_e_out_bits_uop_fu_code = _GEN_7[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_ctrl_br_type = _GEN_8[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_ctrl_op1_sel = _GEN_9[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_op2_sel = _GEN_10[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_imm_sel = _GEN_11[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ctrl_op_fcn = _GEN_12[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw = _GEN_13[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd = _GEN_14[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_load = _GEN_15[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_sta = _GEN_16[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ctrl_is_std = _GEN_17[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_iw_state = _GEN_18[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_poisoned = _GEN_19[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_poisoned = _GEN_20[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_br = _GEN_21[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jalr = _GEN_22[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_jal = _GEN_23[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = _GEN_24[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = _GEN_26[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = _GEN_27[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = _GEN_28[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = _GEN_29[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_taken = _GEN_30[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = _GEN_31[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_stq_retry_e_out_bits_uop_csr_addr = _GEN_32[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_33[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ldq_idx = _GEN_34[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_35[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = _GEN_36[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = _GEN_37[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = _GEN_38[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = _GEN_39[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = _GEN_40[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = _GEN_41[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = _GEN_42[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = _GEN_43[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = _GEN_44[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = _GEN_45[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = _GEN_46[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_exception = _GEN_47[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = _GEN_49[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bypassable = _GEN_50[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = _GEN_51[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_52[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = _GEN_53[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fence = _GEN_54[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = _GEN_56[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_57[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = _GEN_59[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = _GEN_60[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = _GEN_61[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_is_unique = _GEN_62[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = _GEN_63[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = _GEN_64[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = _GEN_65[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = _GEN_66[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = _GEN_67[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = _GEN_68[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_ldst_val = _GEN_69[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = _GEN_70[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = _GEN_71[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = _GEN_72[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = _GEN_73[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_val = _GEN_74[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_fp_single = _GEN_75[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = _GEN_76[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = _GEN_77[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = _GEN_78[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = _GEN_79[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = _GEN_80[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = _GEN_81[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = _GEN_82[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_valid = _GEN_83[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = _GEN_84[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = _GEN_85[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_data_valid = _GEN_86[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = _GEN_87[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_committed = _GEN_89[_stq_retry_e_T_1]; // @[util.scala:106:23] wire mem_stq_retry_e_out_bits_succeeded = _GEN_191[_stq_retry_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = _GEN_192[_stq_retry_e_T_1]; // @[util.scala:106:23] wire _can_fire_sta_retry_T = _GEN[_stq_retry_e_T_1] & mem_stq_retry_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_sta_retry_T_1 = _can_fire_sta_retry_T & mem_stq_retry_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_sta_retry_T_2 = _can_fire_sta_retry_T_1; // @[lsu.scala:478:79, :479:79] reg can_fire_sta_retry_REG; // @[lsu.scala:481:41] wire _can_fire_sta_retry_T_3 = _can_fire_sta_retry_T_2 & can_fire_sta_retry_REG; // @[lsu.scala:479:79, :480:79, :481:41] wire _can_fire_sta_retry_T_8 = _can_fire_sta_retry_T_3; // @[lsu.scala:480:79, :481:79] wire _can_fire_sta_retry_T_5 = stq_incoming_idx_0 == stq_retry_idx; // @[lsu.scala:263:49, :421:30, :484:70] wire can_fire_sta_retry_0 = _can_fire_sta_retry_T_8; // @[lsu.scala:263:49, :481:79] wire _can_fire_store_commit_T = ~_GEN_55; // @[lsu.scala:222:42, :489:33] wire _can_fire_store_commit_T_1 = _GEN_0 & _can_fire_store_commit_T; // @[lsu.scala:222:42, :488:79, :489:33] wire _can_fire_store_commit_T_2 = ~mem_xcpt_valid; // @[lsu.scala:358:29, :490:33] wire _can_fire_store_commit_T_3 = _can_fire_store_commit_T_1 & _can_fire_store_commit_T_2; // @[lsu.scala:488:79, :489:79, :490:33] wire _can_fire_store_commit_T_4 = ~_GEN_48; // @[lsu.scala:222:42, :491:33] wire _can_fire_store_commit_T_5 = _can_fire_store_commit_T_3 & _can_fire_store_commit_T_4; // @[lsu.scala:489:79, :490:79, :491:33] wire _can_fire_store_commit_T_6 = _can_fire_store_commit_T_5; // @[lsu.scala:490:79, :491:79] wire _can_fire_store_commit_T_7 = _GEN_58 & _GEN_83[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :493:101] wire _can_fire_store_commit_T_8 = ~_GEN_85[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :495:66] wire _can_fire_store_commit_T_9 = _can_fire_store_commit_T_7 & _can_fire_store_commit_T_8; // @[lsu.scala:493:101, :494:101, :495:66] wire _can_fire_store_commit_T_10 = _can_fire_store_commit_T_9 & _GEN_86[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :494:101, :495:101] wire _can_fire_store_commit_T_11 = _GEN_89[stq_execute_head] | _can_fire_store_commit_T_10; // @[lsu.scala:218:29, :222:42, :493:62, :495:101] wire _can_fire_store_commit_T_12 = _can_fire_store_commit_T_6 & _can_fire_store_commit_T_11; // @[lsu.scala:491:79, :492:79, :493:62] wire can_fire_store_commit_0 = _can_fire_store_commit_T_12; // @[lsu.scala:263:49, :492:79] wire _will_fire_store_commit_0_will_fire_T_3 = can_fire_store_commit_0; // @[lsu.scala:263:49, :533:32] wire block_load_wakeup; // @[lsu.scala:499:35] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_uopc = _GEN_101[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = _GEN_102[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = _GEN_103[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = _GEN_104[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = _GEN_105[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iq_type = _GEN_106[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [9:0] mem_ldq_wakeup_e_out_bits_uop_fu_code = _GEN_107[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type = _GEN_108[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel = _GEN_109[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel = _GEN_110[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel = _GEN_111[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn = _GEN_112[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw = _GEN_113[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd = _GEN_114[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load = _GEN_115[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta = _GEN_116[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std = _GEN_117[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_iw_state = _GEN_118[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned = _GEN_119[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned = _GEN_120[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_br = _GEN_121[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jalr = _GEN_122[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_jal = _GEN_123[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = _GEN_124[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = _GEN_126[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = _GEN_127[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = _GEN_128[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = _GEN_129[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = _GEN_130[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = _GEN_131[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [11:0] mem_ldq_wakeup_e_out_bits_uop_csr_addr = _GEN_132[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = _GEN_133[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = _GEN_134[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_135[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = _GEN_136[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = _GEN_137[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = _GEN_138[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = _GEN_139[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = _GEN_140[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = _GEN_141[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = _GEN_142[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = _GEN_143[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = _GEN_144[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = _GEN_145[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = _GEN_146[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bypassable = _GEN_147[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = _GEN_148[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_149[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = _GEN_150[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = _GEN_151[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = _GEN_152[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = _GEN_153[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = _GEN_154[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = _GEN_155[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = _GEN_156[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = _GEN_157[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = _GEN_158[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = _GEN_159[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = _GEN_160[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = _GEN_161[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = _GEN_162[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = _GEN_163[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_val = _GEN_164[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = _GEN_165[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = _GEN_166[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = _GEN_167[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = _GEN_168[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = _GEN_169[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_single = _GEN_170[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = _GEN_171[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = _GEN_172[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = _GEN_173[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = _GEN_174[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = _GEN_175[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = _GEN_176[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = _GEN_177[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = _GEN_178[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = _GEN_179[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = _GEN_180[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = _GEN_181[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_executed = _GEN_182[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_succeeded = _GEN_183[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_order_fail = _GEN_184[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_observed = _GEN_185[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [23:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_186[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_youngest_stq_idx = _GEN_187[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = _GEN_188[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [4:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = _GEN_189[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = _GEN_190[_ldq_wakeup_e_T_1]; // @[util.scala:106:23] wire _can_fire_load_wakeup_T = _GEN_94[_ldq_wakeup_e_T_1] & mem_ldq_wakeup_e_out_bits_addr_valid; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_1 = ~mem_ldq_wakeup_e_out_bits_succeeded; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:501:88, :502:88, :503:31] wire _can_fire_load_wakeup_T_3 = ~mem_ldq_wakeup_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:502:88, :503:88, :504:31] wire _can_fire_load_wakeup_T_5 = ~mem_ldq_wakeup_e_out_bits_executed; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:503:88, :504:88, :505:31] wire _can_fire_load_wakeup_T_7 = ~mem_ldq_wakeup_e_out_bits_order_fail; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:504:88, :505:88, :506:31] wire [4:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire _can_fire_load_wakeup_T_11 = ~_GEN_241[_can_fire_load_wakeup_T_10]; // @[lsu.scala:467:33, :507:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:505:88, :506:88, :507:31] wire [4:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire _can_fire_load_wakeup_T_15 = ~_GEN_242[_can_fire_load_wakeup_T_14]; // @[lsu.scala:468:33, :508:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:506:88, :507:88, :508:31] wire _can_fire_load_wakeup_T_17 = ~store_needs_order; // @[lsu.scala:406:35, :470:33, :509:31] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:507:88, :508:88, :509:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:499:35, :510:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:508:88, :509:88, :510:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:509:88, :510:88] wire _can_fire_load_wakeup_T_22 = ~mem_ldq_wakeup_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:213:29, :429:31, :513:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:201:7, :512:107, :513:84] wire _can_fire_load_wakeup_T_25 = mem_ldq_wakeup_e_out_bits_st_dep_mask == 24'h0; // @[util.scala:106:23] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:512:107, :513:103, :514:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 | _can_fire_load_wakeup_T_26; // @[lsu.scala:512:{32,71}, :513:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:510:88, :511:88, :512:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:263:49, :511:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:263:49, :533:32] wire can_fire_hella_incoming_0; // @[lsu.scala:517:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:520:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:520:42, :533:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:575:25] wire exe_tlb_valid_0; // @[lsu.scala:525:27] wire _will_fire_load_incoming_0_will_fire_T_7 = _will_fire_load_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_load_incoming_0_will_fire_T_11 = _will_fire_load_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] assign will_fire_load_incoming_0_will_fire = _will_fire_load_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_load_incoming_0 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:370:38, :535:61] wire _will_fire_load_incoming_0_T = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_incoming_0_T_3 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_incoming_0_T_6 = will_fire_load_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_incoming_0_T_1 = ~_will_fire_load_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_incoming_0_T_2 = _will_fire_load_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_incoming_0_T_4 = ~_will_fire_load_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_incoming_0_T_5 = _will_fire_load_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_incoming_0_T_7 = ~_will_fire_load_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_incoming_0_T_8 = _will_fire_load_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_stad_incoming_0_T_8 = _will_fire_load_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_will_fire_T = ~_will_fire_load_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_stad_incoming_0_will_fire_T_1 = _will_fire_stad_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_stad_incoming_0_will_fire_T_2 = ~_will_fire_stad_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_stad_incoming_0_will_fire_T_3 = can_fire_stad_incoming_0 & _will_fire_stad_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_stad_incoming_0_will_fire_T_4 = ~_will_fire_load_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_stad_incoming_0_will_fire_T_5 = _will_fire_stad_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_stad_incoming_0_will_fire_T_6 = ~_will_fire_stad_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_stad_incoming_0_will_fire_T_7 = _will_fire_stad_incoming_0_will_fire_T_3 & _will_fire_stad_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_stad_incoming_0_will_fire_T_11 = _will_fire_stad_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_stad_incoming_0_will_fire_T_8 = ~_will_fire_load_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_stad_incoming_0_will_fire = _will_fire_stad_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] assign will_fire_stad_incoming_0 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:371:38, :535:61] wire _will_fire_stad_incoming_0_T = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_stad_incoming_0_T_3 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_stad_incoming_0_T_9 = will_fire_stad_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_stad_incoming_0_T_1 = ~_will_fire_stad_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_stad_incoming_0_T_2 = _will_fire_load_incoming_0_T_2 & _will_fire_stad_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_stad_incoming_0_T_4 = ~_will_fire_stad_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_stad_incoming_0_T_5 = _will_fire_load_incoming_0_T_5 & _will_fire_stad_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_incoming_0_T_8 = _will_fire_stad_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_stad_incoming_0_T_10 = ~_will_fire_stad_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_stad_incoming_0_T_11 = _will_fire_stad_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sta_incoming_0_will_fire_T = ~_will_fire_stad_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_incoming_0_will_fire_T_1 = _will_fire_sta_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_2 = ~_will_fire_sta_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_incoming_0_will_fire_T_3 = can_fire_sta_incoming_0 & _will_fire_sta_incoming_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_incoming_0_will_fire_T_4 = ~_will_fire_stad_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_incoming_0_will_fire_T_5 = _will_fire_sta_incoming_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_incoming_0_will_fire_T_6 = ~_will_fire_sta_incoming_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_incoming_0_will_fire_T_7 = _will_fire_sta_incoming_0_will_fire_T_3 & _will_fire_sta_incoming_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_incoming_0_will_fire_T_11 = _will_fire_sta_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_incoming_0_will_fire_T_8 = ~_will_fire_stad_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_incoming_0_will_fire_T_12 = ~_will_fire_stad_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_incoming_0_will_fire_T_13 = _will_fire_sta_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_incoming_0_will_fire_T_14 = ~_will_fire_sta_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_incoming_0_will_fire = _will_fire_sta_incoming_0_will_fire_T_11 & _will_fire_sta_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_incoming_0 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:372:38, :535:61] wire _will_fire_sta_incoming_0_T = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_incoming_0_T_3 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_incoming_0_T_9 = will_fire_sta_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_incoming_0_T_1 = ~_will_fire_sta_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_incoming_0_T_2 = _will_fire_stad_incoming_0_T_2 & _will_fire_sta_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_std_incoming_0_T_2 = _will_fire_sta_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_incoming_0_T_4 = ~_will_fire_sta_incoming_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_incoming_0_T_5 = _will_fire_stad_incoming_0_T_5 & _will_fire_sta_incoming_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_std_incoming_0_T_5 = _will_fire_sta_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_std_incoming_0_T_8 = _will_fire_sta_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_incoming_0_T_10 = ~_will_fire_sta_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_incoming_0_T_11 = _will_fire_stad_incoming_0_T_11 & _will_fire_sta_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_std_incoming_0_will_fire_T = ~_will_fire_sta_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_std_incoming_0_will_fire_T_7 = _will_fire_std_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_std_incoming_0_will_fire_T_4 = ~_will_fire_sta_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_std_incoming_0_will_fire_T_11 = _will_fire_std_incoming_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_std_incoming_0_will_fire_T_8 = ~_will_fire_sta_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_std_incoming_0_will_fire_T_12 = ~_will_fire_sta_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_std_incoming_0_will_fire_T_13 = _will_fire_std_incoming_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_std_incoming_0_will_fire_T_14 = ~_will_fire_std_incoming_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_std_incoming_0_will_fire = _will_fire_std_incoming_0_will_fire_T_11 & _will_fire_std_incoming_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_std_incoming_0 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:373:38, :535:61] wire _will_fire_std_incoming_0_T_9 = will_fire_std_incoming_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_5 = _will_fire_std_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_sfence_0_T_8 = _will_fire_std_incoming_0_T_8; // @[lsu.scala:539:31] wire _will_fire_std_incoming_0_T_10 = ~_will_fire_std_incoming_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_std_incoming_0_T_11 = _will_fire_sta_incoming_0_T_11 & _will_fire_std_incoming_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_sfence_0_will_fire_T = ~_will_fire_std_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sfence_0_will_fire_T_1 = _will_fire_sfence_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sfence_0_will_fire_T_2 = ~_will_fire_sfence_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0 & _will_fire_sfence_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_sfence_0_will_fire_T_4 = ~_will_fire_std_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sfence_0_will_fire_T_11 = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sfence_0_will_fire_T_8 = ~_will_fire_std_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sfence_0_will_fire_T_12 = ~_will_fire_std_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sfence_0_will_fire_T_13 = _will_fire_sfence_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sfence_0_will_fire_T_14 = ~_will_fire_sfence_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_11 & _will_fire_sfence_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:374:38, :535:61] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sfence_0_T_9 = will_fire_sfence_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_std_incoming_0_T_2 & _will_fire_sfence_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:537:31] wire _will_fire_release_0_T_8 = _will_fire_sfence_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sfence_0_T_10 = ~_will_fire_sfence_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sfence_0_T_11 = _will_fire_std_incoming_0_T_11 & _will_fire_sfence_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_release_0_T_11 = _will_fire_sfence_0_T_11; // @[lsu.scala:540:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_sfence_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_release_0_will_fire_T_11 = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_sfence_0_T_8; // @[lsu.scala:535:50, :539:31] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_release_0_will_fire_T_12 = ~_will_fire_sfence_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:377:38, :535:61] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_sfence_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_11 = _will_fire_release_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:517:42, :533:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_incoming_0_will_fire_T_11 = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_incoming_0_will_fire_T_12 = ~_will_fire_release_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:375:38, :535:61] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:537:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:538:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_hella_wakeup_0_T_11 = _will_fire_hella_incoming_0_T_11; // @[lsu.scala:540:31] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_hella_wakeup_0_will_fire_T_11 = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_hella_wakeup_0_will_fire_T_12 = ~_will_fire_hella_incoming_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:376:38, :535:61] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_load_retry_0_T_11 = _will_fire_hella_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_retry_0_will_fire_T_11 = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_retry_0_will_fire_T_12 = ~_will_fire_hella_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:378:38, :535:61] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_sta_retry_0_T_8 = _will_fire_load_retry_0_T_8; // @[lsu.scala:539:31] wire _will_fire_sta_retry_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_sta_retry_0_will_fire_T_1 = _will_fire_sta_retry_0_will_fire_T; // @[lsu.scala:533:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_2 = ~_will_fire_sta_retry_0_will_fire_T_1; // @[lsu.scala:533:{35,48}] wire _will_fire_sta_retry_0_will_fire_T_3 = can_fire_sta_retry_0 & _will_fire_sta_retry_0_will_fire_T_2; // @[lsu.scala:263:49, :533:{32,35}] wire _will_fire_sta_retry_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_sta_retry_0_will_fire_T_5 = _will_fire_sta_retry_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_sta_retry_0_will_fire_T_6 = ~_will_fire_sta_retry_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_sta_retry_0_will_fire_T_7 = _will_fire_sta_retry_0_will_fire_T_3 & _will_fire_sta_retry_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_sta_retry_0_will_fire_T_11 = _will_fire_sta_retry_0_will_fire_T_7; // @[lsu.scala:533:63, :534:65] wire _will_fire_sta_retry_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_sta_retry_0_will_fire_T_12 = ~_will_fire_load_retry_0_T_11; // @[lsu.scala:536:51, :540:31] wire _will_fire_sta_retry_0_will_fire_T_13 = _will_fire_sta_retry_0_will_fire_T_12; // @[lsu.scala:536:{48,51}] wire _will_fire_sta_retry_0_will_fire_T_14 = ~_will_fire_sta_retry_0_will_fire_T_13; // @[lsu.scala:536:{35,48}] assign will_fire_sta_retry_0_will_fire = _will_fire_sta_retry_0_will_fire_T_11 & _will_fire_sta_retry_0_will_fire_T_14; // @[lsu.scala:534:65, :535:61, :536:35] assign will_fire_sta_retry_0 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:379:38, :535:61] wire _will_fire_sta_retry_0_T = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :537:46] wire _will_fire_sta_retry_0_T_3 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_sta_retry_0_T_9 = will_fire_sta_retry_0_will_fire; // @[lsu.scala:535:61, :540:46] wire _will_fire_sta_retry_0_T_1 = ~_will_fire_sta_retry_0_T; // @[lsu.scala:537:{34,46}] wire _will_fire_sta_retry_0_T_2 = _will_fire_load_retry_0_T_2 & _will_fire_sta_retry_0_T_1; // @[lsu.scala:537:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_sta_retry_0_T_2; // @[lsu.scala:537:31] wire _will_fire_sta_retry_0_T_4 = ~_will_fire_sta_retry_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_sta_retry_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_sta_retry_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_sta_retry_0_T_10 = ~_will_fire_sta_retry_0_T_9; // @[lsu.scala:540:{34,46}] wire _will_fire_sta_retry_0_T_11 = _will_fire_load_retry_0_T_11 & _will_fire_sta_retry_0_T_10; // @[lsu.scala:540:{31,34}] wire _will_fire_load_wakeup_0_T_11 = _will_fire_sta_retry_0_T_11; // @[lsu.scala:540:31] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_sta_retry_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_sta_retry_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:534:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:534:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:533:{32,63}, :534:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_sta_retry_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_load_wakeup_0_will_fire_T_11 = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_load_wakeup_0_will_fire_T_12 = ~_will_fire_sta_retry_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:381:38, :535:61] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :538:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:537:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:538:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_sta_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:538:{31,34}] wire _will_fire_store_commit_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:538:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_sta_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:539:{31,34}] wire _will_fire_store_commit_0_T_11 = _will_fire_load_wakeup_0_T_11; // @[lsu.scala:540:31] wire _will_fire_store_commit_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:533:51, :537:31] wire _will_fire_store_commit_0_will_fire_T_7 = _will_fire_store_commit_0_will_fire_T_3; // @[lsu.scala:533:{32,63}] wire _will_fire_store_commit_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:534:52, :538:31] wire _will_fire_store_commit_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:535:50, :539:31] wire _will_fire_store_commit_0_will_fire_T_9 = _will_fire_store_commit_0_will_fire_T_8; // @[lsu.scala:535:{47,50}] wire _will_fire_store_commit_0_will_fire_T_10 = ~_will_fire_store_commit_0_will_fire_T_9; // @[lsu.scala:535:{35,47}] wire _will_fire_store_commit_0_will_fire_T_11 = _will_fire_store_commit_0_will_fire_T_7 & _will_fire_store_commit_0_will_fire_T_10; // @[lsu.scala:533:63, :534:65, :535:35] assign will_fire_store_commit_0_will_fire = _will_fire_store_commit_0_will_fire_T_11; // @[lsu.scala:534:65, :535:61] wire _will_fire_store_commit_0_will_fire_T_12 = ~_will_fire_load_wakeup_0_T_11; // @[lsu.scala:536:51, :540:31] assign will_fire_store_commit_0 = will_fire_store_commit_0_will_fire; // @[lsu.scala:380:38, :535:61] wire _will_fire_store_commit_0_T_6 = will_fire_store_commit_0_will_fire; // @[lsu.scala:535:61, :539:46] wire _will_fire_store_commit_0_T_7 = ~_will_fire_store_commit_0_T_6; // @[lsu.scala:539:{34,46}] wire _will_fire_store_commit_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_0_T_7; // @[lsu.scala:539:{31,34}] wire _T_189 = will_fire_load_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:370:38, :371:38, :566:63] wire _exe_tlb_uop_T; // @[lsu.scala:596:53] assign _exe_tlb_uop_T = _T_189; // @[lsu.scala:566:63, :596:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:606:53] assign _exe_tlb_vaddr_T = _T_189; // @[lsu.scala:566:63, :606:53] wire _exe_size_T; // @[lsu.scala:623:52] assign _exe_size_T = _T_189; // @[lsu.scala:566:63, :623:52] wire _exe_cmd_T; // @[lsu.scala:632:52] assign _exe_cmd_T = _T_189; // @[lsu.scala:566:63, :632:52] wire _GEN_243 = ldq_wakeup_idx == 5'h0; // @[lsu.scala:429:31, :569:49] wire _GEN_244 = ldq_wakeup_idx == 5'h1; // @[lsu.scala:429:31, :569:49] wire _GEN_245 = ldq_wakeup_idx == 5'h2; // @[lsu.scala:429:31, :569:49] wire _GEN_246 = ldq_wakeup_idx == 5'h3; // @[lsu.scala:429:31, :569:49] wire _GEN_247 = ldq_wakeup_idx == 5'h4; // @[lsu.scala:429:31, :569:49] wire _GEN_248 = ldq_wakeup_idx == 5'h5; // @[lsu.scala:429:31, :569:49] wire _GEN_249 = ldq_wakeup_idx == 5'h6; // @[lsu.scala:429:31, :569:49] wire _GEN_250 = ldq_wakeup_idx == 5'h7; // @[lsu.scala:429:31, :569:49] wire _GEN_251 = ldq_wakeup_idx == 5'h8; // @[lsu.scala:429:31, :569:49] wire _GEN_252 = ldq_wakeup_idx == 5'h9; // @[lsu.scala:429:31, :569:49] wire _GEN_253 = ldq_wakeup_idx == 5'hA; // @[lsu.scala:429:31, :569:49] wire _GEN_254 = ldq_wakeup_idx == 5'hB; // @[lsu.scala:429:31, :569:49] wire _GEN_255 = ldq_wakeup_idx == 5'hC; // @[lsu.scala:429:31, :569:49] wire _GEN_256 = ldq_wakeup_idx == 5'hD; // @[lsu.scala:429:31, :569:49] wire _GEN_257 = ldq_wakeup_idx == 5'hE; // @[lsu.scala:429:31, :569:49] wire _GEN_258 = ldq_wakeup_idx == 5'hF; // @[lsu.scala:429:31, :569:49] wire _GEN_259 = ldq_wakeup_idx == 5'h10; // @[lsu.scala:429:31, :569:49] wire _GEN_260 = ldq_wakeup_idx == 5'h11; // @[lsu.scala:429:31, :569:49] wire _GEN_261 = ldq_wakeup_idx == 5'h12; // @[lsu.scala:429:31, :569:49] wire _GEN_262 = ldq_wakeup_idx == 5'h13; // @[lsu.scala:429:31, :569:49] wire _GEN_263 = ldq_wakeup_idx == 5'h14; // @[lsu.scala:429:31, :569:49] wire _GEN_264 = ldq_wakeup_idx == 5'h15; // @[lsu.scala:429:31, :569:49] wire _GEN_265 = ldq_wakeup_idx == 5'h16; // @[lsu.scala:429:31, :569:49] wire _GEN_266 = ldq_wakeup_idx == 5'h17; // @[lsu.scala:429:31, :569:49] wire _GEN_267 = ldq_retry_idx == 5'h0; // @[lsu.scala:414:30, :573:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_243 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h0 : will_fire_load_retry_0 & _GEN_267; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_268 = ldq_retry_idx == 5'h1; // @[lsu.scala:414:30, :573:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_244 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h1 : will_fire_load_retry_0 & _GEN_268; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_269 = ldq_retry_idx == 5'h2; // @[lsu.scala:414:30, :573:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_245 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h2 : will_fire_load_retry_0 & _GEN_269; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_270 = ldq_retry_idx == 5'h3; // @[lsu.scala:414:30, :573:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_246 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h3 : will_fire_load_retry_0 & _GEN_270; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_271 = ldq_retry_idx == 5'h4; // @[lsu.scala:414:30, :573:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_247 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h4 : will_fire_load_retry_0 & _GEN_271; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_272 = ldq_retry_idx == 5'h5; // @[lsu.scala:414:30, :573:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_248 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h5 : will_fire_load_retry_0 & _GEN_272; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_273 = ldq_retry_idx == 5'h6; // @[lsu.scala:414:30, :573:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_249 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h6 : will_fire_load_retry_0 & _GEN_273; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_274 = ldq_retry_idx == 5'h7; // @[lsu.scala:414:30, :573:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_250 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h7 : will_fire_load_retry_0 & _GEN_274; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_275 = ldq_retry_idx == 5'h8; // @[lsu.scala:414:30, :573:49] assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_251 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h8 : will_fire_load_retry_0 & _GEN_275; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_276 = ldq_retry_idx == 5'h9; // @[lsu.scala:414:30, :573:49] assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_252 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h9 : will_fire_load_retry_0 & _GEN_276; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_277 = ldq_retry_idx == 5'hA; // @[lsu.scala:414:30, :573:49] assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_253 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hA : will_fire_load_retry_0 & _GEN_277; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_278 = ldq_retry_idx == 5'hB; // @[lsu.scala:414:30, :573:49] assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_254 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hB : will_fire_load_retry_0 & _GEN_278; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_279 = ldq_retry_idx == 5'hC; // @[lsu.scala:414:30, :573:49] assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_255 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hC : will_fire_load_retry_0 & _GEN_279; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_280 = ldq_retry_idx == 5'hD; // @[lsu.scala:414:30, :573:49] assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_256 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hD : will_fire_load_retry_0 & _GEN_280; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_281 = ldq_retry_idx == 5'hE; // @[lsu.scala:414:30, :573:49] assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_257 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hE : will_fire_load_retry_0 & _GEN_281; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_282 = ldq_retry_idx == 5'hF; // @[lsu.scala:414:30, :573:49] assign block_load_mask_15 = will_fire_load_wakeup_0 ? _GEN_258 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'hF : will_fire_load_retry_0 & _GEN_282; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_283 = ldq_retry_idx == 5'h10; // @[lsu.scala:414:30, :573:49] assign block_load_mask_16 = will_fire_load_wakeup_0 ? _GEN_259 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h10 : will_fire_load_retry_0 & _GEN_283; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_284 = ldq_retry_idx == 5'h11; // @[lsu.scala:414:30, :573:49] assign block_load_mask_17 = will_fire_load_wakeup_0 ? _GEN_260 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h11 : will_fire_load_retry_0 & _GEN_284; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_285 = ldq_retry_idx == 5'h12; // @[lsu.scala:414:30, :573:49] assign block_load_mask_18 = will_fire_load_wakeup_0 ? _GEN_261 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h12 : will_fire_load_retry_0 & _GEN_285; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_286 = ldq_retry_idx == 5'h13; // @[lsu.scala:414:30, :573:49] assign block_load_mask_19 = will_fire_load_wakeup_0 ? _GEN_262 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h13 : will_fire_load_retry_0 & _GEN_286; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_287 = ldq_retry_idx == 5'h14; // @[lsu.scala:414:30, :573:49] assign block_load_mask_20 = will_fire_load_wakeup_0 ? _GEN_263 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h14 : will_fire_load_retry_0 & _GEN_287; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_288 = ldq_retry_idx == 5'h15; // @[lsu.scala:414:30, :573:49] assign block_load_mask_21 = will_fire_load_wakeup_0 ? _GEN_264 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h15 : will_fire_load_retry_0 & _GEN_288; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_289 = ldq_retry_idx == 5'h16; // @[lsu.scala:414:30, :573:49] assign block_load_mask_22 = will_fire_load_wakeup_0 ? _GEN_265 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h16 : will_fire_load_retry_0 & _GEN_289; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] wire _GEN_290 = ldq_retry_idx == 5'h17; // @[lsu.scala:414:30, :573:49] assign block_load_mask_23 = will_fire_load_wakeup_0 ? _GEN_266 : will_fire_load_incoming_0 ? exe_req_0_bits_uop_ldq_idx == 5'h17 : will_fire_load_retry_0 & _GEN_290; // @[lsu.scala:370:38, :378:38, :381:38, :383:25, :396:36, :568:37, :569:49, :570:46, :571:52, :572:43, :573:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_0_T_2; // @[lsu.scala:537:31, :575:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:525:27, :575:25] wire _exe_tlb_uop_T_1 = _exe_tlb_uop_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :596:53, :597:53] wire _exe_tlb_uop_T_2 = _exe_tlb_uop_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :597:53, :598:53] wire [6:0] _exe_tlb_uop_T_4_uopc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_rvc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_iq_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_4_fu_code = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_4_ctrl_br_type = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_ctrl_op1_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_op2_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_imm_sel = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ctrl_op_fcn = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_fcn_dw = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_4_ctrl_csr_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_load = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_sta = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ctrl_is_std = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_iw_state = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p1_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_iw_p2_poisoned = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_br = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jalr = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_jal = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sfb = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [15:0] _exe_tlb_uop_T_4_br_mask = will_fire_sta_retry_0 ? _GEN_25[_stq_retry_e_T_1] : 16'h0; // @[lsu.scala:222:42, :379:38, :477:79, :601:24] wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_br_tag : 4'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ftq_idx : 5'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_edge_inst = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_taken = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_4_csr_addr = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_rob_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rob_idx : 7'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldq_idx : 5'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_stq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stq_idx : 5'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_pdst : 7'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs1 : 7'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs2 : 7'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_prs3 : 7'h0; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ppred : 5'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_stale_pdst : 7'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_exception = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bypassable = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_mem_signed = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fence = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_fencei = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_amo = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_uses_stq = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_is_unique = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_ldst_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_frs3_en = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_val = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_fp_single = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_sta_retry_0 & mem_stq_retry_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_uopc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uopc : _exe_tlb_uop_T_4_uopc; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[util.scala:106:23] wire [31:0] _exe_tlb_uop_T_5_debug_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_rvc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[util.scala:106:23] wire [39:0] _exe_tlb_uop_T_5_debug_pc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_iq_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iq_type : _exe_tlb_uop_T_4_iq_type; // @[util.scala:106:23] wire [9:0] _exe_tlb_uop_T_5_fu_code = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fu_code : _exe_tlb_uop_T_4_fu_code; // @[util.scala:106:23] wire [3:0] _exe_tlb_uop_T_5_ctrl_br_type = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_br_type : _exe_tlb_uop_T_4_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_ctrl_op1_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_4_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_op2_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_4_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_imm_sel = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_4_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ctrl_op_fcn = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_4_ctrl_op_fcn; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_fcn_dw = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_4_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _exe_tlb_uop_T_5_ctrl_csr_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_4_ctrl_csr_cmd; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_load = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_load : _exe_tlb_uop_T_4_ctrl_is_load; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_sta = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_4_ctrl_is_sta; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ctrl_is_std = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ctrl_is_std : _exe_tlb_uop_T_4_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_iw_state = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_state : _exe_tlb_uop_T_4_iw_state; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p1_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_4_iw_p1_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_iw_p2_poisoned = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_4_iw_p2_poisoned; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_br = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_br : _exe_tlb_uop_T_4_is_br; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jalr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jalr : _exe_tlb_uop_T_4_is_jalr; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_jal = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_jal : _exe_tlb_uop_T_4_is_jal; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sfb = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[util.scala:106:23] wire [15:0] _exe_tlb_uop_T_5_br_mask = will_fire_load_retry_0 ? _GEN_125[_ldq_retry_e_T_1] : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:263:49, :378:38, :464:79, :600:24, :601:24] wire [3:0] _exe_tlb_uop_T_5_br_tag = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ftq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_edge_inst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_pc_lob = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_taken = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[util.scala:106:23] wire [19:0] _exe_tlb_uop_T_5_imm_packed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[util.scala:106:23] wire [11:0] _exe_tlb_uop_T_5_csr_addr = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_csr_addr : _exe_tlb_uop_T_4_csr_addr; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_rob_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ldq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_stq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_prs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_prs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_5_prs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_ppred = will_fire_load_retry_0 ? 5'h0 : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:378:38, :600:24, :601:24] wire _exe_tlb_uop_T_5_prs1_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs2_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_prs3_busy = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ppred_busy = ~will_fire_load_retry_0 & _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:378:38, :600:24, :601:24] wire [6:0] _exe_tlb_uop_T_5_stale_pdst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_exception = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[util.scala:106:23] wire [63:0] _exe_tlb_uop_T_5_exc_cause = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bypassable = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bypassable : _exe_tlb_uop_T_4_bypassable; // @[util.scala:106:23] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_mem_size = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_mem_signed = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fence = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_fencei = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_amo = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_ldq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_uses_stq = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_sys_pc2epc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_is_unique = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_flush_on_commit = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_is_rs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_ldst = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs1 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs2 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[util.scala:106:23] wire [5:0] _exe_tlb_uop_T_5_lrs3 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_ldst_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_ldst_val : _exe_tlb_uop_T_4_ldst_val; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_frs3_en = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_val = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_fp_single = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_fp_single : _exe_tlb_uop_T_4_fp_single; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_pf_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ae_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_xcpt_ma_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_debug_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[util.scala:106:23] wire _exe_tlb_uop_T_5_bp_xcpt_if = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_fsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[util.scala:106:23] wire [1:0] _exe_tlb_uop_T_5_debug_tsrc = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[util.scala:106:23] wire [6:0] _exe_tlb_uop_T_6_uopc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uopc : _exe_tlb_uop_T_5_uopc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_inst : _exe_tlb_uop_T_5_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [31:0] _exe_tlb_uop_T_6_debug_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_inst : _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_rvc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_rvc : _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [39:0] _exe_tlb_uop_T_6_debug_pc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_pc : _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_iq_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iq_type : _exe_tlb_uop_T_5_iq_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [9:0] _exe_tlb_uop_T_6_fu_code = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fu_code : _exe_tlb_uop_T_5_fu_code; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_ctrl_br_type = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_br_type : _exe_tlb_uop_T_5_ctrl_br_type; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_ctrl_op1_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op1_sel : _exe_tlb_uop_T_5_ctrl_op1_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_op2_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op2_sel : _exe_tlb_uop_T_5_ctrl_op2_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_imm_sel = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_imm_sel : _exe_tlb_uop_T_5_ctrl_imm_sel; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ctrl_op_fcn = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_op_fcn : _exe_tlb_uop_T_5_ctrl_op_fcn; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_fcn_dw = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_fcn_dw : _exe_tlb_uop_T_5_ctrl_fcn_dw; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [2:0] _exe_tlb_uop_T_6_ctrl_csr_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_csr_cmd : _exe_tlb_uop_T_5_ctrl_csr_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_load = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_load : _exe_tlb_uop_T_5_ctrl_is_load; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_sta = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_sta : _exe_tlb_uop_T_5_ctrl_is_sta; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ctrl_is_std = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ctrl_is_std : _exe_tlb_uop_T_5_ctrl_is_std; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_iw_state = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_state : _exe_tlb_uop_T_5_iw_state; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p1_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p1_poisoned : _exe_tlb_uop_T_5_iw_p1_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_iw_p2_poisoned = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_iw_p2_poisoned : _exe_tlb_uop_T_5_iw_p2_poisoned; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_br = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_br : _exe_tlb_uop_T_5_is_br; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jalr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jalr : _exe_tlb_uop_T_5_is_jalr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_jal = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_jal : _exe_tlb_uop_T_5_is_jal; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sfb = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sfb : _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [15:0] _exe_tlb_uop_T_6_br_mask = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_mask : _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [3:0] _exe_tlb_uop_T_6_br_tag = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_br_tag : _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ftq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ftq_idx : _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_edge_inst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_edge_inst : _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_pc_lob = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pc_lob : _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_taken = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_taken : _exe_tlb_uop_T_5_taken; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [19:0] _exe_tlb_uop_T_6_imm_packed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_imm_packed : _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [11:0] _exe_tlb_uop_T_6_csr_addr = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_csr_addr : _exe_tlb_uop_T_5_csr_addr; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_rob_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rob_idx : _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ldq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldq_idx : _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_stq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stq_idx : _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_rxq_idx = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_rxq_idx : _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_pdst : _exe_tlb_uop_T_5_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_prs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1 : _exe_tlb_uop_T_5_prs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_prs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2 : _exe_tlb_uop_T_5_prs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_prs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3 : _exe_tlb_uop_T_5_prs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_ppred = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred : _exe_tlb_uop_T_5_ppred; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs1_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs1_busy : _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs2_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs2_busy : _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_prs3_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_prs3_busy : _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ppred_busy = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ppred_busy : _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] _exe_tlb_uop_T_6_stale_pdst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_stale_pdst : _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_exception = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exception : _exe_tlb_uop_T_5_exception; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [63:0] _exe_tlb_uop_T_6_exc_cause = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_exc_cause : _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bypassable = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bypassable : _exe_tlb_uop_T_5_bypassable; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [4:0] _exe_tlb_uop_T_6_mem_cmd = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_cmd : _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_mem_size = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_size : _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_mem_signed = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_mem_signed : _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fence = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fence : _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_fencei = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_fencei : _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_amo = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_amo : _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_ldq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_ldq : _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_uses_stq = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_uses_stq : _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_sys_pc2epc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_is_unique = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_is_unique : _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_flush_on_commit = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_is_rs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_ldst = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst : _exe_tlb_uop_T_5_ldst; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs1 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1 : _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs2 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2 : _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [5:0] _exe_tlb_uop_T_6_lrs3 = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs3 : _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_ldst_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_ldst_val : _exe_tlb_uop_T_5_ldst_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_dst_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_dst_rtype : _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs1_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_lrs2_rtype = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_frs3_en = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_frs3_en : _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_val = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_val : _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_fp_single = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_fp_single : _exe_tlb_uop_T_5_fp_single; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_pf_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ae_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_xcpt_ma_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_debug_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire _exe_tlb_uop_T_6_bp_xcpt_if = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_fsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [1:0] _exe_tlb_uop_T_6_debug_tsrc = _exe_tlb_uop_T_2 ? exe_req_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:383:25, :596:24, :598:53, :600:24] wire [6:0] exe_tlb_uop_0_uopc = _exe_tlb_uop_T_6_uopc; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_6_inst; // @[lsu.scala:263:49, :596:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_6_debug_inst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_6_is_rvc; // @[lsu.scala:263:49, :596:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_6_debug_pc; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_iq_type = _exe_tlb_uop_T_6_iq_type; // @[lsu.scala:263:49, :596:24] wire [9:0] exe_tlb_uop_0_fu_code = _exe_tlb_uop_T_6_fu_code; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_ctrl_br_type = _exe_tlb_uop_T_6_ctrl_br_type; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_ctrl_op1_sel = _exe_tlb_uop_T_6_ctrl_op1_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_op2_sel = _exe_tlb_uop_T_6_ctrl_op2_sel; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_imm_sel = _exe_tlb_uop_T_6_ctrl_imm_sel; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ctrl_op_fcn = _exe_tlb_uop_T_6_ctrl_op_fcn; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_fcn_dw = _exe_tlb_uop_T_6_ctrl_fcn_dw; // @[lsu.scala:263:49, :596:24] wire [2:0] exe_tlb_uop_0_ctrl_csr_cmd = _exe_tlb_uop_T_6_ctrl_csr_cmd; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_6_ctrl_is_load; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_6_ctrl_is_sta; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ctrl_is_std = _exe_tlb_uop_T_6_ctrl_is_std; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_iw_state = _exe_tlb_uop_T_6_iw_state; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p1_poisoned = _exe_tlb_uop_T_6_iw_p1_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_iw_p2_poisoned = _exe_tlb_uop_T_6_iw_p2_poisoned; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_br = _exe_tlb_uop_T_6_is_br; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jalr = _exe_tlb_uop_T_6_is_jalr; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_jal = _exe_tlb_uop_T_6_is_jal; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_6_is_sfb; // @[lsu.scala:263:49, :596:24] wire [15:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_6_br_mask; // @[lsu.scala:263:49, :596:24] wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_6_br_tag; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_6_ftq_idx; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_6_edge_inst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_6_pc_lob; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_6_taken; // @[lsu.scala:263:49, :596:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_6_imm_packed; // @[lsu.scala:263:49, :596:24] wire [11:0] exe_tlb_uop_0_csr_addr = _exe_tlb_uop_T_6_csr_addr; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_6_rob_idx; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_6_ldq_idx; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_6_stq_idx; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_6_rxq_idx; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_6_pdst; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_6_prs1; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_6_prs2; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_6_prs3; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_6_ppred; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_6_prs1_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_6_prs2_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_6_prs3_busy; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_6_ppred_busy; // @[lsu.scala:263:49, :596:24] wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_6_stale_pdst; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_6_exception; // @[lsu.scala:263:49, :596:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_6_exc_cause; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bypassable = _exe_tlb_uop_T_6_bypassable; // @[lsu.scala:263:49, :596:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_6_mem_cmd; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_6_mem_size; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_6_mem_signed; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_6_is_fence; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_6_is_fencei; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_6_is_amo; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_6_uses_ldq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_6_uses_stq; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_6_is_sys_pc2epc; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_6_is_unique; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_6_flush_on_commit; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_6_ldst_is_rs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_6_ldst; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_6_lrs1; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_6_lrs2; // @[lsu.scala:263:49, :596:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_6_lrs3; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_ldst_val = _exe_tlb_uop_T_6_ldst_val; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_6_dst_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_6_lrs1_rtype; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_6_lrs2_rtype; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_6_frs3_en; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_6_fp_val; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_fp_single = _exe_tlb_uop_T_6_fp_single; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_6_xcpt_pf_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_6_xcpt_ae_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_6_xcpt_ma_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_6_bp_debug_if; // @[lsu.scala:263:49, :596:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_6_bp_xcpt_if; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_6_debug_fsrc; // @[lsu.scala:263:49, :596:24] wire [1:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_6_debug_tsrc; // @[lsu.scala:263:49, :596:24] wire [6:0] mem_xcpt_uops_out_uopc = exe_tlb_uop_0_uopc; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:96:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:96:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_iq_type = exe_tlb_uop_0_iq_type; // @[util.scala:96:23] wire [9:0] mem_xcpt_uops_out_fu_code = exe_tlb_uop_0_fu_code; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_ctrl_br_type = exe_tlb_uop_0_ctrl_br_type; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_ctrl_op1_sel = exe_tlb_uop_0_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_op2_sel = exe_tlb_uop_0_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_imm_sel = exe_tlb_uop_0_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ctrl_op_fcn = exe_tlb_uop_0_ctrl_op_fcn; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_fcn_dw = exe_tlb_uop_0_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] mem_xcpt_uops_out_ctrl_csr_cmd = exe_tlb_uop_0_ctrl_csr_cmd; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_load = exe_tlb_uop_0_ctrl_is_load; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_sta = exe_tlb_uop_0_ctrl_is_sta; // @[util.scala:96:23] wire mem_xcpt_uops_out_ctrl_is_std = exe_tlb_uop_0_ctrl_is_std; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_iw_state = exe_tlb_uop_0_iw_state; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p1_poisoned = exe_tlb_uop_0_iw_p1_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_iw_p2_poisoned = exe_tlb_uop_0_iw_p2_poisoned; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_br = exe_tlb_uop_0_is_br; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jalr = exe_tlb_uop_0_is_jalr; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_jal = exe_tlb_uop_0_is_jal; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:96:23] wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:96:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:96:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:96:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:96:23] wire [11:0] mem_xcpt_uops_out_csr_addr = exe_tlb_uop_0_csr_addr; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:96:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:96:23] wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:96:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:96:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:96:23] wire mem_xcpt_uops_out_bypassable = exe_tlb_uop_0_bypassable; // @[util.scala:96:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:96:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:96:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:96:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:96:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:96:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:96:23] wire mem_xcpt_uops_out_ldst_val = exe_tlb_uop_0_ldst_val; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:96:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:96:23] wire mem_xcpt_uops_out_fp_single = exe_tlb_uop_0_fp_single; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:96:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:96:23] wire [1:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:96:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :606:53, :607:53] wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:241:34, :375:38, :612:24] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0 ? mem_stq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_2; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_4 = will_fire_load_retry_0 ? mem_ldq_retry_e_out_bits_addr_bits : _exe_tlb_vaddr_T_3; // @[util.scala:106:23] wire [39:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {1'h0, exe_req_0_bits_sfence_bits_addr} : _exe_tlb_vaddr_T_4; // @[lsu.scala:374:38, :383:25, :609:24, :610:24] wire [39:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? exe_req_0_bits_addr : _exe_tlb_vaddr_T_5; // @[lsu.scala:383:25, :606:24, :607:53, :609:24] wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:263:49, :606:24] wire exe_sfence_bits_rs1; // @[lsu.scala:615:28] wire exe_sfence_bits_rs2; // @[lsu.scala:615:28] wire [38:0] exe_sfence_bits_addr; // @[lsu.scala:615:28] wire exe_sfence_bits_asid; // @[lsu.scala:615:28] wire exe_sfence_valid; // @[lsu.scala:615:28] assign exe_sfence_valid = will_fire_sfence_0 & exe_req_0_bits_sfence_valid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs1 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs1; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_rs2 = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_rs2; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_addr = will_fire_sfence_0 ? exe_req_0_bits_sfence_bits_addr : 39'h0; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] assign exe_sfence_bits_asid = will_fire_sfence_0 & exe_req_0_bits_sfence_bits_asid; // @[lsu.scala:374:38, :383:25, :615:28, :617:32, :618:18] wire _exe_size_T_1 = _exe_size_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :623:52, :624:52] wire _exe_size_T_2 = _exe_size_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :624:52, :625:52] wire _exe_size_T_3 = _exe_size_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :625:52, :626:52] wire _exe_size_T_4 = _exe_size_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :626:52, :627:52] wire [1:0] _exe_size_T_5 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:375:38, :629:23] wire [1:0] _exe_size_T_6 = _exe_size_T_4 ? exe_tlb_uop_0_mem_size : _exe_size_T_5; // @[lsu.scala:263:49, :623:23, :627:52, :629:23] wire [1:0] exe_size_0 = _exe_size_T_6; // @[lsu.scala:263:49, :623:23] wire _exe_cmd_T_1 = _exe_cmd_T | will_fire_sta_incoming_0; // @[lsu.scala:372:38, :632:52, :633:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 | will_fire_sfence_0; // @[lsu.scala:374:38, :633:52, :634:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 | will_fire_load_retry_0; // @[lsu.scala:378:38, :634:52, :635:52] wire _exe_cmd_T_4 = _exe_cmd_T_3 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :635:52, :636:52] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_4 ? exe_tlb_uop_0_mem_cmd : 5'h0; // @[lsu.scala:263:49, :632:23, :636:52] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:263:49, :632:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:263:49, :642:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :375:38, :645:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:263:49, :645:23] wire _ma_ld_T = will_fire_load_incoming_0 & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:370:38, :383:25, :660:56] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:263:49, :660:56] wire _T_242 = will_fire_sta_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :372:38, :661:56] wire _ma_st_T; // @[lsu.scala:661:56] assign _ma_st_T = _T_242; // @[lsu.scala:661:56] wire _stq_idx_T; // @[lsu.scala:851:51] assign _stq_idx_T = _T_242; // @[lsu.scala:661:56, :851:51] wire _ma_st_T_1 = _ma_st_T & exe_req_0_bits_mxcpt_valid; // @[lsu.scala:383:25, :661:{56,87}] wire ma_st_0 = _ma_st_T_1; // @[lsu.scala:263:49, :661:87] wire _pf_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_ld; // @[lsu.scala:247:20, :525:27, :662:50] wire _pf_ld_T_1 = _pf_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :662:{50,75}] wire pf_ld_0 = _pf_ld_T_1; // @[lsu.scala:263:49, :662:75] wire _pf_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_pf_st; // @[lsu.scala:247:20, :525:27, :663:50] wire _pf_st_T_1 = _pf_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :663:{50,75}] wire pf_st_0 = _pf_st_T_1; // @[lsu.scala:263:49, :663:75] wire _ae_ld_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_ld; // @[lsu.scala:247:20, :525:27, :664:50] wire _ae_ld_T_1 = _ae_ld_T & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:263:49, :664:{50,75}] wire ae_ld_0 = _ae_ld_T_1; // @[lsu.scala:263:49, :664:75] wire _ae_st_T = exe_tlb_valid_0 & _dtlb_io_resp_0_ae_st; // @[lsu.scala:247:20, :525:27, :665:50] wire _ae_st_T_1 = _ae_st_T & exe_tlb_uop_0_uses_stq; // @[lsu.scala:263:49, :665:{50,75}] wire ae_st_0 = _ae_st_T_1; // @[lsu.scala:263:49, :665:75] wire _mem_xcpt_valids_T = pf_ld_0 | pf_st_0; // @[lsu.scala:263:49, :669:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T | ae_ld_0; // @[lsu.scala:263:49, :669:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 | ae_st_0; // @[lsu.scala:263:49, :669:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 | ma_ld_0; // @[lsu.scala:263:49, :669:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 | ma_st_0; // @[lsu.scala:263:49, :669:{68,80}] wire _mem_xcpt_valids_T_5 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_4 & _mem_xcpt_valids_T_5; // @[lsu.scala:669:{80,93}, :670:22] wire [15:0] _mem_xcpt_valids_T_7 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:118:51] wire _mem_xcpt_valids_T_8 = |_mem_xcpt_valids_T_7; // @[util.scala:118:{51,59}] wire _mem_xcpt_valids_T_9 = ~_mem_xcpt_valids_T_8; // @[util.scala:118:59] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_6 & _mem_xcpt_valids_T_9; // @[lsu.scala:669:93, :670:41, :671:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_10; // @[lsu.scala:263:49, :670:41] reg mem_xcpt_valids_0; // @[lsu.scala:668:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:358:29, :668:32] wire [6:0] _mem_xcpt_uops_WIRE_0_uopc = mem_xcpt_uops_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:96:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iq_type = mem_xcpt_uops_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_xcpt_uops_WIRE_0_fu_code = mem_xcpt_uops_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_ctrl_br_type = mem_xcpt_uops_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_ctrl_op1_sel = mem_xcpt_uops_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_op2_sel = mem_xcpt_uops_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_imm_sel = mem_xcpt_uops_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ctrl_op_fcn = mem_xcpt_uops_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_fcn_dw = mem_xcpt_uops_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_xcpt_uops_WIRE_0_ctrl_csr_cmd = mem_xcpt_uops_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_load = mem_xcpt_uops_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_sta = mem_xcpt_uops_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ctrl_is_std = mem_xcpt_uops_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_iw_state = mem_xcpt_uops_out_iw_state; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_poisoned = mem_xcpt_uops_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_poisoned = mem_xcpt_uops_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_br = mem_xcpt_uops_out_is_br; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jalr = mem_xcpt_uops_out_is_jalr; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_jal = mem_xcpt_uops_out_is_jal; // @[util.scala:96:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:96:23] wire [15:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:96:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:96:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_xcpt_uops_WIRE_0_csr_addr = mem_xcpt_uops_out_csr_addr; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:96:23] wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:96:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bypassable = mem_xcpt_uops_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_ldst_val = mem_xcpt_uops_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_fp_single = mem_xcpt_uops_out_fp_single; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:96:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:96:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_xcpt_uops_0_uopc; // @[lsu.scala:672:32] assign mem_xcpt_uop_uopc = mem_xcpt_uops_0_uopc; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:360:29, :672:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:360:29, :672:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_iq_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_iq_type = mem_xcpt_uops_0_iq_type; // @[lsu.scala:360:29, :672:32] reg [9:0] mem_xcpt_uops_0_fu_code; // @[lsu.scala:672:32] assign mem_xcpt_uop_fu_code = mem_xcpt_uops_0_fu_code; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_br_type = mem_xcpt_uops_0_ctrl_br_type; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op1_sel = mem_xcpt_uops_0_ctrl_op1_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op2_sel = mem_xcpt_uops_0_ctrl_op2_sel; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_imm_sel = mem_xcpt_uops_0_ctrl_imm_sel; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_op_fcn = mem_xcpt_uops_0_ctrl_op_fcn; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_fcn_dw = mem_xcpt_uops_0_ctrl_fcn_dw; // @[lsu.scala:360:29, :672:32] reg [2:0] mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_csr_cmd = mem_xcpt_uops_0_ctrl_csr_cmd; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_load = mem_xcpt_uops_0_ctrl_is_load; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_sta = mem_xcpt_uops_0_ctrl_is_sta; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:672:32] assign mem_xcpt_uop_ctrl_is_std = mem_xcpt_uops_0_ctrl_is_std; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_iw_state; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_state = mem_xcpt_uops_0_iw_state; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p1_poisoned = mem_xcpt_uops_0_iw_p1_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:672:32] assign mem_xcpt_uop_iw_p2_poisoned = mem_xcpt_uops_0_iw_p2_poisoned; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_br; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_br = mem_xcpt_uops_0_is_br; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jalr; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jalr = mem_xcpt_uops_0_is_jalr; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_jal; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_jal = mem_xcpt_uops_0_is_jal; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:360:29, :672:32] reg [15:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:360:29, :672:32] reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:672:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:672:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:672:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:672:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:360:29, :672:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:672:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:360:29, :672:32] reg [11:0] mem_xcpt_uops_0_csr_addr; // @[lsu.scala:672:32] assign mem_xcpt_uop_csr_addr = mem_xcpt_uops_0_csr_addr; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:672:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:672:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:360:29, :672:32] reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:672:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:672:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:360:29, :672:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:672:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bypassable; // @[lsu.scala:672:32] assign mem_xcpt_uop_bypassable = mem_xcpt_uops_0_bypassable; // @[lsu.scala:360:29, :672:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:672:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:672:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:672:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:672:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:360:29, :672:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_ldst_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_ldst_val = mem_xcpt_uops_0_ldst_val; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:672:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:672:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_fp_single; // @[lsu.scala:672:32] assign mem_xcpt_uop_fp_single = mem_xcpt_uops_0_fp_single; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:360:29, :672:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:672:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:360:29, :672:32] reg [1:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:672:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:360:29, :672:32] wire [2:0] _mem_xcpt_causes_T = {1'h1, ~ae_ld_0, 1'h1}; // @[lsu.scala:263:49, :678:8] wire [3:0] _mem_xcpt_causes_T_1 = pf_st_0 ? 4'hF : {1'h0, _mem_xcpt_causes_T}; // @[lsu.scala:263:49, :677:8, :678:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : _mem_xcpt_causes_T_1; // @[lsu.scala:263:49, :676:8, :677:8] wire [3:0] _mem_xcpt_causes_T_3 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_2; // @[lsu.scala:263:49, :675:8, :676:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:263:49, :674:8, :675:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_4; // @[lsu.scala:263:49, :674:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:673:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:359:29, :673:32] reg [39:0] mem_xcpt_vaddrs_0; // @[lsu.scala:680:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:361:29, :680:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:709:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:525:27, :709:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:263:49, :709:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:247:20, :710:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:263:49, :711:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:710:{40,62}, :711:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:263:49, :710:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:247:20, :712:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:263:49, :712:43] reg REG; // @[lsu.scala:719:21] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uopc_0 = dmem_req_0_bits_uop_uopc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0 = dmem_req_0_bits_uop_iq_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0 = dmem_req_0_bits_uop_fu_code; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_br_type_0 = dmem_req_0_bits_uop_ctrl_br_type; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel_0 = dmem_req_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel_0 = dmem_req_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel_0 = dmem_req_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn_0 = dmem_req_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw_0 = dmem_req_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd_0 = dmem_req_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_load_0 = dmem_req_0_bits_uop_ctrl_is_load; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta_0 = dmem_req_0_bits_uop_ctrl_is_sta; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ctrl_is_std_0 = dmem_req_0_bits_uop_ctrl_is_std; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_state_0 = dmem_req_0_bits_uop_iw_state; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned_0 = dmem_req_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned_0 = dmem_req_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_br_0 = dmem_req_0_bits_uop_is_br; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jalr_0 = dmem_req_0_bits_uop_is_jalr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_jal_0 = dmem_req_0_bits_uop_is_jal; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_csr_addr_0 = dmem_req_0_bits_uop_csr_addr; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bypassable_0 = dmem_req_0_bits_uop_bypassable; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_ldst_val_0 = dmem_req_0_bits_uop_ldst_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_fp_single_0 = dmem_req_0_bits_uop_fp_single; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:201:7, :750:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:263:49, :750:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:201:7, :750:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:201:7, :750:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:263:49, :753:55] wire s0_executing_loads_0; // @[lsu.scala:755:36] wire s0_executing_loads_1; // @[lsu.scala:755:36] wire s0_executing_loads_2; // @[lsu.scala:755:36] wire s0_executing_loads_3; // @[lsu.scala:755:36] wire s0_executing_loads_4; // @[lsu.scala:755:36] wire s0_executing_loads_5; // @[lsu.scala:755:36] wire s0_executing_loads_6; // @[lsu.scala:755:36] wire s0_executing_loads_7; // @[lsu.scala:755:36] wire s0_executing_loads_8; // @[lsu.scala:755:36] wire s0_executing_loads_9; // @[lsu.scala:755:36] wire s0_executing_loads_10; // @[lsu.scala:755:36] wire s0_executing_loads_11; // @[lsu.scala:755:36] wire s0_executing_loads_12; // @[lsu.scala:755:36] wire s0_executing_loads_13; // @[lsu.scala:755:36] wire s0_executing_loads_14; // @[lsu.scala:755:36] wire s0_executing_loads_15; // @[lsu.scala:755:36] wire s0_executing_loads_16; // @[lsu.scala:755:36] wire s0_executing_loads_17; // @[lsu.scala:755:36] wire s0_executing_loads_18; // @[lsu.scala:755:36] wire s0_executing_loads_19; // @[lsu.scala:755:36] wire s0_executing_loads_20; // @[lsu.scala:755:36] wire s0_executing_loads_21; // @[lsu.scala:755:36] wire s0_executing_loads_22; // @[lsu.scala:755:36] wire s0_executing_loads_23; // @[lsu.scala:755:36] wire _dmem_req_0_valid_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33] wire _dmem_req_0_valid_T_1 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53] wire _dmem_req_0_valid_T_2 = _dmem_req_0_valid_T & _dmem_req_0_valid_T_1; // @[lsu.scala:768:{33,50,53}] wire [39:0] _GEN_291 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:263:49, :769:30] wire _dmem_req_0_valid_T_3 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :775:33] wire _dmem_req_0_valid_T_4 = ~exe_tlb_uncacheable_0; // @[lsu.scala:263:49, :768:53, :775:53] wire _dmem_req_0_valid_T_5 = _dmem_req_0_valid_T_3 & _dmem_req_0_valid_T_4; // @[lsu.scala:775:{33,50,53}] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _GEN_88[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _GEN_88[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _GEN_88[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _GEN_88; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_292 = stq_execute_head == 5'h17; // @[util.scala:205:25] wire stq_execute_head_wrap; // @[util.scala:205:25] assign stq_execute_head_wrap = _GEN_292; // @[util.scala:205:25] wire stq_execute_head_wrap_1; // @[util.scala:205:25] assign stq_execute_head_wrap_1 = _GEN_292; // @[util.scala:205:25] wire [5:0] _GEN_293 = {1'h0, stq_execute_head} + 6'h1; // @[util.scala:206:28] wire [5:0] _stq_execute_head_T; // @[util.scala:206:28] assign _stq_execute_head_T = _GEN_293; // @[util.scala:206:28] wire [5:0] _stq_execute_head_T_4; // @[util.scala:206:28] assign _stq_execute_head_T_4 = _GEN_293; // @[util.scala:206:28] wire [4:0] _stq_execute_head_T_1 = _stq_execute_head_T[4:0]; // @[util.scala:206:28] wire [4:0] _stq_execute_head_T_2 = stq_execute_head_wrap ? 5'h0 : _stq_execute_head_T_1; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _stq_execute_head_T_3 = dmem_req_fire_0 ? _stq_execute_head_T_2 : stq_execute_head; // @[util.scala:206:10] wire _GEN_294 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:218:29, :370:38, :378:38, :767:39, :774:43, :781:45] assign dmem_req_0_bits_uop_uopc = _GEN_294 ? exe_tlb_uop_0_uopc : will_fire_store_commit_0 ? _GEN_1[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_uopc : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_inst = _GEN_294 ? exe_tlb_uop_0_inst : will_fire_store_commit_0 ? _GEN_2[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_inst = _GEN_294 ? exe_tlb_uop_0_debug_inst : will_fire_store_commit_0 ? _GEN_3[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_inst : 32'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_rvc = _GEN_294 ? exe_tlb_uop_0_is_rvc : will_fire_store_commit_0 ? _GEN_4[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_rvc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_pc = _GEN_294 ? exe_tlb_uop_0_debug_pc : will_fire_store_commit_0 ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_pc : 40'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iq_type = _GEN_294 ? exe_tlb_uop_0_iq_type : will_fire_store_commit_0 ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iq_type : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fu_code = _GEN_294 ? exe_tlb_uop_0_fu_code : will_fire_store_commit_0 ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_fu_code : 10'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_br_type = _GEN_294 ? exe_tlb_uop_0_ctrl_br_type : will_fire_store_commit_0 ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_br_type : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op1_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_op1_sel : will_fire_store_commit_0 ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op1_sel : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op2_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_op2_sel : will_fire_store_commit_0 ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op2_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_imm_sel = _GEN_294 ? exe_tlb_uop_0_ctrl_imm_sel : will_fire_store_commit_0 ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_imm_sel : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_op_fcn = _GEN_294 ? exe_tlb_uop_0_ctrl_op_fcn : will_fire_store_commit_0 ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_op_fcn : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_fcn_dw = _GEN_294 ? exe_tlb_uop_0_ctrl_fcn_dw : will_fire_store_commit_0 ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_csr_cmd = _GEN_294 ? exe_tlb_uop_0_ctrl_csr_cmd : will_fire_store_commit_0 ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ctrl_csr_cmd : 3'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_load = _GEN_294 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0 ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_sta = _GEN_294 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0 ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ctrl_is_std = _GEN_294 ? exe_tlb_uop_0_ctrl_is_std : will_fire_store_commit_0 ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_state = _GEN_294 ? exe_tlb_uop_0_iw_state : will_fire_store_commit_0 ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_iw_state : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p1_poisoned = _GEN_294 ? exe_tlb_uop_0_iw_p1_poisoned : will_fire_store_commit_0 ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_iw_p2_poisoned = _GEN_294 ? exe_tlb_uop_0_iw_p2_poisoned : will_fire_store_commit_0 ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_br = _GEN_294 ? exe_tlb_uop_0_is_br : will_fire_store_commit_0 ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_br; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jalr = _GEN_294 ? exe_tlb_uop_0_is_jalr : will_fire_store_commit_0 ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jalr; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_jal = _GEN_294 ? exe_tlb_uop_0_is_jal : will_fire_store_commit_0 ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_jal; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sfb = _GEN_294 ? exe_tlb_uop_0_is_sfb : will_fire_store_commit_0 ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sfb; // @[util.scala:106:23] assign dmem_req_0_bits_uop_br_mask = _GEN_294 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0 ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0 ? _GEN_125[_ldq_wakeup_e_T_1] : 16'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :381:38, :501:88, :750:22, :760:28, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44, :798:30] assign dmem_req_0_bits_uop_br_tag = _GEN_294 ? exe_tlb_uop_0_br_tag : will_fire_store_commit_0 ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_br_tag : 4'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ftq_idx = _GEN_294 ? exe_tlb_uop_0_ftq_idx : will_fire_store_commit_0 ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ftq_idx : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_edge_inst = _GEN_294 ? exe_tlb_uop_0_edge_inst : will_fire_store_commit_0 ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_edge_inst; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pc_lob = _GEN_294 ? exe_tlb_uop_0_pc_lob : will_fire_store_commit_0 ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pc_lob : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_taken = _GEN_294 ? exe_tlb_uop_0_taken : will_fire_store_commit_0 ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_taken; // @[util.scala:106:23] assign dmem_req_0_bits_uop_imm_packed = _GEN_294 ? exe_tlb_uop_0_imm_packed : will_fire_store_commit_0 ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_imm_packed : 20'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_csr_addr = _GEN_294 ? exe_tlb_uop_0_csr_addr : will_fire_store_commit_0 ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_csr_addr : 12'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rob_idx = _GEN_294 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0 ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rob_idx : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldq_idx = _GEN_294 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0 ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldq_idx : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_stq_idx = _GEN_294 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0 ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_rxq_idx = _GEN_294 ? exe_tlb_uop_0_rxq_idx : will_fire_store_commit_0 ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_rxq_idx : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_pdst = _GEN_294 ? exe_tlb_uop_0_pdst : will_fire_store_commit_0 ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_pdst : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs1 = _GEN_294 ? exe_tlb_uop_0_prs1 : will_fire_store_commit_0 ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs1 : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2 = _GEN_294 ? exe_tlb_uop_0_prs2 : will_fire_store_commit_0 ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs2 : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3 = _GEN_294 ? exe_tlb_uop_0_prs3 : will_fire_store_commit_0 ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_prs3 : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred = _GEN_294 ? exe_tlb_uop_0_ppred : will_fire_store_commit_0 ? _GEN_41[stq_execute_head] : 5'h0; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_prs1_busy = _GEN_294 ? exe_tlb_uop_0_prs1_busy : will_fire_store_commit_0 ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs2_busy = _GEN_294 ? exe_tlb_uop_0_prs2_busy : will_fire_store_commit_0 ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_prs3_busy = _GEN_294 ? exe_tlb_uop_0_prs3_busy : will_fire_store_commit_0 ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ppred_busy = _GEN_294 ? exe_tlb_uop_0_ppred_busy : will_fire_store_commit_0 & _GEN_45[stq_execute_head]; // @[lsu.scala:218:29, :222:42, :263:49, :380:38, :750:22, :767:39, :770:30, :774:43, :777:30, :781:45, :788:33, :795:44] assign dmem_req_0_bits_uop_stale_pdst = _GEN_294 ? exe_tlb_uop_0_stale_pdst : will_fire_store_commit_0 ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_stale_pdst : 7'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exception = _GEN_294 ? exe_tlb_uop_0_exception : will_fire_store_commit_0 ? _GEN_48 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_exception; // @[util.scala:106:23] assign dmem_req_0_bits_uop_exc_cause = _GEN_294 ? exe_tlb_uop_0_exc_cause : will_fire_store_commit_0 ? _GEN_49[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_exc_cause : 64'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bypassable = _GEN_294 ? exe_tlb_uop_0_bypassable : will_fire_store_commit_0 ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bypassable; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fence = _GEN_294 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0 ? _GEN_55 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fence; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_fencei = _GEN_294 ? exe_tlb_uop_0_is_fencei : will_fire_store_commit_0 ? _GEN_56[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_fencei; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_amo = _GEN_294 ? exe_tlb_uop_0_is_amo : will_fire_store_commit_0 ? _GEN_58 : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_amo; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_ldq = _GEN_294 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0 ? _GEN_59[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_uses_stq = _GEN_294 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0 ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_uses_stq; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_294 ? exe_tlb_uop_0_is_sys_pc2epc : will_fire_store_commit_0 ? _GEN_61[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] assign dmem_req_0_bits_uop_is_unique = _GEN_294 ? exe_tlb_uop_0_is_unique : will_fire_store_commit_0 ? _GEN_62[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_is_unique; // @[util.scala:106:23] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_294 ? exe_tlb_uop_0_flush_on_commit : will_fire_store_commit_0 ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_294 ? exe_tlb_uop_0_ldst_is_rs1 : will_fire_store_commit_0 ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst = _GEN_294 ? exe_tlb_uop_0_ldst : will_fire_store_commit_0 ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_ldst : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1 = _GEN_294 ? exe_tlb_uop_0_lrs1 : will_fire_store_commit_0 ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2 = _GEN_294 ? exe_tlb_uop_0_lrs2 : will_fire_store_commit_0 ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs3 = _GEN_294 ? exe_tlb_uop_0_lrs3 : will_fire_store_commit_0 ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs3 : 6'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_ldst_val = _GEN_294 ? exe_tlb_uop_0_ldst_val : will_fire_store_commit_0 ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_ldst_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_dst_rtype = _GEN_294 ? exe_tlb_uop_0_dst_rtype : will_fire_store_commit_0 ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_dst_rtype : 2'h2; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_294 ? exe_tlb_uop_0_lrs1_rtype : will_fire_store_commit_0 ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_294 ? exe_tlb_uop_0_lrs2_rtype : will_fire_store_commit_0 ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_frs3_en = _GEN_294 ? exe_tlb_uop_0_frs3_en : will_fire_store_commit_0 ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_frs3_en; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_val = _GEN_294 ? exe_tlb_uop_0_fp_val : will_fire_store_commit_0 ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_val; // @[util.scala:106:23] assign dmem_req_0_bits_uop_fp_single = _GEN_294 ? exe_tlb_uop_0_fp_single : will_fire_store_commit_0 ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_fp_single; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_294 ? exe_tlb_uop_0_xcpt_pf_if : will_fire_store_commit_0 ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_294 ? exe_tlb_uop_0_xcpt_ae_if : will_fire_store_commit_0 ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_294 ? exe_tlb_uop_0_xcpt_ma_if : will_fire_store_commit_0 ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_294 ? exe_tlb_uop_0_bp_debug_if : will_fire_store_commit_0 ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_294 ? exe_tlb_uop_0_bp_xcpt_if : will_fire_store_commit_0 ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_294 ? exe_tlb_uop_0_debug_fsrc : will_fire_store_commit_0 ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_fsrc : 2'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_294 ? exe_tlb_uop_0_debug_tsrc : will_fire_store_commit_0 ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_debug_tsrc : 2'h0; // @[util.scala:106:23] assign s0_executing_loads_0 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h0 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_267 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_243 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_1 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h1 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_268 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_244 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_2 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h2 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_269 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_245 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_3 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h3 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_270 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_246 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_4 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h4 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_271 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_247 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_5 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h5 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_272 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_248 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_6 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h6 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_273 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_249 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_7 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h7 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_274 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_250 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_8 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h8 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_275 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_251 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_9 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h9 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_276 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_252 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_10 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hA & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_277 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_253 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_11 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hB & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_278 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_254 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_12 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hC & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_279 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_255 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_13 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hD & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_280 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_256 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_14 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hE & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_281 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_257 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_15 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'hF & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_282 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_258 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_16 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h10 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_283 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_259 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_17 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h11 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_284 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_260 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_18 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h12 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_285 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_261 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_19 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h13 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_286 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_262 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_20 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h14 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_287 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_263 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_21 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h15 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_288 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_264 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_22 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h16 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_289 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_265 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] assign s0_executing_loads_23 = will_fire_load_incoming_0 ? ldq_incoming_idx_0 == 5'h17 & dmem_req_fire_0 : will_fire_load_retry_0 ? _GEN_290 & dmem_req_fire_0 : ~will_fire_store_commit_0 & will_fire_load_wakeup_0 & _GEN_266 & dmem_req_fire_0; // @[lsu.scala:218:29, :263:49, :370:38, :378:38, :380:38, :381:38, :569:49, :573:49, :755:36, :767:39, :772:47, :774:43, :779:41, :781:45, :795:44, :800:42] wire _dmem_req_0_valid_T_6 = ~io_hellacache_s1_kill_0; // @[lsu.scala:201:7, :806:42] wire _dmem_req_0_valid_T_9 = _dmem_req_0_valid_T_6; // @[lsu.scala:806:{42,65}] wire _dmem_req_0_valid_T_7 = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :806:69] wire _GEN_295 = will_fire_store_commit_0 | will_fire_load_wakeup_0; // @[lsu.scala:243:34, :380:38, :381:38, :781:45, :795:44, :803:47] assign dmem_req_0_valid = will_fire_load_incoming_0 ? _dmem_req_0_valid_T_2 : will_fire_load_retry_0 ? _dmem_req_0_valid_T_5 : _GEN_295 | (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_9 : will_fire_hella_wakeup_0); // @[lsu.scala:243:34, :370:38, :375:38, :376:38, :378:38, :750:22, :767:39, :768:{30,50}, :774:43, :775:{30,50}, :781:45, :782:33, :795:44, :796:30, :803:47, :806:{39,65}, :820:5] assign dmem_req_0_bits_addr = will_fire_load_incoming_0 | will_fire_load_retry_0 ? _GEN_291 : will_fire_store_commit_0 ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_291 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[util.scala:106:23] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_294 ? 64'h0 : will_fire_store_commit_0 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 | will_fire_hella_incoming_0 | ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_294 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0 ? _GEN_51[stq_execute_head] : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_cmd : 5'h0; // @[util.scala:106:23] assign dmem_req_0_bits_uop_mem_size = _GEN_294 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0 ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0 ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0 | will_fire_hella_wakeup_0}}; // @[AMOALU.scala:11:18] assign dmem_req_0_bits_uop_mem_signed = _GEN_294 ? exe_tlb_uop_0_mem_signed : will_fire_store_commit_0 ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0 & mem_ldq_wakeup_e_out_bits_uop_mem_signed; // @[util.scala:106:23] assign dmem_req_0_bits_is_hella = ~(_GEN_294 | will_fire_store_commit_0 | will_fire_load_wakeup_0) & (will_fire_hella_incoming_0 | will_fire_hella_wakeup_0); // @[lsu.scala:218:29, :375:38, :376:38, :380:38, :381:38, :750:22, :763:31, :767:39, :774:43, :781:45, :795:44, :803:47, :815:39, :820:5] wire _T_226 = will_fire_load_incoming_0 | will_fire_load_retry_0; // @[lsu.scala:370:38, :378:38, :836:38] wire [4:0] ldq_idx = will_fire_load_incoming_0 ? ldq_incoming_idx_0 : ldq_retry_idx; // @[lsu.scala:263:49, :370:38, :414:30, :838:24] wire [39:0] _GEN_296 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : _GEN_291; // @[lsu.scala:263:49, :769:30, :840:51] wire [39:0] _ldq_bits_addr_bits_T; // @[lsu.scala:840:51] assign _ldq_bits_addr_bits_T = _GEN_296; // @[lsu.scala:840:51] wire [39:0] _stq_bits_addr_bits_T; // @[lsu.scala:855:42] assign _stq_bits_addr_bits_T = _GEN_296; // @[lsu.scala:840:51, :855:42] wire _ldq_bits_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:263:49, :768:33, :843:74] wire _ldq_bits_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_bits_addr_is_uncacheable_T; // @[lsu.scala:263:49, :843:{71,74}] wire _T_243 = _T_242 | will_fire_sta_retry_0; // @[lsu.scala:379:38, :661:56, :849:67] wire [4:0] stq_idx = _stq_idx_T ? stq_incoming_idx_0 : stq_retry_idx; // @[lsu.scala:263:49, :421:30, :851:{24,51}] wire _stq_bits_addr_valid_T = ~pf_st_0; // @[lsu.scala:263:49, :854:39] wire _io_core_fp_stdata_ready_T = ~will_fire_std_incoming_0; // @[lsu.scala:373:38, :867:34] wire _io_core_fp_stdata_ready_T_1 = ~will_fire_stad_incoming_0; // @[lsu.scala:371:38, :867:64] assign _io_core_fp_stdata_ready_T_2 = _io_core_fp_stdata_ready_T & _io_core_fp_stdata_ready_T_1; // @[lsu.scala:867:{34,61,64}] assign io_core_fp_stdata_ready_0 = _io_core_fp_stdata_ready_T_2; // @[lsu.scala:201:7, :867:61] wire _GEN_297 = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid_0; // @[Decoupled.scala:51:35] wire _fp_stdata_fire_T; // @[Decoupled.scala:51:35] assign _fp_stdata_fire_T = _GEN_297; // @[Decoupled.scala:51:35] wire will_fire_stdf_incoming; // @[Decoupled.scala:51:35] assign will_fire_stdf_incoming = _GEN_297; // @[Decoupled.scala:51:35] wire fp_stdata_fire = _fp_stdata_fire_T; // @[Decoupled.scala:51:35] wire _T_257 = will_fire_std_incoming_0 | will_fire_stad_incoming_0; // @[lsu.scala:371:38, :373:38, :869:37] wire _sidx_T; // @[lsu.scala:871:48] assign _sidx_T = _T_257; // @[lsu.scala:869:37, :871:48] wire _stq_bits_data_bits_T; // @[lsu.scala:875:66] assign _stq_bits_data_bits_T = _T_257; // @[lsu.scala:869:37, :875:66] wire _T_258 = _T_257 | fp_stdata_fire; // @[lsu.scala:868:49, :869:{37,67}] wire [4:0] sidx = _sidx_T ? stq_incoming_idx_0 : io_core_fp_stdata_bits_uop_stq_idx_0; // @[lsu.scala:201:7, :263:49, :871:{21,48}] wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? exe_req_0_bits_data : io_core_fp_stdata_bits_data_0; // @[lsu.scala:201:7, :383:25, :875:{39,66}] wire [15:0] _exe_req_killed_T = io_core_brupdate_b1_mispredict_mask_0 & exe_req_0_bits_uop_br_mask; // @[util.scala:118:51] wire _exe_req_killed_T_1 = |_exe_req_killed_T; // @[util.scala:118:{51,59}] wire exe_req_killed_0 = _exe_req_killed_T_1; // @[util.scala:118:59] wire [15:0] _stdf_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_fp_stdata_bits_uop_br_mask_0; // @[util.scala:118:51] wire stdf_killed = |_stdf_killed_T; // @[util.scala:118:{51,59}] wire _fired_load_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82] wire _fired_load_incoming_T_1 = will_fire_load_incoming_0 & _fired_load_incoming_T; // @[lsu.scala:370:38, :895:{79,82}] reg fired_load_incoming_REG; // @[lsu.scala:895:51] wire fired_load_incoming_0 = fired_load_incoming_REG; // @[lsu.scala:263:49, :895:51] wire _io_core_spec_ld_wakeup_0_valid_T = fired_load_incoming_0; // @[lsu.scala:263:49, :1259:69] wire _fired_stad_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :896:82] wire _fired_stad_incoming_T_1 = will_fire_stad_incoming_0 & _fired_stad_incoming_T; // @[lsu.scala:371:38, :896:{79,82}] reg fired_stad_incoming_REG; // @[lsu.scala:896:51] wire fired_stad_incoming_0 = fired_stad_incoming_REG; // @[lsu.scala:263:49, :896:51] wire _fired_sta_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :897:82] wire _fired_sta_incoming_T_1 = will_fire_sta_incoming_0 & _fired_sta_incoming_T; // @[lsu.scala:372:38, :897:{79,82}] reg fired_sta_incoming_REG; // @[lsu.scala:897:51] wire fired_sta_incoming_0 = fired_sta_incoming_REG; // @[lsu.scala:263:49, :897:51] wire _fired_std_incoming_T = ~exe_req_killed_0; // @[lsu.scala:263:49, :895:82, :898:82] wire _fired_std_incoming_T_1 = will_fire_std_incoming_0 & _fired_std_incoming_T; // @[lsu.scala:373:38, :898:{79,82}] reg fired_std_incoming_REG; // @[lsu.scala:898:51] wire fired_std_incoming_0 = fired_std_incoming_REG; // @[lsu.scala:263:49, :898:51] wire _fired_stdf_incoming_T = ~stdf_killed; // @[util.scala:118:59] wire _fired_stdf_incoming_T_1 = will_fire_stdf_incoming & _fired_stdf_incoming_T; // @[Decoupled.scala:51:35] reg fired_stdf_incoming; // @[lsu.scala:899:37] reg fired_sfence_0; // @[lsu.scala:900:37] reg fired_release_0; // @[lsu.scala:901:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:263:49, :901:37] wire [15:0] _GEN_298 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_ldq_retry_e_T_1]; // @[util.scala:118:51] wire [15:0] _fired_load_retry_T; // @[util.scala:118:51] assign _fired_load_retry_T = _GEN_298; // @[util.scala:118:51] wire [15:0] _mem_ldq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_retry_e_out_valid_T = _GEN_298; // @[util.scala:118:51] wire _fired_load_retry_T_1 = |_fired_load_retry_T; // @[util.scala:118:{51,59}] wire _fired_load_retry_T_2 = ~_fired_load_retry_T_1; // @[util.scala:118:59] wire _fired_load_retry_T_3 = will_fire_load_retry_0 & _fired_load_retry_T_2; // @[lsu.scala:378:38, :902:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:902:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:263:49, :902:51] wire [15:0] _GEN_299 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_25[_stq_retry_e_T_1]; // @[util.scala:118:51] wire [15:0] _fired_sta_retry_T; // @[util.scala:118:51] assign _fired_sta_retry_T = _GEN_299; // @[util.scala:118:51] wire [15:0] _mem_stq_retry_e_out_valid_T; // @[util.scala:118:51] assign _mem_stq_retry_e_out_valid_T = _GEN_299; // @[util.scala:118:51] wire _fired_sta_retry_T_1 = |_fired_sta_retry_T; // @[util.scala:118:{51,59}] wire _fired_sta_retry_T_2 = ~_fired_sta_retry_T_1; // @[util.scala:118:59] wire _fired_sta_retry_T_3 = will_fire_sta_retry_0 & _fired_sta_retry_T_2; // @[lsu.scala:379:38, :903:{79,82}] reg fired_sta_retry_REG; // @[lsu.scala:903:51] wire fired_sta_retry_0 = fired_sta_retry_REG; // @[lsu.scala:263:49, :903:51] reg fired_store_commit_0; // @[lsu.scala:904:37] wire [15:0] _GEN_300 = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_ldq_wakeup_e_T_1]; // @[util.scala:118:51] wire [15:0] _fired_load_wakeup_T; // @[util.scala:118:51] assign _fired_load_wakeup_T = _GEN_300; // @[util.scala:118:51] wire [15:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_300; // @[util.scala:118:51] wire _fired_load_wakeup_T_1 = |_fired_load_wakeup_T; // @[util.scala:118:{51,59}] wire _fired_load_wakeup_T_2 = ~_fired_load_wakeup_T_1; // @[util.scala:118:59] wire _fired_load_wakeup_T_3 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_2; // @[lsu.scala:381:38, :905:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:905:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:263:49, :905:51] reg fired_hella_incoming_0; // @[lsu.scala:906:37] reg fired_hella_wakeup_0; // @[lsu.scala:907:37] wire [6:0] _mem_incoming_uop_WIRE_0_uopc = mem_incoming_uop_out_uopc; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:96:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:96:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_iq_type = mem_incoming_uop_out_iq_type; // @[util.scala:96:23] wire [9:0] _mem_incoming_uop_WIRE_0_fu_code = mem_incoming_uop_out_fu_code; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_ctrl_br_type = mem_incoming_uop_out_ctrl_br_type; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_ctrl_op1_sel = mem_incoming_uop_out_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_op2_sel = mem_incoming_uop_out_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_imm_sel = mem_incoming_uop_out_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ctrl_op_fcn = mem_incoming_uop_out_ctrl_op_fcn; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_fcn_dw = mem_incoming_uop_out_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] _mem_incoming_uop_WIRE_0_ctrl_csr_cmd = mem_incoming_uop_out_ctrl_csr_cmd; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_load = mem_incoming_uop_out_ctrl_is_load; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_sta = mem_incoming_uop_out_ctrl_is_sta; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ctrl_is_std = mem_incoming_uop_out_ctrl_is_std; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_iw_state = mem_incoming_uop_out_iw_state; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p1_poisoned = mem_incoming_uop_out_iw_p1_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_iw_p2_poisoned = mem_incoming_uop_out_iw_p2_poisoned; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_br = mem_incoming_uop_out_is_br; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jalr = mem_incoming_uop_out_is_jalr; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_jal = mem_incoming_uop_out_is_jal; // @[util.scala:96:23] wire [15:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:96:23] wire [15:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:96:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:96:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:96:23] wire [11:0] _mem_incoming_uop_WIRE_0_csr_addr = mem_incoming_uop_out_csr_addr; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:96:23] wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:96:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bypassable = mem_incoming_uop_out_bypassable; // @[util.scala:96:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:96:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_ldst_val = mem_incoming_uop_out_ldst_val; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_fp_single = mem_incoming_uop_out_fp_single; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:96:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:96:23] wire [1:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:96:23] wire [15:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_incoming_uop_out_br_mask_T_1 = exe_req_0_bits_uop_br_mask & _mem_incoming_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_incoming_uop_0_uopc; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:909:37] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:909:37] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_iq_type; // @[lsu.scala:909:37] reg [9:0] mem_incoming_uop_0_fu_code; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_ctrl_br_type; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_ctrl_op1_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_op2_sel; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_imm_sel; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ctrl_op_fcn; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_fcn_dw; // @[lsu.scala:909:37] reg [2:0] mem_incoming_uop_0_ctrl_csr_cmd; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_load; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_sta; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ctrl_is_std; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_iw_state; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p1_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_iw_p2_poisoned; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_br; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jalr; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_jal; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:909:37] reg [15:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:909:37] reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:909:37] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:909:37] reg mem_incoming_uop_0_taken; // @[lsu.scala:909:37] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:909:37] reg [11:0] mem_incoming_uop_0_csr_addr; // @[lsu.scala:909:37] reg [6:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:909:37] reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:909:37] assign io_core_spec_ld_wakeup_0_bits_0 = mem_incoming_uop_0_pdst; // @[lsu.scala:201:7, :909:37] reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:909:37] reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:909:37] reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:909:37] reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:909:37] reg mem_incoming_uop_0_exception; // @[lsu.scala:909:37] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bypassable; // @[lsu.scala:909:37] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:909:37] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:909:37] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:909:37] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:909:37] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:909:37] reg mem_incoming_uop_0_ldst_val; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:909:37] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37] reg mem_incoming_uop_0_fp_single; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:909:37] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:909:37] reg [1:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:909:37] wire _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_uopc = mem_ldq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type = mem_ldq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code = mem_ldq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_ldq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_ldq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_ldq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_ldq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_ldq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_ldq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_ldq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_ldq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_state = mem_ldq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_ldq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_br = mem_ldq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_ldq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_jal = mem_ldq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_ldq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bypassable = mem_ldq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_ldq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_single = mem_ldq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:106:23] wire [23:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_youngest_stq_idx = mem_ldq_incoming_e_out_bits_youngest_stq_idx; // @[util.scala:106:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:106:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:106:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [15:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_ldq_incoming_e_out_valid_T_1 = |_mem_ldq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = ~_mem_ldq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_incoming_e_out_valid_T_3 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:910:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:910:37] reg [9:0] mem_ldq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:910:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:910:37] reg [15:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:910:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:910:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:910:37] reg [11:0] mem_ldq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:910:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:910:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:910:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:910:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:910:37] reg [23:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_youngest_stq_idx; // @[lsu.scala:910:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:910:37] reg [4:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:910:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:910:37] wire _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:108:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_uopc = mem_stq_incoming_e_out_bits_uop_uopc; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:106:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type = mem_stq_incoming_e_out_bits_uop_iq_type; // @[util.scala:106:23] wire [9:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code = mem_stq_incoming_e_out_bits_uop_fu_code; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_br_type = mem_stq_incoming_e_out_bits_uop_ctrl_br_type; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op1_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op1_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op2_sel = mem_stq_incoming_e_out_bits_uop_ctrl_op2_sel; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_imm_sel = mem_stq_incoming_e_out_bits_uop_ctrl_imm_sel; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_op_fcn = mem_stq_incoming_e_out_bits_uop_ctrl_op_fcn; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_fcn_dw = mem_stq_incoming_e_out_bits_uop_ctrl_fcn_dw; // @[util.scala:106:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_csr_cmd = mem_stq_incoming_e_out_bits_uop_ctrl_csr_cmd; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_load = mem_stq_incoming_e_out_bits_uop_ctrl_is_load; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_sta = mem_stq_incoming_e_out_bits_uop_ctrl_is_sta; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ctrl_is_std = mem_stq_incoming_e_out_bits_uop_ctrl_is_std; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_state = mem_stq_incoming_e_out_bits_uop_iw_state; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p1_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_poisoned = mem_stq_incoming_e_out_bits_uop_iw_p2_poisoned; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_br = mem_stq_incoming_e_out_bits_uop_is_br; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jalr = mem_stq_incoming_e_out_bits_uop_is_jalr; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_jal = mem_stq_incoming_e_out_bits_uop_is_jal; // @[util.scala:106:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:106:23] wire [15:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:106:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:106:23] wire [11:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_addr = mem_stq_incoming_e_out_bits_uop_csr_addr; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:106:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bypassable = mem_stq_incoming_e_out_bits_uop_bypassable; // @[util.scala:106:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:106:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_val = mem_stq_incoming_e_out_bits_uop_ldst_val; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_single = mem_stq_incoming_e_out_bits_uop_fp_single; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:106:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:106:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:106:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:106:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:106:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire [15:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire _mem_stq_incoming_e_out_valid_T_1 = |_mem_stq_incoming_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = ~_mem_stq_incoming_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_incoming_e_out_valid_T_3 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_uopc; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:911:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iq_type; // @[lsu.scala:911:37] reg [9:0] mem_stq_incoming_e_0_bits_uop_fu_code; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_ctrl_br_type; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_iw_state; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_br; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jalr; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_jal; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:911:37] reg [15:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:911:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:911:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:911:37] reg [11:0] mem_stq_incoming_e_0_bits_uop_csr_addr; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:911:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bypassable; // @[lsu.scala:911:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:911:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_ldst_val; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_fp_single; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:911:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:911:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:911:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:911:37] wire _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:108:31] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [15:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:106:23] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = _GEN_125[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = |_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = ~_mem_ldq_wakeup_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_wakeup_e_out_valid_T_3 = _GEN_94[_ldq_wakeup_e_T_1] & _mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_uopc; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:912:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iq_type; // @[lsu.scala:912:37] reg [9:0] mem_ldq_wakeup_e_bits_uop_fu_code; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_ctrl_br_type; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:912:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_iw_state; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:912:37] reg [15:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:912:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:912:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:912:37] reg [11:0] mem_ldq_wakeup_e_bits_uop_csr_addr; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:912:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:912:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:912:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:912:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:912:37] reg [23:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_youngest_stq_idx; // @[lsu.scala:912:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:912:37] reg [4:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:912:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:912:37] wire _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [15:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:106:23] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_125[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_ldq_retry_e_out_valid_T_1 = |_mem_ldq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = ~_mem_ldq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_ldq_retry_e_out_valid_T_3 = _GEN_94[_ldq_retry_e_T_1] & _mem_ldq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_uopc; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:913:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_iq_type; // @[lsu.scala:913:37] reg [9:0] mem_ldq_retry_e_bits_uop_fu_code; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:913:37] reg [2:0] mem_ldq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_iw_state; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_br; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jalr; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_jal; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:913:37] reg [15:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:913:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:913:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:913:37] reg [11:0] mem_ldq_retry_e_bits_uop_csr_addr; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:913:37] reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bypassable; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:913:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_ldst_val; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_fp_single; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:913:37] reg [1:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:913:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:913:37] reg [23:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_youngest_stq_idx; // @[lsu.scala:913:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:913:37] reg [4:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:913:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:913:37] wire _mem_stq_retry_e_out_valid_T_3; // @[util.scala:108:31] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21] wire [15:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:106:23] wire mem_stq_retry_e_out_valid; // @[util.scala:106:23] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = _GEN_25[_stq_retry_e_T_1] & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:89:21, :106:23] wire _mem_stq_retry_e_out_valid_T_1 = |_mem_stq_retry_e_out_valid_T; // @[util.scala:118:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = ~_mem_stq_retry_e_out_valid_T_1; // @[util.scala:108:34, :118:59] assign _mem_stq_retry_e_out_valid_T_3 = _GEN[_stq_retry_e_T_1] & _mem_stq_retry_e_out_valid_T_2; // @[util.scala:108:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_3; // @[util.scala:106:23, :108:31] reg mem_stq_retry_e_valid; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_uopc; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:914:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_iq_type; // @[lsu.scala:914:37] reg [9:0] mem_stq_retry_e_bits_uop_fu_code; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_ctrl_br_type; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_ctrl_op1_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_op2_sel; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_imm_sel; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ctrl_op_fcn; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:914:37] reg [2:0] mem_stq_retry_e_bits_uop_ctrl_csr_cmd; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_iw_state; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:914:37] reg [15:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:914:37] reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:914:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:914:37] reg [11:0] mem_stq_retry_e_bits_uop_csr_addr; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:914:37] reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:914:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:914:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:914:37] reg [1:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:914:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:914:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:914:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:914:37] wire _mem_ldq_e_T_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_uopc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [31:0] _mem_ldq_e_T_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_iq_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [9:0] _mem_ldq_e_T_bits_uop_fu_code = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_ctrl_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_ctrl_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ctrl_op_fcn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :912:37, :918:33] wire [2:0] _mem_ldq_e_T_bits_uop_ctrl_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_load = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_sta = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ctrl_is_std = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_iw_state = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p1_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_iw_p2_poisoned = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_br = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_br; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jalr = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_jal = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_jal; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :912:37, :918:33] wire [15:0] _mem_ldq_e_T_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [3:0] _mem_ldq_e_T_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:263:49, :912:37, :918:33] wire [19:0] _mem_ldq_e_T_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [11:0] _mem_ldq_e_T_bits_uop_csr_addr = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :912:37, :918:33] wire [6:0] _mem_ldq_e_T_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bypassable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bypassable; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [5:0] _mem_ldq_e_T_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_ldst_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_fp_single = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_single; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [1:0] _mem_ldq_e_T_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:263:49, :912:37, :918:33] wire [39:0] _mem_ldq_e_T_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:263:49, :912:37, :918:33] wire [23:0] _mem_ldq_e_T_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 24'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_youngest_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_youngest_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:263:49, :912:37, :918:33] wire [4:0] _mem_ldq_e_T_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 5'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire [63:0] _mem_ldq_e_T_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :912:37, :918:33] wire _mem_ldq_e_T_1_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_uopc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uopc : _mem_ldq_e_T_bits_uop_uopc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_bits_uop_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_bits_uop_debug_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_bits_uop_is_rvc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_bits_uop_debug_pc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iq_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type : _mem_ldq_e_T_bits_uop_iq_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [9:0] _mem_ldq_e_T_1_bits_uop_fu_code = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code : _mem_ldq_e_T_bits_uop_fu_code; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_ctrl_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_br_type : _mem_ldq_e_T_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_load = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_load : _mem_ldq_e_T_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_sta = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_sta : _mem_ldq_e_T_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ctrl_is_std = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ctrl_is_std : _mem_ldq_e_T_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_iw_state = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_state : _mem_ldq_e_T_bits_uop_iw_state; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_br = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_br : _mem_ldq_e_T_bits_uop_is_br; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jalr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jalr : _mem_ldq_e_T_bits_uop_is_jalr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_jal = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_jal : _mem_ldq_e_T_bits_uop_is_jal; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_bits_uop_is_sfb; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [15:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_bits_uop_br_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_bits_uop_br_tag; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_bits_uop_ftq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_bits_uop_edge_inst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_bits_uop_pc_lob; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_bits_uop_taken; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_bits_uop_imm_packed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [11:0] _mem_ldq_e_T_1_bits_uop_csr_addr = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_addr : _mem_ldq_e_T_bits_uop_csr_addr; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_bits_uop_rob_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_bits_uop_ldq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_bits_uop_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_bits_uop_rxq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_bits_uop_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_bits_uop_prs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_bits_uop_prs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_bits_uop_prs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_bits_uop_ppred; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_bits_uop_prs1_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_bits_uop_prs2_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_bits_uop_prs3_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_bits_uop_ppred_busy; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_bits_uop_stale_pdst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_bits_uop_exception; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_bits_uop_exc_cause; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bypassable = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bypassable : _mem_ldq_e_T_bits_uop_bypassable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_bits_uop_mem_cmd; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_bits_uop_mem_size; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_bits_uop_mem_signed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_bits_uop_is_fence; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_bits_uop_is_fencei; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_bits_uop_is_amo; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_bits_uop_uses_ldq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_bits_uop_uses_stq; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_bits_uop_is_unique; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_bits_uop_ldst; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_bits_uop_lrs1; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_bits_uop_lrs2; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_bits_uop_lrs3; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_ldst_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_val : _mem_ldq_e_T_bits_uop_ldst_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_bits_uop_dst_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_bits_uop_frs3_en; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_bits_uop_fp_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_fp_single = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_single : _mem_ldq_e_T_bits_uop_fp_single; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_bits_addr_valid; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_bits_addr_bits; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_bits_addr_is_virtual; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_bits_executed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_bits_succeeded; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_bits_order_fail; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_bits_observed; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [23:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_bits_st_dep_mask; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_youngest_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_youngest_stq_idx : _mem_ldq_e_T_bits_youngest_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_bits_forward_std_val; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [4:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_bits_forward_stq_idx; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_bits_debug_wb_data; // @[lsu.scala:263:49, :913:37, :917:33, :918:33] wire _mem_ldq_e_T_2_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_uopc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uopc : _mem_ldq_e_T_1_bits_uop_uopc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iq_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iq_type : _mem_ldq_e_T_1_bits_uop_iq_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [9:0] _mem_ldq_e_T_2_bits_uop_fu_code = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fu_code : _mem_ldq_e_T_1_bits_uop_fu_code; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_ctrl_br_type = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_br_type : _mem_ldq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_ldq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_ldq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_ldq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_ldq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_ldq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_load = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_load : _mem_ldq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_sta = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_ldq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ctrl_is_std = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ctrl_is_std : _mem_ldq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_iw_state = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_state : _mem_ldq_e_T_1_bits_uop_iw_state; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_ldq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_br = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_br : _mem_ldq_e_T_1_bits_uop_is_br; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jalr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jalr : _mem_ldq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_jal = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_jal : _mem_ldq_e_T_1_bits_uop_is_jal; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [15:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [11:0] _mem_ldq_e_T_2_bits_uop_csr_addr = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_csr_addr : _mem_ldq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bypassable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bypassable : _mem_ldq_e_T_1_bits_uop_bypassable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_ldst_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_ldst_val : _mem_ldq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_fp_single = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_fp_single : _mem_ldq_e_T_1_bits_uop_fp_single; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [23:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_youngest_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_youngest_stq_idx : _mem_ldq_e_T_1_bits_youngest_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [4:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_incoming_0 ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:263:49, :910:37, :916:33, :917:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_2_valid; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_uopc = _mem_ldq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :916:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_iq_type = _mem_ldq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :916:33] wire [9:0] mem_ldq_e_0_bits_uop_fu_code = _mem_ldq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_ctrl_br_type = _mem_ldq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_ctrl_op1_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_op2_sel = _mem_ldq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_imm_sel = _mem_ldq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ctrl_op_fcn = _mem_ldq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_fcn_dw = _mem_ldq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :916:33] wire [2:0] mem_ldq_e_0_bits_uop_ctrl_csr_cmd = _mem_ldq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_load = _mem_ldq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_sta = _mem_ldq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ctrl_is_std = _mem_ldq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_iw_state = _mem_ldq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p1_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_iw_p2_poisoned = _mem_ldq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_br = _mem_ldq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jalr = _mem_ldq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_jal = _mem_ldq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :916:33] wire [15:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :916:33] wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :916:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :916:33] wire [11:0] mem_ldq_e_0_bits_uop_csr_addr = _mem_ldq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :916:33] wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bypassable = _mem_ldq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :916:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_ldst_val = _mem_ldq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_fp_single = _mem_ldq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :916:33] wire [1:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :916:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:263:49, :916:33] wire [23:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_youngest_stq_idx = _mem_ldq_e_T_2_bits_youngest_stq_idx; // @[lsu.scala:263:49, :916:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:263:49, :916:33] wire [4:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:263:49, :916:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :916:33] wire [23:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:263:49] wire _GEN_301 = fired_stad_incoming_0 | fired_sta_incoming_0; // @[lsu.scala:263:49, :920:57] wire _mem_stq_e_T; // @[lsu.scala:920:57] assign _mem_stq_e_T = _GEN_301; // @[lsu.scala:920:57] wire _do_st_search_T; // @[lsu.scala:1015:60] assign _do_st_search_T = _GEN_301; // @[lsu.scala:920:57, :1015:60] wire _lcam_addr_T; // @[lsu.scala:1026:61] assign _lcam_addr_T = _GEN_301; // @[lsu.scala:920:57, :1026:61] wire _lcam_stq_idx_T; // @[lsu.scala:1041:50] assign _lcam_stq_idx_T = _GEN_301; // @[lsu.scala:920:57, :1041:50] wire _mem_stq_e_T_1_valid = fired_sta_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_uopc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iq_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [9:0] _mem_stq_e_T_1_bits_uop_fu_code = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_ctrl_br_type = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_ctrl_op1_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_op2_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_imm_sel = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ctrl_op_fcn = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :914:37, :922:33] wire [2:0] _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_load = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_sta = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ctrl_is_std = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_iw_state = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_poisoned = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_br = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_br; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jalr = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jalr; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_jal = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_jal; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:263:49, :914:37, :922:33] wire [15:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:263:49, :914:37, :922:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [11:0] _mem_stq_e_T_1_bits_uop_csr_addr = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:263:49, :914:37, :922:33] wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bypassable = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bypassable; // @[lsu.scala:263:49, :914:37, :922:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_ldst_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_ldst_val; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_fp_single = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_fp_single; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_sta_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire [1:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_sta_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_sta_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_data_valid = fired_sta_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_sta_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_committed = fired_sta_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_1_bits_succeeded = fired_sta_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:263:49, :914:37, :922:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_sta_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:263:49, :914:37, :922:33] wire _mem_stq_e_T_2_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_1_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_uopc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uopc : _mem_stq_e_T_1_bits_uop_uopc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [31:0] _mem_stq_e_T_2_bits_uop_debug_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_rvc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_uop_debug_pc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_iq_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iq_type : _mem_stq_e_T_1_bits_uop_iq_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [9:0] _mem_stq_e_T_2_bits_uop_fu_code = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fu_code : _mem_stq_e_T_1_bits_uop_fu_code; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_ctrl_br_type = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_br_type : _mem_stq_e_T_1_bits_uop_ctrl_br_type; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_ctrl_op1_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op1_sel : _mem_stq_e_T_1_bits_uop_ctrl_op1_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_op2_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op2_sel : _mem_stq_e_T_1_bits_uop_ctrl_op2_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_imm_sel = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_imm_sel : _mem_stq_e_T_1_bits_uop_ctrl_imm_sel; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ctrl_op_fcn = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_op_fcn : _mem_stq_e_T_1_bits_uop_ctrl_op_fcn; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_fcn_dw : _mem_stq_e_T_1_bits_uop_ctrl_fcn_dw; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [2:0] _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_csr_cmd : _mem_stq_e_T_1_bits_uop_ctrl_csr_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_load = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_load : _mem_stq_e_T_1_bits_uop_ctrl_is_load; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_sta = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_sta : _mem_stq_e_T_1_bits_uop_ctrl_is_sta; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ctrl_is_std = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ctrl_is_std : _mem_stq_e_T_1_bits_uop_ctrl_is_std; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_iw_state = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_state : _mem_stq_e_T_1_bits_uop_iw_state; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p1_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p1_poisoned : _mem_stq_e_T_1_bits_uop_iw_p1_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_iw_p2_poisoned = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_iw_p2_poisoned : _mem_stq_e_T_1_bits_uop_iw_p2_poisoned; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_br = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_br : _mem_stq_e_T_1_bits_uop_is_br; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jalr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jalr : _mem_stq_e_T_1_bits_uop_is_jalr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_jal = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_jal : _mem_stq_e_T_1_bits_uop_is_jal; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sfb = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [15:0] _mem_stq_e_T_2_bits_uop_br_mask = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [3:0] _mem_stq_e_T_2_bits_uop_br_tag = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ftq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_edge_inst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_pc_lob = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_taken = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [19:0] _mem_stq_e_T_2_bits_uop_imm_packed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [11:0] _mem_stq_e_T_2_bits_uop_csr_addr = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_csr_addr : _mem_stq_e_T_1_bits_uop_csr_addr; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_rob_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ldq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_stq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_rxq_idx = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_prs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_prs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_prs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_ppred = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs1_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs2_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_prs3_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ppred_busy = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [6:0] _mem_stq_e_T_2_bits_uop_stale_pdst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_exception = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_uop_exc_cause = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bypassable = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bypassable : _mem_stq_e_T_1_bits_uop_bypassable; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [4:0] _mem_stq_e_T_2_bits_uop_mem_cmd = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_mem_size = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_mem_signed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fence = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_fencei = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_amo = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_ldq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_uses_stq = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_sys_pc2epc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_is_unique = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_flush_on_commit = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_is_rs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_ldst = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs1 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs2 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [5:0] _mem_stq_e_T_2_bits_uop_lrs3 = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_ldst_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_ldst_val : _mem_stq_e_T_1_bits_uop_ldst_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_dst_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs1_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_lrs2_rtype = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_frs3_en = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_val = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_fp_single = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_fp_single : _mem_stq_e_T_1_bits_uop_fp_single; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_pf_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ae_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_xcpt_ma_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_debug_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_uop_bp_xcpt_if = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_fsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [1:0] _mem_stq_e_T_2_bits_uop_debug_tsrc = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [39:0] _mem_stq_e_T_2_bits_addr_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_addr_is_virtual = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_data_valid = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_data_bits = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_committed = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_1_bits_committed; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire _mem_stq_e_T_2_bits_succeeded = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire [63:0] _mem_stq_e_T_2_bits_debug_wb_data = _mem_stq_e_T ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:911:37, :920:{33,57}, :922:33] wire mem_stq_e_0_valid = _mem_stq_e_T_2_valid; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_uopc = _mem_stq_e_T_2_bits_uop_uopc; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_2_bits_uop_inst; // @[lsu.scala:263:49, :920:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_iq_type = _mem_stq_e_T_2_bits_uop_iq_type; // @[lsu.scala:263:49, :920:33] wire [9:0] mem_stq_e_0_bits_uop_fu_code = _mem_stq_e_T_2_bits_uop_fu_code; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_ctrl_br_type = _mem_stq_e_T_2_bits_uop_ctrl_br_type; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_ctrl_op1_sel = _mem_stq_e_T_2_bits_uop_ctrl_op1_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_op2_sel = _mem_stq_e_T_2_bits_uop_ctrl_op2_sel; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_imm_sel = _mem_stq_e_T_2_bits_uop_ctrl_imm_sel; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ctrl_op_fcn = _mem_stq_e_T_2_bits_uop_ctrl_op_fcn; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_fcn_dw = _mem_stq_e_T_2_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :920:33] wire [2:0] mem_stq_e_0_bits_uop_ctrl_csr_cmd = _mem_stq_e_T_2_bits_uop_ctrl_csr_cmd; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_load = _mem_stq_e_T_2_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_sta = _mem_stq_e_T_2_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ctrl_is_std = _mem_stq_e_T_2_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_iw_state = _mem_stq_e_T_2_bits_uop_iw_state; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p1_poisoned = _mem_stq_e_T_2_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_iw_p2_poisoned = _mem_stq_e_T_2_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_br = _mem_stq_e_T_2_bits_uop_is_br; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jalr = _mem_stq_e_T_2_bits_uop_is_jalr; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_jal = _mem_stq_e_T_2_bits_uop_is_jal; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:263:49, :920:33] wire [15:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_2_bits_uop_br_mask; // @[lsu.scala:263:49, :920:33] wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_2_bits_uop_br_tag; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_2_bits_uop_taken; // @[lsu.scala:263:49, :920:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:263:49, :920:33] wire [11:0] mem_stq_e_0_bits_uop_csr_addr = _mem_stq_e_T_2_bits_uop_csr_addr; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_2_bits_uop_pdst; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_2_bits_uop_prs1; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_2_bits_uop_prs2; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_2_bits_uop_prs3; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_2_bits_uop_ppred; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:263:49, :920:33] wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_2_bits_uop_exception; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bypassable = _mem_stq_e_T_2_bits_uop_bypassable; // @[lsu.scala:263:49, :920:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_2_bits_uop_mem_size; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_2_bits_uop_is_fence; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_2_bits_uop_is_amo; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_2_bits_uop_is_unique; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_2_bits_uop_ldst; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_2_bits_uop_lrs1; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_2_bits_uop_lrs2; // @[lsu.scala:263:49, :920:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_2_bits_uop_lrs3; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_ldst_val = _mem_stq_e_T_2_bits_uop_ldst_val; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_2_bits_uop_fp_val; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_fp_single = _mem_stq_e_T_2_bits_uop_fp_single; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:263:49, :920:33] wire [1:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_2_bits_addr_valid; // @[lsu.scala:263:49, :920:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_2_bits_addr_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_2_bits_data_valid; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_2_bits_data_bits; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_2_bits_committed; // @[lsu.scala:263:49, :920:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_2_bits_succeeded; // @[lsu.scala:263:49, :920:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_2_bits_debug_wb_data; // @[lsu.scala:263:49, :920:33] wire [15:0] _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25] wire [15:0] mem_stdf_uop_out_br_mask; // @[util.scala:96:23] wire [15:0] _mem_stdf_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _mem_stdf_uop_out_br_mask_T_1 = io_core_fp_stdata_bits_uop_br_mask_0 & _mem_stdf_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign mem_stdf_uop_out_br_mask = _mem_stdf_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [6:0] mem_stdf_uop_uopc; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_inst; // @[lsu.scala:923:37] reg [31:0] mem_stdf_uop_debug_inst; // @[lsu.scala:923:37] reg mem_stdf_uop_is_rvc; // @[lsu.scala:923:37] reg [39:0] mem_stdf_uop_debug_pc; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_iq_type; // @[lsu.scala:923:37] reg [9:0] mem_stdf_uop_fu_code; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_ctrl_br_type; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_ctrl_op1_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_op2_sel; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_imm_sel; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ctrl_op_fcn; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_fcn_dw; // @[lsu.scala:923:37] reg [2:0] mem_stdf_uop_ctrl_csr_cmd; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_load; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_sta; // @[lsu.scala:923:37] reg mem_stdf_uop_ctrl_is_std; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_iw_state; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p1_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_iw_p2_poisoned; // @[lsu.scala:923:37] reg mem_stdf_uop_is_br; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jalr; // @[lsu.scala:923:37] reg mem_stdf_uop_is_jal; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sfb; // @[lsu.scala:923:37] reg [15:0] mem_stdf_uop_br_mask; // @[lsu.scala:923:37] reg [3:0] mem_stdf_uop_br_tag; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ftq_idx; // @[lsu.scala:923:37] reg mem_stdf_uop_edge_inst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_pc_lob; // @[lsu.scala:923:37] reg mem_stdf_uop_taken; // @[lsu.scala:923:37] reg [19:0] mem_stdf_uop_imm_packed; // @[lsu.scala:923:37] reg [11:0] mem_stdf_uop_csr_addr; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_rob_idx; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ldq_idx; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_stq_idx; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_rxq_idx; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_pdst; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_prs1; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_prs2; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_prs3; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_ppred; // @[lsu.scala:923:37] reg mem_stdf_uop_prs1_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs2_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_prs3_busy; // @[lsu.scala:923:37] reg mem_stdf_uop_ppred_busy; // @[lsu.scala:923:37] reg [6:0] mem_stdf_uop_stale_pdst; // @[lsu.scala:923:37] reg mem_stdf_uop_exception; // @[lsu.scala:923:37] reg [63:0] mem_stdf_uop_exc_cause; // @[lsu.scala:923:37] reg mem_stdf_uop_bypassable; // @[lsu.scala:923:37] reg [4:0] mem_stdf_uop_mem_cmd; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_mem_size; // @[lsu.scala:923:37] reg mem_stdf_uop_mem_signed; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fence; // @[lsu.scala:923:37] reg mem_stdf_uop_is_fencei; // @[lsu.scala:923:37] reg mem_stdf_uop_is_amo; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_ldq; // @[lsu.scala:923:37] reg mem_stdf_uop_uses_stq; // @[lsu.scala:923:37] reg mem_stdf_uop_is_sys_pc2epc; // @[lsu.scala:923:37] reg mem_stdf_uop_is_unique; // @[lsu.scala:923:37] reg mem_stdf_uop_flush_on_commit; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_is_rs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_ldst; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs1; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs2; // @[lsu.scala:923:37] reg [5:0] mem_stdf_uop_lrs3; // @[lsu.scala:923:37] reg mem_stdf_uop_ldst_val; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_dst_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs1_rtype; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_lrs2_rtype; // @[lsu.scala:923:37] reg mem_stdf_uop_frs3_en; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_val; // @[lsu.scala:923:37] reg mem_stdf_uop_fp_single; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_pf_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ae_if; // @[lsu.scala:923:37] reg mem_stdf_uop_xcpt_ma_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_debug_if; // @[lsu.scala:923:37] reg mem_stdf_uop_bp_xcpt_if; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_fsrc; // @[lsu.scala:923:37] reg [1:0] mem_stdf_uop_debug_tsrc; // @[lsu.scala:923:37] reg mem_tlb_miss_0; // @[lsu.scala:926:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:927:41] reg [39:0] mem_paddr_0; // @[lsu.scala:928:41] reg clr_bsy_valid_0; // @[lsu.scala:931:32] reg [6:0] clr_bsy_rob_idx_0; // @[lsu.scala:932:28] assign io_core_clr_bsy_0_bits_0 = clr_bsy_rob_idx_0; // @[lsu.scala:201:7, :932:28] reg [15:0] clr_bsy_brmask_0; // @[lsu.scala:933:28] wire _clr_bsy_valid_0_T = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29] wire _clr_bsy_valid_0_T_1 = mem_stq_incoming_e_0_valid & _clr_bsy_valid_0_T; // @[lsu.scala:911:37, :942:68, :943:29] wire _clr_bsy_valid_0_T_2 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29] wire _clr_bsy_valid_0_T_3 = _clr_bsy_valid_0_T_1 & _clr_bsy_valid_0_T_2; // @[lsu.scala:942:68, :943:68, :944:29] wire [15:0] _GEN_302 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:118:51] wire [15:0] _clr_bsy_valid_0_T_4; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_4 = _GEN_302; // @[util.scala:118:51] wire [15:0] _clr_bsy_valid_0_T_13; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_13 = _GEN_302; // @[util.scala:118:51] wire [15:0] _clr_bsy_valid_0_T_22; // @[util.scala:118:51] assign _clr_bsy_valid_0_T_22 = _GEN_302; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_5 = |_clr_bsy_valid_0_T_4; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_6 = ~_clr_bsy_valid_0_T_5; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_7 = _clr_bsy_valid_0_T_3 & _clr_bsy_valid_0_T_6; // @[lsu.scala:943:68, :944:68, :945:29] wire [15:0] _clr_bsy_brmask_0_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _clr_bsy_brmask_0_T_1 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_8 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:911:37, :949:69] wire _clr_bsy_valid_0_T_9 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :951:29] wire _clr_bsy_valid_0_T_10 = _clr_bsy_valid_0_T_8 & _clr_bsy_valid_0_T_9; // @[lsu.scala:949:69, :950:69, :951:29] wire _clr_bsy_valid_0_T_11 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :952:29] wire _clr_bsy_valid_0_T_12 = _clr_bsy_valid_0_T_10 & _clr_bsy_valid_0_T_11; // @[lsu.scala:950:69, :951:69, :952:29] wire _clr_bsy_valid_0_T_14 = |_clr_bsy_valid_0_T_13; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_15 = ~_clr_bsy_valid_0_T_14; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_16 = _clr_bsy_valid_0_T_12 & _clr_bsy_valid_0_T_15; // @[lsu.scala:951:69, :952:69, :953:29] wire [15:0] _clr_bsy_brmask_0_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _clr_bsy_brmask_0_T_3 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_2; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_17 = mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:911:37, :957:74] wire _clr_bsy_valid_0_T_18 = ~mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:911:37, :959:29] wire _clr_bsy_valid_0_T_19 = _clr_bsy_valid_0_T_17 & _clr_bsy_valid_0_T_18; // @[lsu.scala:957:74, :958:74, :959:29] wire _clr_bsy_valid_0_T_20 = ~mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:911:37, :944:29, :960:29] wire _clr_bsy_valid_0_T_21 = _clr_bsy_valid_0_T_19 & _clr_bsy_valid_0_T_20; // @[lsu.scala:958:74, :959:74, :960:29] wire _clr_bsy_valid_0_T_23 = |_clr_bsy_valid_0_T_22; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_24 = ~_clr_bsy_valid_0_T_23; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_25 = _clr_bsy_valid_0_T_21 & _clr_bsy_valid_0_T_24; // @[lsu.scala:959:74, :960:74, :961:29] wire [15:0] _clr_bsy_brmask_0_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _clr_bsy_brmask_0_T_5 = mem_stq_incoming_e_0_bits_uop_br_mask & _clr_bsy_brmask_0_T_4; // @[util.scala:85:{25,27}] wire [15:0] _clr_bsy_brmask_0_T_6 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _clr_bsy_brmask_0_T_7 = mem_incoming_uop_0_br_mask & _clr_bsy_brmask_0_T_6; // @[util.scala:85:{25,27}] wire _clr_bsy_valid_0_T_26 = mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:914:37, :969:63] wire _clr_bsy_valid_0_T_27 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :971:29] wire _clr_bsy_valid_0_T_28 = _clr_bsy_valid_0_T_26 & _clr_bsy_valid_0_T_27; // @[lsu.scala:969:63, :970:63, :971:29] wire _clr_bsy_valid_0_T_29 = ~mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:914:37, :972:29] wire _clr_bsy_valid_0_T_30 = _clr_bsy_valid_0_T_28 & _clr_bsy_valid_0_T_29; // @[lsu.scala:970:63, :971:63, :972:29] wire [15:0] _clr_bsy_valid_0_T_31 = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_bits_uop_br_mask; // @[util.scala:118:51] wire _clr_bsy_valid_0_T_32 = |_clr_bsy_valid_0_T_31; // @[util.scala:118:{51,59}] wire _clr_bsy_valid_0_T_33 = ~_clr_bsy_valid_0_T_32; // @[util.scala:118:59] wire _clr_bsy_valid_0_T_34 = _clr_bsy_valid_0_T_30 & _clr_bsy_valid_0_T_33; // @[lsu.scala:971:63, :972:63, :973:29] wire [15:0] _clr_bsy_brmask_0_T_8 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _clr_bsy_brmask_0_T_9 = mem_stq_retry_e_bits_uop_br_mask & _clr_bsy_brmask_0_T_8; // @[util.scala:85:{25,27}] wire [15:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_bsy_brmask_0; // @[util.scala:118:51] wire _io_core_clr_bsy_0_valid_T_1 = |_io_core_clr_bsy_0_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = ~_io_core_clr_bsy_0_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_0_valid_T_3 = clr_bsy_valid_0 & _io_core_clr_bsy_0_valid_T_2; // @[lsu.scala:931:32, :978:50, :979:32] wire _io_core_clr_bsy_0_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :980:32] wire _io_core_clr_bsy_0_valid_T_5 = _io_core_clr_bsy_0_valid_T_3 & _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:978:50, :979:87, :980:32] reg io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:62] wire _io_core_clr_bsy_0_valid_T_6 = ~io_core_clr_bsy_0_valid_REG; // @[lsu.scala:980:{54,62}] wire _io_core_clr_bsy_0_valid_T_7 = _io_core_clr_bsy_0_valid_T_5 & _io_core_clr_bsy_0_valid_T_6; // @[lsu.scala:979:87, :980:{51,54}] reg io_core_clr_bsy_0_valid_REG_1; // @[lsu.scala:980:101] reg io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:93] wire _io_core_clr_bsy_0_valid_T_8 = ~io_core_clr_bsy_0_valid_REG_2; // @[lsu.scala:980:{85,93}] assign _io_core_clr_bsy_0_valid_T_9 = _io_core_clr_bsy_0_valid_T_7 & _io_core_clr_bsy_0_valid_T_8; // @[lsu.scala:980:{51,82,85}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_9; // @[lsu.scala:201:7, :980:82] reg stdf_clr_bsy_valid; // @[lsu.scala:984:37] reg [6:0] stdf_clr_bsy_rob_idx; // @[lsu.scala:985:33] assign io_core_clr_bsy_1_bits_0 = stdf_clr_bsy_rob_idx; // @[lsu.scala:201:7, :985:33] reg [15:0] stdf_clr_bsy_brmask; // @[lsu.scala:986:33] wire _stdf_clr_bsy_valid_T = _GEN[mem_stdf_uop_stq_idx] & _GEN_83[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62] wire _stdf_clr_bsy_valid_T_1 = ~_GEN_85[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :994:29] wire _stdf_clr_bsy_valid_T_2 = _stdf_clr_bsy_valid_T & _stdf_clr_bsy_valid_T_1; // @[lsu.scala:992:62, :993:62, :994:29] wire _stdf_clr_bsy_valid_T_3 = ~_GEN_57[mem_stdf_uop_stq_idx]; // @[lsu.scala:222:42, :923:37, :992:62, :995:29] wire _stdf_clr_bsy_valid_T_4 = _stdf_clr_bsy_valid_T_2 & _stdf_clr_bsy_valid_T_3; // @[lsu.scala:993:62, :994:62, :995:29] wire [15:0] _stdf_clr_bsy_valid_T_5 = io_core_brupdate_b1_mispredict_mask_0 & mem_stdf_uop_br_mask; // @[util.scala:118:51] wire _stdf_clr_bsy_valid_T_6 = |_stdf_clr_bsy_valid_T_5; // @[util.scala:118:{51,59}] wire _stdf_clr_bsy_valid_T_7 = ~_stdf_clr_bsy_valid_T_6; // @[util.scala:118:59] wire _stdf_clr_bsy_valid_T_8 = _stdf_clr_bsy_valid_T_4 & _stdf_clr_bsy_valid_T_7; // @[lsu.scala:994:62, :995:62, :996:29] wire [15:0] _stdf_clr_bsy_brmask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _stdf_clr_bsy_brmask_T_1 = mem_stdf_uop_br_mask & _stdf_clr_bsy_brmask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stdf_clr_bsy_brmask; // @[util.scala:118:51] wire _io_core_clr_bsy_1_valid_T_1 = |_io_core_clr_bsy_1_valid_T; // @[util.scala:118:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = ~_io_core_clr_bsy_1_valid_T_1; // @[util.scala:118:59] wire _io_core_clr_bsy_1_valid_T_3 = stdf_clr_bsy_valid & _io_core_clr_bsy_1_valid_T_2; // @[lsu.scala:984:37, :1003:57, :1004:37] wire _io_core_clr_bsy_1_valid_T_4 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1005:37] wire _io_core_clr_bsy_1_valid_T_5 = _io_core_clr_bsy_1_valid_T_3 & _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1003:57, :1004:94, :1005:37] reg io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:67] wire _io_core_clr_bsy_1_valid_T_6 = ~io_core_clr_bsy_1_valid_REG; // @[lsu.scala:1005:{59,67}] wire _io_core_clr_bsy_1_valid_T_7 = _io_core_clr_bsy_1_valid_T_5 & _io_core_clr_bsy_1_valid_T_6; // @[lsu.scala:1004:94, :1005:{56,59}] reg io_core_clr_bsy_1_valid_REG_1; // @[lsu.scala:1005:106] reg io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:98] wire _io_core_clr_bsy_1_valid_T_8 = ~io_core_clr_bsy_1_valid_REG_2; // @[lsu.scala:1005:{90,98}] assign _io_core_clr_bsy_1_valid_T_9 = _io_core_clr_bsy_1_valid_T_7 & _io_core_clr_bsy_1_valid_T_8; // @[lsu.scala:1005:{56,87,90}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_9; // @[lsu.scala:201:7, :1005:87] wire _do_st_search_T_1 = _do_st_search_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1015:{60,85}] wire _do_st_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1015:111] wire _do_st_search_T_3 = _do_st_search_T_1 & _do_st_search_T_2; // @[lsu.scala:1015:{85,108,111}] wire do_st_search_0 = _do_st_search_T_3; // @[lsu.scala:263:49, :1015:108] wire _GEN_303 = fired_load_incoming_0 | fired_load_retry_0; // @[lsu.scala:263:49, :1017:61] wire _do_ld_search_T; // @[lsu.scala:1017:61] assign _do_ld_search_T = _GEN_303; // @[lsu.scala:1017:61] wire _can_forward_T; // @[lsu.scala:1046:32] assign _can_forward_T = _GEN_303; // @[lsu.scala:1017:61, :1046:32] wire _do_ld_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:926:41, :943:29, :1017:88] wire _do_ld_search_T_2 = _do_ld_search_T & _do_ld_search_T_1; // @[lsu.scala:1017:{61,85,88}] wire _do_ld_search_T_3 = _do_ld_search_T_2 | fired_load_wakeup_0; // @[lsu.scala:263:49, :1017:{85,106}] wire do_ld_search_0 = _do_ld_search_T_3; // @[lsu.scala:263:49, :1017:106] wire _lcam_addr_T_1 = _lcam_addr_T | fired_sta_retry_0; // @[lsu.scala:263:49, :1026:{61,86}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1027:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1028:67] wire [39:0] _lcam_addr_T_2 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:901:37, :928:41, :1028:{41,67}] wire [39:0] _lcam_addr_T_3 = _lcam_addr_T_1 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_2; // @[lsu.scala:1026:{37,86}, :1027:45, :1028:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_3; // @[lsu.scala:263:49, :1026:37] wire [6:0] _lcam_uop_T_uopc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_uopc : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:263:49, :1031:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_iq_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iq_type : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [9:0] _lcam_uop_T_fu_code = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fu_code : 10'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_ctrl_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_br_type : 4'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_ctrl_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op1_sel : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op2_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_imm_sel : 3'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ctrl_op_fcn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_op_fcn : 5'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_fcn_dw; // @[lsu.scala:263:49, :1031:37] wire [2:0] _lcam_uop_T_ctrl_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ctrl_csr_cmd : 3'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_load = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_load; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_sta = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_sta; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ctrl_is_std = do_ld_search_0 & mem_ldq_e_0_bits_uop_ctrl_is_std; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_iw_state = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_state : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p1_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_iw_p2_poisoned = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_poisoned; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_br = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_br; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jalr = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jalr; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_jal = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_jal; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:263:49, :1031:37] wire [15:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 16'h0; // @[lsu.scala:263:49, :1031:37] wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:263:49, :1031:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:263:49, :1031:37] wire [11:0] _lcam_uop_T_csr_addr = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_addr : 12'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:263:49, :1031:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bypassable = do_ld_search_0 & mem_ldq_e_0_bits_uop_bypassable; // @[lsu.scala:263:49, :1031:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_ldst_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_val; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h2; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_fp_single = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_single; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:263:49, :1031:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [1:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 2'h0; // @[lsu.scala:263:49, :1031:37] wire [6:0] _lcam_uop_T_1_uopc = do_st_search_0 ? mem_stq_e_0_bits_uop_uopc : _lcam_uop_T_uopc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_iq_type = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type : _lcam_uop_T_iq_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [9:0] _lcam_uop_T_1_fu_code = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code : _lcam_uop_T_fu_code; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_ctrl_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_br_type : _lcam_uop_T_ctrl_br_type; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_ctrl_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op1_sel : _lcam_uop_T_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op2_sel : _lcam_uop_T_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_imm_sel : _lcam_uop_T_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ctrl_op_fcn = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_op_fcn : _lcam_uop_T_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_fcn_dw : _lcam_uop_T_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [2:0] _lcam_uop_T_1_ctrl_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_csr_cmd : _lcam_uop_T_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_load = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_load : _lcam_uop_T_ctrl_is_load; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_sta = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_sta : _lcam_uop_T_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ctrl_is_std = do_st_search_0 ? mem_stq_e_0_bits_uop_ctrl_is_std : _lcam_uop_T_ctrl_is_std; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_iw_state = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_state : _lcam_uop_T_iw_state; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p1_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_poisoned : _lcam_uop_T_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_iw_p2_poisoned = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_poisoned : _lcam_uop_T_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_br = do_st_search_0 ? mem_stq_e_0_bits_uop_is_br : _lcam_uop_T_is_br; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jalr = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jalr : _lcam_uop_T_is_jalr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_jal = do_st_search_0 ? mem_stq_e_0_bits_uop_is_jal : _lcam_uop_T_is_jal; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [15:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [11:0] _lcam_uop_T_1_csr_addr = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_addr : _lcam_uop_T_csr_addr; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bypassable = do_st_search_0 ? mem_stq_e_0_bits_uop_bypassable : _lcam_uop_T_bypassable; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_ldst_val = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_val : _lcam_uop_T_ldst_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_fp_single = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_single : _lcam_uop_T_fp_single; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [1:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:263:49, :1030:37, :1031:37] wire [6:0] lcam_uop_0_uopc = _lcam_uop_T_1_uopc; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:263:49, :1030:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:263:49, :1030:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_iq_type = _lcam_uop_T_1_iq_type; // @[lsu.scala:263:49, :1030:37] wire [9:0] lcam_uop_0_fu_code = _lcam_uop_T_1_fu_code; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_ctrl_br_type = _lcam_uop_T_1_ctrl_br_type; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_ctrl_op1_sel = _lcam_uop_T_1_ctrl_op1_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_op2_sel = _lcam_uop_T_1_ctrl_op2_sel; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_imm_sel = _lcam_uop_T_1_ctrl_imm_sel; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ctrl_op_fcn = _lcam_uop_T_1_ctrl_op_fcn; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_fcn_dw = _lcam_uop_T_1_ctrl_fcn_dw; // @[lsu.scala:263:49, :1030:37] wire [2:0] lcam_uop_0_ctrl_csr_cmd = _lcam_uop_T_1_ctrl_csr_cmd; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_load = _lcam_uop_T_1_ctrl_is_load; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_sta = _lcam_uop_T_1_ctrl_is_sta; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ctrl_is_std = _lcam_uop_T_1_ctrl_is_std; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_iw_state = _lcam_uop_T_1_iw_state; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p1_poisoned = _lcam_uop_T_1_iw_p1_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_iw_p2_poisoned = _lcam_uop_T_1_iw_p2_poisoned; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_br = _lcam_uop_T_1_is_br; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jalr = _lcam_uop_T_1_is_jalr; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_jal = _lcam_uop_T_1_is_jal; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:263:49, :1030:37] wire [15:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:263:49, :1030:37] wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:263:49, :1030:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:263:49, :1030:37] wire [11:0] lcam_uop_0_csr_addr = _lcam_uop_T_1_csr_addr; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:263:49, :1030:37] wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:263:49, :1030:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bypassable = _lcam_uop_T_1_bypassable; // @[lsu.scala:263:49, :1030:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:263:49, :1030:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_ldst_val = _lcam_uop_T_1_ldst_val; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_fp_single = _lcam_uop_T_1_fp_single; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:263:49, :1030:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:263:49, :1030:37] wire [1:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:263:49, :1030:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1665:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:263:49, :1665:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:263:49, :1667:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:263:49, :1667:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:263:49, :1668:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:263:49, :1668:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:263:49, :1669:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:263:49, :1669:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:263:49, :1670:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [4:0] lcam_ldq_idx_REG; // @[lsu.scala:1038:58] reg [4:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1039:58] wire [4:0] _lcam_ldq_idx_T = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 5'h0; // @[lsu.scala:263:49, :1039:{26,58}] wire [4:0] _lcam_ldq_idx_T_1 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T; // @[lsu.scala:263:49, :1038:{26,58}, :1039:26] wire [4:0] _lcam_ldq_idx_T_2 = fired_load_incoming_0 ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_1; // @[lsu.scala:263:49, :909:37, :1037:26, :1038:26] wire [4:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_2; // @[lsu.scala:263:49, :1037:26] wire [4:0] _can_forward_T_2 = lcam_ldq_idx_0; // @[lsu.scala:263:49] reg [4:0] lcam_stq_idx_REG; // @[lsu.scala:1043:58] wire [4:0] _lcam_stq_idx_T_1 = fired_sta_retry_0 ? lcam_stq_idx_REG : 5'h0; // @[lsu.scala:263:49, :1043:{26,58}] wire [4:0] _lcam_stq_idx_T_2 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T_1; // @[lsu.scala:909:37, :1041:{26,50}, :1043:26] wire [4:0] lcam_stq_idx_0 = _lcam_stq_idx_T_2; // @[lsu.scala:263:49, :1041:26] wire _can_forward_T_1 = ~mem_tlb_uncacheable_0; // @[lsu.scala:927:41, :1046:56] wire [4:0] _can_forward_T_3 = _can_forward_T_2; wire _can_forward_T_4 = ~_GEN_181[_can_forward_T_3]; // @[lsu.scala:263:49, :1047:7] wire _can_forward_T_5 = _can_forward_T ? _can_forward_T_1 : _can_forward_T_4; // @[lsu.scala:1046:{8,32,56}, :1047:7] wire _can_forward_WIRE_0 = _can_forward_T_5; // @[lsu.scala:263:49, :1046:8] wire can_forward_0; // @[lsu.scala:1045:29] wire ldst_addr_matches_0_0; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_1; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_2; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_3; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_4; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_5; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_6; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_7; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_8; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_9; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_10; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_11; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_12; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_13; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_14; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_15; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_16; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_17; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_18; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_19; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_20; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_21; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_22; // @[lsu.scala:1050:38] wire ldst_addr_matches_0_23; // @[lsu.scala:1050:38] wire ldst_forward_matches_0_0; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_1; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_2; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_3; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_4; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_5; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_6; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_7; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_8; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_9; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_10; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_11; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_12; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_13; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_14; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_15; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_16; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_17; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_18; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_19; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_20; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_21; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_22; // @[lsu.scala:1052:38] wire ldst_forward_matches_0_23; // @[lsu.scala:1052:38] wire _temp_bits_WIRE_1_24 = failed_loads_0; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_25 = failed_loads_1; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_26 = failed_loads_2; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_27 = failed_loads_3; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_28 = failed_loads_4; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_29 = failed_loads_5; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_30 = failed_loads_6; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_31 = failed_loads_7; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_32 = failed_loads_8; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_33 = failed_loads_9; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_34 = failed_loads_10; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_35 = failed_loads_11; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_36 = failed_loads_12; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_37 = failed_loads_13; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_38 = failed_loads_14; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_39 = failed_loads_15; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_40 = failed_loads_16; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_41 = failed_loads_17; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_42 = failed_loads_18; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_43 = failed_loads_19; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_44 = failed_loads_20; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_45 = failed_loads_21; // @[lsu.scala:1054:34, :1229:27] wire _temp_bits_WIRE_1_46 = failed_loads_22; // @[lsu.scala:1054:34, :1229:27] wire failed_loads_23; // @[lsu.scala:1054:34] wire _temp_bits_WIRE_1_47 = failed_loads_23; // @[lsu.scala:1054:34, :1229:27] wire nacking_loads_0; // @[lsu.scala:1055:34] wire nacking_loads_1; // @[lsu.scala:1055:34] wire nacking_loads_2; // @[lsu.scala:1055:34] wire nacking_loads_3; // @[lsu.scala:1055:34] wire nacking_loads_4; // @[lsu.scala:1055:34] wire nacking_loads_5; // @[lsu.scala:1055:34] wire nacking_loads_6; // @[lsu.scala:1055:34] wire nacking_loads_7; // @[lsu.scala:1055:34] wire nacking_loads_8; // @[lsu.scala:1055:34] wire nacking_loads_9; // @[lsu.scala:1055:34] wire nacking_loads_10; // @[lsu.scala:1055:34] wire nacking_loads_11; // @[lsu.scala:1055:34] wire nacking_loads_12; // @[lsu.scala:1055:34] wire nacking_loads_13; // @[lsu.scala:1055:34] wire nacking_loads_14; // @[lsu.scala:1055:34] wire nacking_loads_15; // @[lsu.scala:1055:34] wire nacking_loads_16; // @[lsu.scala:1055:34] wire nacking_loads_17; // @[lsu.scala:1055:34] wire nacking_loads_18; // @[lsu.scala:1055:34] wire nacking_loads_19; // @[lsu.scala:1055:34] wire nacking_loads_20; // @[lsu.scala:1055:34] wire nacking_loads_21; // @[lsu.scala:1055:34] wire nacking_loads_22; // @[lsu.scala:1055:34] wire nacking_loads_23; // @[lsu.scala:1055:34] reg s1_executing_loads_0; // @[lsu.scala:1057:35] reg s1_executing_loads_1; // @[lsu.scala:1057:35] reg s1_executing_loads_2; // @[lsu.scala:1057:35] reg s1_executing_loads_3; // @[lsu.scala:1057:35] reg s1_executing_loads_4; // @[lsu.scala:1057:35] reg s1_executing_loads_5; // @[lsu.scala:1057:35] reg s1_executing_loads_6; // @[lsu.scala:1057:35] reg s1_executing_loads_7; // @[lsu.scala:1057:35] reg s1_executing_loads_8; // @[lsu.scala:1057:35] reg s1_executing_loads_9; // @[lsu.scala:1057:35] reg s1_executing_loads_10; // @[lsu.scala:1057:35] reg s1_executing_loads_11; // @[lsu.scala:1057:35] reg s1_executing_loads_12; // @[lsu.scala:1057:35] reg s1_executing_loads_13; // @[lsu.scala:1057:35] reg s1_executing_loads_14; // @[lsu.scala:1057:35] reg s1_executing_loads_15; // @[lsu.scala:1057:35] reg s1_executing_loads_16; // @[lsu.scala:1057:35] reg s1_executing_loads_17; // @[lsu.scala:1057:35] reg s1_executing_loads_18; // @[lsu.scala:1057:35] reg s1_executing_loads_19; // @[lsu.scala:1057:35] reg s1_executing_loads_20; // @[lsu.scala:1057:35] reg s1_executing_loads_21; // @[lsu.scala:1057:35] reg s1_executing_loads_22; // @[lsu.scala:1057:35] reg s1_executing_loads_23; // @[lsu.scala:1057:35] wire s1_set_execute_0; // @[lsu.scala:1058:36] wire s1_set_execute_1; // @[lsu.scala:1058:36] wire s1_set_execute_2; // @[lsu.scala:1058:36] wire s1_set_execute_3; // @[lsu.scala:1058:36] wire s1_set_execute_4; // @[lsu.scala:1058:36] wire s1_set_execute_5; // @[lsu.scala:1058:36] wire s1_set_execute_6; // @[lsu.scala:1058:36] wire s1_set_execute_7; // @[lsu.scala:1058:36] wire s1_set_execute_8; // @[lsu.scala:1058:36] wire s1_set_execute_9; // @[lsu.scala:1058:36] wire s1_set_execute_10; // @[lsu.scala:1058:36] wire s1_set_execute_11; // @[lsu.scala:1058:36] wire s1_set_execute_12; // @[lsu.scala:1058:36] wire s1_set_execute_13; // @[lsu.scala:1058:36] wire s1_set_execute_14; // @[lsu.scala:1058:36] wire s1_set_execute_15; // @[lsu.scala:1058:36] wire s1_set_execute_16; // @[lsu.scala:1058:36] wire s1_set_execute_17; // @[lsu.scala:1058:36] wire s1_set_execute_18; // @[lsu.scala:1058:36] wire s1_set_execute_19; // @[lsu.scala:1058:36] wire s1_set_execute_20; // @[lsu.scala:1058:36] wire s1_set_execute_21; // @[lsu.scala:1058:36] wire s1_set_execute_22; // @[lsu.scala:1058:36] wire s1_set_execute_23; // @[lsu.scala:1058:36] wire mem_forward_valid_0; // @[lsu.scala:1060:33] wire [4:0] forwarding_idx_0; // @[lsu.scala:263:49] wire [4:0] mem_forward_stq_idx_0; // @[lsu.scala:1063:33] reg wb_forward_valid_0; // @[lsu.scala:1065:36] reg [4:0] wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] wire [4:0] _forward_uop_T = wb_forward_ldq_idx_0; // @[lsu.scala:1066:36] reg [39:0] wb_forward_ld_addr_0; // @[lsu.scala:1067:36] reg [4:0] wb_forward_stq_idx_0; // @[lsu.scala:1068:36] wire [7:0] l_mask; // @[lsu.scala:1665:22] wire _l_mask_mask_T = ldq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_1 = ldq_0_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_2 = 15'h1 << _l_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_3 = ldq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_4 = ldq_0_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_5 = {_l_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_6 = 15'h3 << _l_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_7 = ldq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_8 = ldq_0_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_9 = _l_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_10 = &ldq_0_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_12 = _l_mask_mask_T_7 ? _l_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_13 = _l_mask_mask_T_3 ? _l_mask_mask_T_6 : {7'h0, _l_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_14 = _l_mask_mask_T ? _l_mask_mask_T_2 : _l_mask_mask_T_13; // @[Mux.scala:126:16] assign l_mask = _l_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T = wb_forward_ldq_idx_0 == 5'h0; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_1 = wb_forward_valid_0 & _l_forwarders_T; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_0 = _l_forwarders_T_1; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_48 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_51 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_54 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_57 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_60 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_63 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_66 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_69 = lcam_addr_0[39:6]; // @[lsu.scala:263:49, :1081:57] wire [33:0] _block_addr_matches_T_1 = ldq_0_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_64 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_68 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_72 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_76 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_80 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_84 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_88 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_92 = lcam_addr_0[5:3]; // @[lsu.scala:263:49, :1082:81] wire [2:0] _dword_addr_matches_T_1 = ldq_0_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_304 = l_mask & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T; // @[lsu.scala:1083:46] assign _mask_match_T = _GEN_304; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1084:46] assign _mask_overlap_T = _GEN_304; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_1 = _mask_match_T == l_mask; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_1 = |_mask_overlap_T; // @[lsu.scala:1084:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:263:49, :1084:62] wire _T_265 = do_release_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_294 = ldq_0_bits_executed | ldq_0_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _GEN_305 = {19'h0, lcam_stq_idx_0}; // @[lsu.scala:263:49, :1101:38] wire [23:0] _T_273 = ldq_0_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_277 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & (_T_294 | l_forwarders_0) & ~ldq_0_bits_addr_is_virtual & _T_273[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T = l_forward_stq_idx < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_1 = l_forward_stq_idx < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _T_281 = ~ldq_0_bits_forward_std_val | l_forward_stq_idx != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:363:72] wire _T_287 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _GEN_306 = lcam_ldq_idx_0 < ldq_head; // @[util.scala:363:64] wire _searcher_is_older_T_1; // @[util.scala:363:64] assign _searcher_is_older_T_1 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_5; // @[util.scala:363:64] assign _searcher_is_older_T_5 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_9; // @[util.scala:363:64] assign _searcher_is_older_T_9 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_13; // @[util.scala:363:64] assign _searcher_is_older_T_13 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_17; // @[util.scala:363:64] assign _searcher_is_older_T_17 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_21; // @[util.scala:363:64] assign _searcher_is_older_T_21 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_25; // @[util.scala:363:64] assign _searcher_is_older_T_25 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_29; // @[util.scala:363:64] assign _searcher_is_older_T_29 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_33; // @[util.scala:363:64] assign _searcher_is_older_T_33 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_37; // @[util.scala:363:64] assign _searcher_is_older_T_37 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_41; // @[util.scala:363:64] assign _searcher_is_older_T_41 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_45; // @[util.scala:363:64] assign _searcher_is_older_T_45 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_49; // @[util.scala:363:64] assign _searcher_is_older_T_49 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_53; // @[util.scala:363:64] assign _searcher_is_older_T_53 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_57; // @[util.scala:363:64] assign _searcher_is_older_T_57 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_61; // @[util.scala:363:64] assign _searcher_is_older_T_61 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_65; // @[util.scala:363:64] assign _searcher_is_older_T_65 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_69; // @[util.scala:363:64] assign _searcher_is_older_T_69 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_73; // @[util.scala:363:64] assign _searcher_is_older_T_73 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_77; // @[util.scala:363:64] assign _searcher_is_older_T_77 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_81; // @[util.scala:363:64] assign _searcher_is_older_T_81 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_85; // @[util.scala:363:64] assign _searcher_is_older_T_85 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_89; // @[util.scala:363:64] assign _searcher_is_older_T_89 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_93; // @[util.scala:363:64] assign _searcher_is_older_T_93 = _GEN_306; // @[util.scala:363:64] wire _searcher_is_older_T_2 = _searcher_is_older_T_1; // @[util.scala:363:{58,64}] wire _searcher_is_older_T_3 = |ldq_head; // @[util.scala:363:78] wire searcher_is_older = _searcher_is_older_T_2 ^ _searcher_is_older_T_3; // @[util.scala:363:{58,72,78}] wire _GEN_307 = _T_287 & searcher_is_older & (_T_294 | l_forwarders_0) & ~s1_executing_loads_0 & ldq_0_bits_observed; // @[util.scala:363:72] assign failed_loads_0 = ~_T_265 & (_T_277 ? _T_281 : _GEN_307); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG; // @[lsu.scala:1129:57] wire older_nacked = nacking_loads_0 | older_nacked_REG; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_296 = ~_T_294 | older_nacked; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _searcher_is_older_T_4 = lcam_ldq_idx_0 == 5'h0; // @[util.scala:363:52] wire _GEN_308 = _T_265 | _T_277; // @[lsu.scala:1058:36, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_309 = lcam_ldq_idx_0 == 5'h1; // @[lsu.scala:263:49, :1131:48] wire _GEN_310 = lcam_ldq_idx_0 == 5'h2; // @[lsu.scala:263:49, :1131:48] wire _GEN_311 = lcam_ldq_idx_0 == 5'h3; // @[lsu.scala:263:49, :1131:48] wire _GEN_312 = lcam_ldq_idx_0 == 5'h4; // @[lsu.scala:263:49, :1131:48] wire _GEN_313 = lcam_ldq_idx_0 == 5'h5; // @[lsu.scala:263:49, :1131:48] wire _GEN_314 = lcam_ldq_idx_0 == 5'h6; // @[lsu.scala:263:49, :1131:48] wire _GEN_315 = lcam_ldq_idx_0 == 5'h7; // @[lsu.scala:263:49, :1131:48] wire _GEN_316 = lcam_ldq_idx_0 == 5'h8; // @[lsu.scala:263:49, :1131:48] wire _GEN_317 = lcam_ldq_idx_0 == 5'h9; // @[lsu.scala:263:49, :1131:48] wire _GEN_318 = lcam_ldq_idx_0 == 5'hA; // @[lsu.scala:263:49, :1131:48] wire _GEN_319 = lcam_ldq_idx_0 == 5'hB; // @[lsu.scala:263:49, :1131:48] wire _GEN_320 = lcam_ldq_idx_0 == 5'hC; // @[lsu.scala:263:49, :1131:48] wire _GEN_321 = lcam_ldq_idx_0 == 5'hD; // @[lsu.scala:263:49, :1131:48] wire _GEN_322 = lcam_ldq_idx_0 == 5'hE; // @[lsu.scala:263:49, :1131:48] wire _GEN_323 = lcam_ldq_idx_0 == 5'hF; // @[lsu.scala:263:49, :1131:48] wire _GEN_324 = lcam_ldq_idx_0 == 5'h10; // @[lsu.scala:263:49, :1131:48] wire _GEN_325 = lcam_ldq_idx_0 == 5'h11; // @[lsu.scala:263:49, :1131:48] wire _GEN_326 = lcam_ldq_idx_0 == 5'h12; // @[lsu.scala:263:49, :1131:48] wire _GEN_327 = lcam_ldq_idx_0 == 5'h13; // @[lsu.scala:263:49, :1131:48] wire _GEN_328 = lcam_ldq_idx_0 == 5'h14; // @[lsu.scala:263:49, :1131:48] wire _GEN_329 = lcam_ldq_idx_0 == 5'h15; // @[lsu.scala:263:49, :1131:48] wire _GEN_330 = lcam_ldq_idx_0 == 5'h16; // @[lsu.scala:263:49, :1131:48] wire _GEN_331 = lcam_ldq_idx_0 == 5'h17; // @[lsu.scala:263:49, :1131:48] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:1132:58] wire _GEN_332 = (|lcam_ldq_idx_0) & _T_296; // @[lsu.scala:263:49, :765:24, :1126:{38,47}, :1130:{56,73}, :1132:48] wire [7:0] l_mask_1; // @[lsu.scala:1665:22] wire _l_mask_mask_T_15 = ldq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_16 = ldq_1_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_17 = 15'h1 << _l_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_18 = ldq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_19 = ldq_1_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_20 = {_l_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_21 = 15'h3 << _l_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_22 = ldq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_23 = ldq_1_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_24 = _l_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_25 = &ldq_1_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_27 = _l_mask_mask_T_22 ? _l_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_28 = _l_mask_mask_T_18 ? _l_mask_mask_T_21 : {7'h0, _l_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_29 = _l_mask_mask_T_15 ? _l_mask_mask_T_17 : _l_mask_mask_T_28; // @[Mux.scala:126:16] assign l_mask_1 = _l_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_2 = wb_forward_ldq_idx_0 == 5'h1; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_3 = wb_forward_valid_0 & _l_forwarders_T_2; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_1_0 = _l_forwarders_T_3; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_4 = ldq_1_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_5 = ldq_1_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_333 = l_mask_1 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_2; // @[lsu.scala:1083:46] assign _mask_match_T_2 = _GEN_333; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1084:46] assign _mask_overlap_T_2 = _GEN_333; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_3 = _mask_match_T_2 == l_mask_1; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_3 = |_mask_overlap_T_2; // @[lsu.scala:1084:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:263:49, :1084:62] wire _T_301 = do_release_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_330 = ldq_1_bits_executed | ldq_1_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_309 = ldq_1_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_313 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & (_T_330 | l_forwarders_1_0) & ~ldq_1_bits_addr_is_virtual & _T_309[0] & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_4 = l_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_5 = l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _T_317 = ~ldq_1_bits_forward_std_val | l_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1; // @[util.scala:363:72] wire _T_323 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_6 = _searcher_is_older_T_4 ^ _searcher_is_older_T_5; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_7 = |(ldq_head[4:1]); // @[util.scala:363:78] wire searcher_is_older_1 = _searcher_is_older_T_6 ^ _searcher_is_older_T_7; // @[util.scala:363:{58,72,78}] wire _GEN_334 = _T_323 & searcher_is_older_1 & (_T_330 | l_forwarders_1_0) & ~s1_executing_loads_1 & ldq_1_bits_observed; // @[util.scala:363:72] assign failed_loads_1 = ~_T_301 & (_T_313 ? _T_317 : _GEN_334); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_1; // @[lsu.scala:1129:57] wire older_nacked_1 = nacking_loads_1 | older_nacked_REG_1; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_332 = ~_T_330 | older_nacked_1; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_335 = searcher_is_older_1 | _GEN_309; // @[util.scala:363:72] wire _GEN_336 = _T_301 | _T_313; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_1; // @[lsu.scala:1132:58] wire _GEN_337 = _GEN_336 | ~_T_323 | _GEN_335 | ~_T_332; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_2; // @[lsu.scala:1665:22] wire _l_mask_mask_T_30 = ldq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_31 = ldq_2_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_32 = 15'h1 << _l_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_33 = ldq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_34 = ldq_2_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_35 = {_l_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_36 = 15'h3 << _l_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_37 = ldq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_38 = ldq_2_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_39 = _l_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_40 = &ldq_2_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_42 = _l_mask_mask_T_37 ? _l_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_43 = _l_mask_mask_T_33 ? _l_mask_mask_T_36 : {7'h0, _l_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_44 = _l_mask_mask_T_30 ? _l_mask_mask_T_32 : _l_mask_mask_T_43; // @[Mux.scala:126:16] assign l_mask_2 = _l_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_4 = wb_forward_ldq_idx_0 == 5'h2; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_5 = wb_forward_valid_0 & _l_forwarders_T_4; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_2_0 = _l_forwarders_T_5; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_7 = ldq_2_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_9 = ldq_2_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_338 = l_mask_2 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_4; // @[lsu.scala:1083:46] assign _mask_match_T_4 = _GEN_338; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1084:46] assign _mask_overlap_T_4 = _GEN_338; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_5 = _mask_match_T_4 == l_mask_2; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_5 = |_mask_overlap_T_4; // @[lsu.scala:1084:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:263:49, :1084:62] wire _T_337 = do_release_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_366 = ldq_2_bits_executed | ldq_2_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_345 = ldq_2_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_349 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & (_T_366 | l_forwarders_2_0) & ~ldq_2_bits_addr_is_virtual & _T_345[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_8 = l_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_9 = l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _T_353 = ~ldq_2_bits_forward_std_val | l_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:363:72] wire _T_359 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_8 = lcam_ldq_idx_0 < 5'h2; // @[util.scala:363:52] wire _searcher_is_older_T_10 = _searcher_is_older_T_8 ^ _searcher_is_older_T_9; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_11 = ldq_head > 5'h2; // @[util.scala:363:78] wire searcher_is_older_2 = _searcher_is_older_T_10 ^ _searcher_is_older_T_11; // @[util.scala:363:{58,72,78}] wire _GEN_339 = _T_359 & searcher_is_older_2 & (_T_366 | l_forwarders_2_0) & ~s1_executing_loads_2 & ldq_2_bits_observed; // @[util.scala:363:72] assign failed_loads_2 = ~_T_337 & (_T_349 ? _T_353 : _GEN_339); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_2; // @[lsu.scala:1129:57] wire older_nacked_2 = nacking_loads_2 | older_nacked_REG_2; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_368 = ~_T_366 | older_nacked_2; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_340 = searcher_is_older_2 | _GEN_310; // @[util.scala:363:72] wire _GEN_341 = _T_337 | _T_349; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_2; // @[lsu.scala:1132:58] wire _GEN_342 = _GEN_341 | ~_T_359 | _GEN_340 | ~_T_368; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_3; // @[lsu.scala:1665:22] wire _l_mask_mask_T_45 = ldq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_46 = ldq_3_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_47 = 15'h1 << _l_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_48 = ldq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_49 = ldq_3_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_50 = {_l_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_51 = 15'h3 << _l_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_52 = ldq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_53 = ldq_3_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_54 = _l_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_55 = &ldq_3_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_57 = _l_mask_mask_T_52 ? _l_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_58 = _l_mask_mask_T_48 ? _l_mask_mask_T_51 : {7'h0, _l_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_59 = _l_mask_mask_T_45 ? _l_mask_mask_T_47 : _l_mask_mask_T_58; // @[Mux.scala:126:16] assign l_mask_3 = _l_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_6 = wb_forward_ldq_idx_0 == 5'h3; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_7 = wb_forward_valid_0 & _l_forwarders_T_6; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_3_0 = _l_forwarders_T_7; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_10 = ldq_3_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_13 = ldq_3_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_343 = l_mask_3 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_6; // @[lsu.scala:1083:46] assign _mask_match_T_6 = _GEN_343; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1084:46] assign _mask_overlap_T_6 = _GEN_343; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_7 = _mask_match_T_6 == l_mask_3; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_7 = |_mask_overlap_T_6; // @[lsu.scala:1084:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:263:49, :1084:62] wire _T_373 = do_release_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_402 = ldq_3_bits_executed | ldq_3_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_381 = ldq_3_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_385 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & (_T_402 | l_forwarders_3_0) & ~ldq_3_bits_addr_is_virtual & _T_381[0] & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_12 = l_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_13 = l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _T_389 = ~ldq_3_bits_forward_std_val | l_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3; // @[util.scala:363:72] wire _T_395 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_12 = lcam_ldq_idx_0 < 5'h3; // @[util.scala:363:52] wire _searcher_is_older_T_14 = _searcher_is_older_T_12 ^ _searcher_is_older_T_13; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_15 = |(ldq_head[4:2]); // @[util.scala:363:78] wire searcher_is_older_3 = _searcher_is_older_T_14 ^ _searcher_is_older_T_15; // @[util.scala:363:{58,72,78}] wire _GEN_344 = _T_395 & searcher_is_older_3 & (_T_402 | l_forwarders_3_0) & ~s1_executing_loads_3 & ldq_3_bits_observed; // @[util.scala:363:72] assign failed_loads_3 = ~_T_373 & (_T_385 ? _T_389 : _GEN_344); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_3; // @[lsu.scala:1129:57] wire older_nacked_3 = nacking_loads_3 | older_nacked_REG_3; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_404 = ~_T_402 | older_nacked_3; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_345 = searcher_is_older_3 | _GEN_311; // @[util.scala:363:72] wire _GEN_346 = _T_373 | _T_385; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_3; // @[lsu.scala:1132:58] wire _GEN_347 = _GEN_346 | ~_T_395 | _GEN_345 | ~_T_404; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_4; // @[lsu.scala:1665:22] wire _l_mask_mask_T_60 = ldq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_61 = ldq_4_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_62 = 15'h1 << _l_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_63 = ldq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_64 = ldq_4_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_65 = {_l_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_66 = 15'h3 << _l_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_67 = ldq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_68 = ldq_4_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_69 = _l_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_70 = &ldq_4_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_72 = _l_mask_mask_T_67 ? _l_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_73 = _l_mask_mask_T_63 ? _l_mask_mask_T_66 : {7'h0, _l_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_74 = _l_mask_mask_T_60 ? _l_mask_mask_T_62 : _l_mask_mask_T_73; // @[Mux.scala:126:16] assign l_mask_4 = _l_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_8 = wb_forward_ldq_idx_0 == 5'h4; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_9 = wb_forward_valid_0 & _l_forwarders_T_8; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_4_0 = _l_forwarders_T_9; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_13 = ldq_4_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_17 = ldq_4_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_348 = l_mask_4 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_8; // @[lsu.scala:1083:46] assign _mask_match_T_8 = _GEN_348; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1084:46] assign _mask_overlap_T_8 = _GEN_348; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_9 = _mask_match_T_8 == l_mask_4; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_9 = |_mask_overlap_T_8; // @[lsu.scala:1084:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:263:49, :1084:62] wire _T_409 = do_release_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_438 = ldq_4_bits_executed | ldq_4_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_417 = ldq_4_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_421 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & (_T_438 | l_forwarders_4_0) & ~ldq_4_bits_addr_is_virtual & _T_417[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_16 = l_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_17 = l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _T_425 = ~ldq_4_bits_forward_std_val | l_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:363:72] wire _T_431 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_16 = lcam_ldq_idx_0 < 5'h4; // @[util.scala:363:52] wire _searcher_is_older_T_18 = _searcher_is_older_T_16 ^ _searcher_is_older_T_17; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_19 = ldq_head > 5'h4; // @[util.scala:363:78] wire searcher_is_older_4 = _searcher_is_older_T_18 ^ _searcher_is_older_T_19; // @[util.scala:363:{58,72,78}] wire _GEN_349 = _T_431 & searcher_is_older_4 & (_T_438 | l_forwarders_4_0) & ~s1_executing_loads_4 & ldq_4_bits_observed; // @[util.scala:363:72] assign failed_loads_4 = ~_T_409 & (_T_421 ? _T_425 : _GEN_349); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_4; // @[lsu.scala:1129:57] wire older_nacked_4 = nacking_loads_4 | older_nacked_REG_4; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_440 = ~_T_438 | older_nacked_4; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_350 = searcher_is_older_4 | _GEN_312; // @[util.scala:363:72] wire _GEN_351 = _T_409 | _T_421; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_4; // @[lsu.scala:1132:58] wire _GEN_352 = _GEN_351 | ~_T_431 | _GEN_350 | ~_T_440; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_5; // @[lsu.scala:1665:22] wire _l_mask_mask_T_75 = ldq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_76 = ldq_5_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_77 = 15'h1 << _l_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_78 = ldq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_79 = ldq_5_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_80 = {_l_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_81 = 15'h3 << _l_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_82 = ldq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_83 = ldq_5_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_84 = _l_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_85 = &ldq_5_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_87 = _l_mask_mask_T_82 ? _l_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_88 = _l_mask_mask_T_78 ? _l_mask_mask_T_81 : {7'h0, _l_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_89 = _l_mask_mask_T_75 ? _l_mask_mask_T_77 : _l_mask_mask_T_88; // @[Mux.scala:126:16] assign l_mask_5 = _l_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_10 = wb_forward_ldq_idx_0 == 5'h5; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_11 = wb_forward_valid_0 & _l_forwarders_T_10; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_5_0 = _l_forwarders_T_11; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_16 = ldq_5_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_21 = ldq_5_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_353 = l_mask_5 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_10; // @[lsu.scala:1083:46] assign _mask_match_T_10 = _GEN_353; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1084:46] assign _mask_overlap_T_10 = _GEN_353; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_11 = _mask_match_T_10 == l_mask_5; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_11 = |_mask_overlap_T_10; // @[lsu.scala:1084:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:263:49, :1084:62] wire _T_445 = do_release_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_474 = ldq_5_bits_executed | ldq_5_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_453 = ldq_5_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_457 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & (_T_474 | l_forwarders_5_0) & ~ldq_5_bits_addr_is_virtual & _T_453[0] & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_20 = l_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_21 = l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _T_461 = ~ldq_5_bits_forward_std_val | l_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5; // @[util.scala:363:72] wire _T_467 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_20 = lcam_ldq_idx_0 < 5'h5; // @[util.scala:363:52] wire _searcher_is_older_T_22 = _searcher_is_older_T_20 ^ _searcher_is_older_T_21; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_23 = ldq_head > 5'h5; // @[util.scala:363:78] wire searcher_is_older_5 = _searcher_is_older_T_22 ^ _searcher_is_older_T_23; // @[util.scala:363:{58,72,78}] wire _GEN_354 = _T_467 & searcher_is_older_5 & (_T_474 | l_forwarders_5_0) & ~s1_executing_loads_5 & ldq_5_bits_observed; // @[util.scala:363:72] assign failed_loads_5 = ~_T_445 & (_T_457 ? _T_461 : _GEN_354); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_5; // @[lsu.scala:1129:57] wire older_nacked_5 = nacking_loads_5 | older_nacked_REG_5; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_476 = ~_T_474 | older_nacked_5; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_355 = searcher_is_older_5 | _GEN_313; // @[util.scala:363:72] wire _GEN_356 = _T_445 | _T_457; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_5; // @[lsu.scala:1132:58] wire _GEN_357 = _GEN_356 | ~_T_467 | _GEN_355 | ~_T_476; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_6; // @[lsu.scala:1665:22] wire _l_mask_mask_T_90 = ldq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_91 = ldq_6_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_92 = 15'h1 << _l_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_93 = ldq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_94 = ldq_6_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_95 = {_l_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_96 = 15'h3 << _l_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_97 = ldq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_98 = ldq_6_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_99 = _l_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_100 = &ldq_6_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_102 = _l_mask_mask_T_97 ? _l_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_103 = _l_mask_mask_T_93 ? _l_mask_mask_T_96 : {7'h0, _l_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_104 = _l_mask_mask_T_90 ? _l_mask_mask_T_92 : _l_mask_mask_T_103; // @[Mux.scala:126:16] assign l_mask_6 = _l_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_12 = wb_forward_ldq_idx_0 == 5'h6; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_13 = wb_forward_valid_0 & _l_forwarders_T_12; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_6_0 = _l_forwarders_T_13; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_19 = ldq_6_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_25 = ldq_6_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_358 = l_mask_6 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_12; // @[lsu.scala:1083:46] assign _mask_match_T_12 = _GEN_358; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1084:46] assign _mask_overlap_T_12 = _GEN_358; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_13 = _mask_match_T_12 == l_mask_6; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_13 = |_mask_overlap_T_12; // @[lsu.scala:1084:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:263:49, :1084:62] wire _T_481 = do_release_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_510 = ldq_6_bits_executed | ldq_6_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_489 = ldq_6_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_493 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & (_T_510 | l_forwarders_6_0) & ~ldq_6_bits_addr_is_virtual & _T_489[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_24 = l_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_25 = l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _T_497 = ~ldq_6_bits_forward_std_val | l_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:363:72] wire _T_503 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_24 = lcam_ldq_idx_0 < 5'h6; // @[util.scala:363:52] wire _searcher_is_older_T_26 = _searcher_is_older_T_24 ^ _searcher_is_older_T_25; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_27 = ldq_head > 5'h6; // @[util.scala:363:78] wire searcher_is_older_6 = _searcher_is_older_T_26 ^ _searcher_is_older_T_27; // @[util.scala:363:{58,72,78}] wire _GEN_359 = _T_503 & searcher_is_older_6 & (_T_510 | l_forwarders_6_0) & ~s1_executing_loads_6 & ldq_6_bits_observed; // @[util.scala:363:72] assign failed_loads_6 = ~_T_481 & (_T_493 ? _T_497 : _GEN_359); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_6; // @[lsu.scala:1129:57] wire older_nacked_6 = nacking_loads_6 | older_nacked_REG_6; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_512 = ~_T_510 | older_nacked_6; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_360 = searcher_is_older_6 | _GEN_314; // @[util.scala:363:72] wire _GEN_361 = _T_481 | _T_493; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_6; // @[lsu.scala:1132:58] wire _GEN_362 = _GEN_361 | ~_T_503 | _GEN_360 | ~_T_512; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_7; // @[lsu.scala:1665:22] wire _l_mask_mask_T_105 = ldq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_106 = ldq_7_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_107 = 15'h1 << _l_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_108 = ldq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_109 = ldq_7_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_110 = {_l_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_111 = 15'h3 << _l_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_112 = ldq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_113 = ldq_7_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_114 = _l_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_115 = &ldq_7_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_117 = _l_mask_mask_T_112 ? _l_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_118 = _l_mask_mask_T_108 ? _l_mask_mask_T_111 : {7'h0, _l_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_119 = _l_mask_mask_T_105 ? _l_mask_mask_T_107 : _l_mask_mask_T_118; // @[Mux.scala:126:16] assign l_mask_7 = _l_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_14 = wb_forward_ldq_idx_0 == 5'h7; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_15 = wb_forward_valid_0 & _l_forwarders_T_14; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_7_0 = _l_forwarders_T_15; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_22 = ldq_7_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_29 = ldq_7_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_363 = l_mask_7 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_14; // @[lsu.scala:1083:46] assign _mask_match_T_14 = _GEN_363; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1084:46] assign _mask_overlap_T_14 = _GEN_363; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_15 = _mask_match_T_14 == l_mask_7; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_15 = |_mask_overlap_T_14; // @[lsu.scala:1084:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:263:49, :1084:62] wire _T_517 = do_release_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_546 = ldq_7_bits_executed | ldq_7_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_525 = ldq_7_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_529 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & (_T_546 | l_forwarders_7_0) & ~ldq_7_bits_addr_is_virtual & _T_525[0] & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_28 = l_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_29 = l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:363:{58,72,78}] wire _T_533 = ~ldq_7_bits_forward_std_val | l_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7; // @[util.scala:363:72] wire _T_539 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_28 = lcam_ldq_idx_0 < 5'h7; // @[util.scala:363:52] wire _searcher_is_older_T_30 = _searcher_is_older_T_28 ^ _searcher_is_older_T_29; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_31 = |(ldq_head[4:3]); // @[util.scala:351:72, :363:78] wire searcher_is_older_7 = _searcher_is_older_T_30 ^ _searcher_is_older_T_31; // @[util.scala:363:{58,72,78}] wire _GEN_364 = _T_539 & searcher_is_older_7 & (_T_546 | l_forwarders_7_0) & ~s1_executing_loads_7 & ldq_7_bits_observed; // @[util.scala:363:72] assign failed_loads_7 = ~_T_517 & (_T_529 ? _T_533 : _GEN_364); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_7; // @[lsu.scala:1129:57] wire older_nacked_7 = nacking_loads_7 | older_nacked_REG_7; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_548 = ~_T_546 | older_nacked_7; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_365 = searcher_is_older_7 | _GEN_315; // @[util.scala:363:72] wire _GEN_366 = _T_517 | _T_529; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_7; // @[lsu.scala:1132:58] wire _GEN_367 = _GEN_366 | ~_T_539 | _GEN_365 | ~_T_548; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_8; // @[lsu.scala:1665:22] wire _l_mask_mask_T_120 = ldq_8_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_121 = ldq_8_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_122 = 15'h1 << _l_mask_mask_T_121; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_123 = ldq_8_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_124 = ldq_8_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_125 = {_l_mask_mask_T_124, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_126 = 15'h3 << _l_mask_mask_T_125; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_127 = ldq_8_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_128 = ldq_8_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_129 = _l_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_130 = &ldq_8_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_132 = _l_mask_mask_T_127 ? _l_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_133 = _l_mask_mask_T_123 ? _l_mask_mask_T_126 : {7'h0, _l_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_134 = _l_mask_mask_T_120 ? _l_mask_mask_T_122 : _l_mask_mask_T_133; // @[Mux.scala:126:16] assign l_mask_8 = _l_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_16 = wb_forward_ldq_idx_0 == 5'h8; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_17 = wb_forward_valid_0 & _l_forwarders_T_16; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_8_0 = _l_forwarders_T_17; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_8 = l_forwarders_8_0 ? wb_forward_stq_idx_0 : ldq_8_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_25 = ldq_8_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_33 = ldq_8_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_368 = l_mask_8 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_16; // @[lsu.scala:1083:46] assign _mask_match_T_16 = _GEN_368; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1084:46] assign _mask_overlap_T_16 = _GEN_368; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_17 = _mask_match_T_16 == l_mask_8; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_17 = |_mask_overlap_T_16; // @[lsu.scala:1084:{46,62}] wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:263:49, :1084:62] wire _T_553 = do_release_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & block_addr_matches_8_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_582 = ldq_8_bits_executed | ldq_8_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_561 = ldq_8_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_565 = do_st_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & (_T_582 | l_forwarders_8_0) & ~ldq_8_bits_addr_is_virtual & _T_561[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_32 = l_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_33 = l_forward_stq_idx_8 < ldq_8_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < ldq_8_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:363:{58,72,78}] wire _T_569 = ~ldq_8_bits_forward_std_val | l_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:363:72] wire _T_575 = do_ld_search_0 & ldq_8_valid & ldq_8_bits_addr_valid & ~ldq_8_bits_addr_is_virtual & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_32 = lcam_ldq_idx_0 < 5'h8; // @[util.scala:363:52] wire _searcher_is_older_T_34 = _searcher_is_older_T_32 ^ _searcher_is_older_T_33; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_35 = ldq_head > 5'h8; // @[util.scala:363:78] wire searcher_is_older_8 = _searcher_is_older_T_34 ^ _searcher_is_older_T_35; // @[util.scala:363:{58,72,78}] wire _GEN_369 = _T_575 & searcher_is_older_8 & (_T_582 | l_forwarders_8_0) & ~s1_executing_loads_8 & ldq_8_bits_observed; // @[util.scala:363:72] assign failed_loads_8 = ~_T_553 & (_T_565 ? _T_569 : _GEN_369); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_8; // @[lsu.scala:1129:57] wire older_nacked_8 = nacking_loads_8 | older_nacked_REG_8; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_584 = ~_T_582 | older_nacked_8; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_370 = searcher_is_older_8 | _GEN_316; // @[util.scala:363:72] wire _GEN_371 = _T_553 | _T_565; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_8; // @[lsu.scala:1132:58] wire _GEN_372 = _GEN_371 | ~_T_575 | _GEN_370 | ~_T_584; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_9; // @[lsu.scala:1665:22] wire _l_mask_mask_T_135 = ldq_9_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_136 = ldq_9_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_137 = 15'h1 << _l_mask_mask_T_136; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_138 = ldq_9_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_139 = ldq_9_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_140 = {_l_mask_mask_T_139, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_141 = 15'h3 << _l_mask_mask_T_140; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_142 = ldq_9_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_143 = ldq_9_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_144 = _l_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_145 = &ldq_9_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_147 = _l_mask_mask_T_142 ? _l_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_148 = _l_mask_mask_T_138 ? _l_mask_mask_T_141 : {7'h0, _l_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_149 = _l_mask_mask_T_135 ? _l_mask_mask_T_137 : _l_mask_mask_T_148; // @[Mux.scala:126:16] assign l_mask_9 = _l_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_18 = wb_forward_ldq_idx_0 == 5'h9; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_19 = wb_forward_valid_0 & _l_forwarders_T_18; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_9_0 = _l_forwarders_T_19; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_9 = l_forwarders_9_0 ? wb_forward_stq_idx_0 : ldq_9_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_28 = ldq_9_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_37 = ldq_9_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_373 = l_mask_9 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_18; // @[lsu.scala:1083:46] assign _mask_match_T_18 = _GEN_373; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1084:46] assign _mask_overlap_T_18 = _GEN_373; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_19 = _mask_match_T_18 == l_mask_9; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_19 = |_mask_overlap_T_18; // @[lsu.scala:1084:{46,62}] wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:263:49, :1084:62] wire _T_589 = do_release_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & block_addr_matches_9_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_618 = ldq_9_bits_executed | ldq_9_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_597 = ldq_9_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_601 = do_st_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & (_T_618 | l_forwarders_9_0) & ~ldq_9_bits_addr_is_virtual & _T_597[0] & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_36 = l_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_37 = l_forward_stq_idx_9 < ldq_9_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < ldq_9_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:363:{58,72,78}] wire _T_605 = ~ldq_9_bits_forward_std_val | l_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9; // @[util.scala:363:72] wire _T_611 = do_ld_search_0 & ldq_9_valid & ldq_9_bits_addr_valid & ~ldq_9_bits_addr_is_virtual & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_36 = lcam_ldq_idx_0 < 5'h9; // @[util.scala:363:52] wire _searcher_is_older_T_38 = _searcher_is_older_T_36 ^ _searcher_is_older_T_37; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_39 = ldq_head > 5'h9; // @[util.scala:363:78] wire searcher_is_older_9 = _searcher_is_older_T_38 ^ _searcher_is_older_T_39; // @[util.scala:363:{58,72,78}] wire _GEN_374 = _T_611 & searcher_is_older_9 & (_T_618 | l_forwarders_9_0) & ~s1_executing_loads_9 & ldq_9_bits_observed; // @[util.scala:363:72] assign failed_loads_9 = ~_T_589 & (_T_601 ? _T_605 : _GEN_374); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_9; // @[lsu.scala:1129:57] wire older_nacked_9 = nacking_loads_9 | older_nacked_REG_9; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_620 = ~_T_618 | older_nacked_9; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_375 = searcher_is_older_9 | _GEN_317; // @[util.scala:363:72] wire _GEN_376 = _T_589 | _T_601; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_9; // @[lsu.scala:1132:58] wire _GEN_377 = _GEN_376 | ~_T_611 | _GEN_375 | ~_T_620; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_10; // @[lsu.scala:1665:22] wire _l_mask_mask_T_150 = ldq_10_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_151 = ldq_10_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_152 = 15'h1 << _l_mask_mask_T_151; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_153 = ldq_10_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_154 = ldq_10_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_155 = {_l_mask_mask_T_154, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_156 = 15'h3 << _l_mask_mask_T_155; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_157 = ldq_10_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_158 = ldq_10_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_159 = _l_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_160 = &ldq_10_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_162 = _l_mask_mask_T_157 ? _l_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_163 = _l_mask_mask_T_153 ? _l_mask_mask_T_156 : {7'h0, _l_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_164 = _l_mask_mask_T_150 ? _l_mask_mask_T_152 : _l_mask_mask_T_163; // @[Mux.scala:126:16] assign l_mask_10 = _l_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_20 = wb_forward_ldq_idx_0 == 5'hA; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_21 = wb_forward_valid_0 & _l_forwarders_T_20; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_10_0 = _l_forwarders_T_21; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_10 = l_forwarders_10_0 ? wb_forward_stq_idx_0 : ldq_10_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_31 = ldq_10_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_41 = ldq_10_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_378 = l_mask_10 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_20; // @[lsu.scala:1083:46] assign _mask_match_T_20 = _GEN_378; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1084:46] assign _mask_overlap_T_20 = _GEN_378; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_21 = _mask_match_T_20 == l_mask_10; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_21 = |_mask_overlap_T_20; // @[lsu.scala:1084:{46,62}] wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:263:49, :1084:62] wire _T_625 = do_release_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & block_addr_matches_10_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_654 = ldq_10_bits_executed | ldq_10_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_633 = ldq_10_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_637 = do_st_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & (_T_654 | l_forwarders_10_0) & ~ldq_10_bits_addr_is_virtual & _T_633[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_40 = l_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_41 = l_forward_stq_idx_10 < ldq_10_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < ldq_10_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:363:{58,72,78}] wire _T_641 = ~ldq_10_bits_forward_std_val | l_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:363:72] wire _T_647 = do_ld_search_0 & ldq_10_valid & ldq_10_bits_addr_valid & ~ldq_10_bits_addr_is_virtual & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_40 = lcam_ldq_idx_0 < 5'hA; // @[util.scala:363:52] wire _searcher_is_older_T_42 = _searcher_is_older_T_40 ^ _searcher_is_older_T_41; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_43 = ldq_head > 5'hA; // @[util.scala:363:78] wire searcher_is_older_10 = _searcher_is_older_T_42 ^ _searcher_is_older_T_43; // @[util.scala:363:{58,72,78}] wire _GEN_379 = _T_647 & searcher_is_older_10 & (_T_654 | l_forwarders_10_0) & ~s1_executing_loads_10 & ldq_10_bits_observed; // @[util.scala:363:72] assign failed_loads_10 = ~_T_625 & (_T_637 ? _T_641 : _GEN_379); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_10; // @[lsu.scala:1129:57] wire older_nacked_10 = nacking_loads_10 | older_nacked_REG_10; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_656 = ~_T_654 | older_nacked_10; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_380 = searcher_is_older_10 | _GEN_318; // @[util.scala:363:72] wire _GEN_381 = _T_625 | _T_637; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_10; // @[lsu.scala:1132:58] wire _GEN_382 = _GEN_381 | ~_T_647 | _GEN_380 | ~_T_656; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_11; // @[lsu.scala:1665:22] wire _l_mask_mask_T_165 = ldq_11_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_166 = ldq_11_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_167 = 15'h1 << _l_mask_mask_T_166; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_168 = ldq_11_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_169 = ldq_11_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_170 = {_l_mask_mask_T_169, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_171 = 15'h3 << _l_mask_mask_T_170; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_172 = ldq_11_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_173 = ldq_11_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_174 = _l_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_175 = &ldq_11_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_177 = _l_mask_mask_T_172 ? _l_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_178 = _l_mask_mask_T_168 ? _l_mask_mask_T_171 : {7'h0, _l_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_179 = _l_mask_mask_T_165 ? _l_mask_mask_T_167 : _l_mask_mask_T_178; // @[Mux.scala:126:16] assign l_mask_11 = _l_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_22 = wb_forward_ldq_idx_0 == 5'hB; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_23 = wb_forward_valid_0 & _l_forwarders_T_22; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_11_0 = _l_forwarders_T_23; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_11 = l_forwarders_11_0 ? wb_forward_stq_idx_0 : ldq_11_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_34 = ldq_11_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_45 = ldq_11_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_383 = l_mask_11 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_22; // @[lsu.scala:1083:46] assign _mask_match_T_22 = _GEN_383; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1084:46] assign _mask_overlap_T_22 = _GEN_383; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_23 = _mask_match_T_22 == l_mask_11; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_23 = |_mask_overlap_T_22; // @[lsu.scala:1084:{46,62}] wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:263:49, :1084:62] wire _T_661 = do_release_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & block_addr_matches_11_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_690 = ldq_11_bits_executed | ldq_11_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_669 = ldq_11_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_673 = do_st_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & (_T_690 | l_forwarders_11_0) & ~ldq_11_bits_addr_is_virtual & _T_669[0] & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_44 = l_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_45 = l_forward_stq_idx_11 < ldq_11_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < ldq_11_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:363:{58,72,78}] wire _T_677 = ~ldq_11_bits_forward_std_val | l_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11; // @[util.scala:363:72] wire _T_683 = do_ld_search_0 & ldq_11_valid & ldq_11_bits_addr_valid & ~ldq_11_bits_addr_is_virtual & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_44 = lcam_ldq_idx_0 < 5'hB; // @[util.scala:363:52] wire _searcher_is_older_T_46 = _searcher_is_older_T_44 ^ _searcher_is_older_T_45; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_47 = ldq_head > 5'hB; // @[util.scala:363:78] wire searcher_is_older_11 = _searcher_is_older_T_46 ^ _searcher_is_older_T_47; // @[util.scala:363:{58,72,78}] wire _GEN_384 = _T_683 & searcher_is_older_11 & (_T_690 | l_forwarders_11_0) & ~s1_executing_loads_11 & ldq_11_bits_observed; // @[util.scala:363:72] assign failed_loads_11 = ~_T_661 & (_T_673 ? _T_677 : _GEN_384); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_11; // @[lsu.scala:1129:57] wire older_nacked_11 = nacking_loads_11 | older_nacked_REG_11; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_692 = ~_T_690 | older_nacked_11; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_385 = searcher_is_older_11 | _GEN_319; // @[util.scala:363:72] wire _GEN_386 = _T_661 | _T_673; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_11; // @[lsu.scala:1132:58] wire _GEN_387 = _GEN_386 | ~_T_683 | _GEN_385 | ~_T_692; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_12; // @[lsu.scala:1665:22] wire _l_mask_mask_T_180 = ldq_12_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_181 = ldq_12_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_182 = 15'h1 << _l_mask_mask_T_181; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_183 = ldq_12_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_184 = ldq_12_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_185 = {_l_mask_mask_T_184, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_186 = 15'h3 << _l_mask_mask_T_185; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_187 = ldq_12_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_188 = ldq_12_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_189 = _l_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_190 = &ldq_12_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_192 = _l_mask_mask_T_187 ? _l_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_193 = _l_mask_mask_T_183 ? _l_mask_mask_T_186 : {7'h0, _l_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_194 = _l_mask_mask_T_180 ? _l_mask_mask_T_182 : _l_mask_mask_T_193; // @[Mux.scala:126:16] assign l_mask_12 = _l_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_24 = wb_forward_ldq_idx_0 == 5'hC; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_25 = wb_forward_valid_0 & _l_forwarders_T_24; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_12_0 = _l_forwarders_T_25; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_12 = l_forwarders_12_0 ? wb_forward_stq_idx_0 : ldq_12_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_37 = ldq_12_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_49 = ldq_12_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_388 = l_mask_12 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_24; // @[lsu.scala:1083:46] assign _mask_match_T_24 = _GEN_388; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1084:46] assign _mask_overlap_T_24 = _GEN_388; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_25 = _mask_match_T_24 == l_mask_12; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_25 = |_mask_overlap_T_24; // @[lsu.scala:1084:{46,62}] wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:263:49, :1084:62] wire _T_697 = do_release_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & block_addr_matches_12_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_726 = ldq_12_bits_executed | ldq_12_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_705 = ldq_12_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_709 = do_st_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & (_T_726 | l_forwarders_12_0) & ~ldq_12_bits_addr_is_virtual & _T_705[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_48 = l_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_49 = l_forward_stq_idx_12 < ldq_12_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < ldq_12_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:363:{58,72,78}] wire _T_713 = ~ldq_12_bits_forward_std_val | l_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:363:72] wire _T_719 = do_ld_search_0 & ldq_12_valid & ldq_12_bits_addr_valid & ~ldq_12_bits_addr_is_virtual & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_48 = lcam_ldq_idx_0 < 5'hC; // @[util.scala:363:52] wire _searcher_is_older_T_50 = _searcher_is_older_T_48 ^ _searcher_is_older_T_49; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_51 = ldq_head > 5'hC; // @[util.scala:363:78] wire searcher_is_older_12 = _searcher_is_older_T_50 ^ _searcher_is_older_T_51; // @[util.scala:363:{58,72,78}] wire _GEN_389 = _T_719 & searcher_is_older_12 & (_T_726 | l_forwarders_12_0) & ~s1_executing_loads_12 & ldq_12_bits_observed; // @[util.scala:363:72] assign failed_loads_12 = ~_T_697 & (_T_709 ? _T_713 : _GEN_389); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_12; // @[lsu.scala:1129:57] wire older_nacked_12 = nacking_loads_12 | older_nacked_REG_12; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_728 = ~_T_726 | older_nacked_12; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_390 = searcher_is_older_12 | _GEN_320; // @[util.scala:363:72] wire _GEN_391 = _T_697 | _T_709; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_12; // @[lsu.scala:1132:58] wire _GEN_392 = _GEN_391 | ~_T_719 | _GEN_390 | ~_T_728; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_13; // @[lsu.scala:1665:22] wire _l_mask_mask_T_195 = ldq_13_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_196 = ldq_13_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_197 = 15'h1 << _l_mask_mask_T_196; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_198 = ldq_13_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_199 = ldq_13_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_200 = {_l_mask_mask_T_199, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_201 = 15'h3 << _l_mask_mask_T_200; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_202 = ldq_13_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_203 = ldq_13_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_204 = _l_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_205 = &ldq_13_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_207 = _l_mask_mask_T_202 ? _l_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_208 = _l_mask_mask_T_198 ? _l_mask_mask_T_201 : {7'h0, _l_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_209 = _l_mask_mask_T_195 ? _l_mask_mask_T_197 : _l_mask_mask_T_208; // @[Mux.scala:126:16] assign l_mask_13 = _l_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_26 = wb_forward_ldq_idx_0 == 5'hD; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_27 = wb_forward_valid_0 & _l_forwarders_T_26; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_13_0 = _l_forwarders_T_27; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_13 = l_forwarders_13_0 ? wb_forward_stq_idx_0 : ldq_13_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_40 = ldq_13_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_53 = ldq_13_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_393 = l_mask_13 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_26; // @[lsu.scala:1083:46] assign _mask_match_T_26 = _GEN_393; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1084:46] assign _mask_overlap_T_26 = _GEN_393; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_27 = _mask_match_T_26 == l_mask_13; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_27 = |_mask_overlap_T_26; // @[lsu.scala:1084:{46,62}] wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:263:49, :1084:62] wire _T_733 = do_release_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & block_addr_matches_13_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_762 = ldq_13_bits_executed | ldq_13_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_741 = ldq_13_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_745 = do_st_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & (_T_762 | l_forwarders_13_0) & ~ldq_13_bits_addr_is_virtual & _T_741[0] & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_52 = l_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_53 = l_forward_stq_idx_13 < ldq_13_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < ldq_13_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:363:{58,72,78}] wire _T_749 = ~ldq_13_bits_forward_std_val | l_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13; // @[util.scala:363:72] wire _T_755 = do_ld_search_0 & ldq_13_valid & ldq_13_bits_addr_valid & ~ldq_13_bits_addr_is_virtual & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_52 = lcam_ldq_idx_0 < 5'hD; // @[util.scala:363:52] wire _searcher_is_older_T_54 = _searcher_is_older_T_52 ^ _searcher_is_older_T_53; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_55 = ldq_head > 5'hD; // @[util.scala:363:78] wire searcher_is_older_13 = _searcher_is_older_T_54 ^ _searcher_is_older_T_55; // @[util.scala:363:{58,72,78}] wire _GEN_394 = _T_755 & searcher_is_older_13 & (_T_762 | l_forwarders_13_0) & ~s1_executing_loads_13 & ldq_13_bits_observed; // @[util.scala:363:72] assign failed_loads_13 = ~_T_733 & (_T_745 ? _T_749 : _GEN_394); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_13; // @[lsu.scala:1129:57] wire older_nacked_13 = nacking_loads_13 | older_nacked_REG_13; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_764 = ~_T_762 | older_nacked_13; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_395 = searcher_is_older_13 | _GEN_321; // @[util.scala:363:72] wire _GEN_396 = _T_733 | _T_745; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_13; // @[lsu.scala:1132:58] wire _GEN_397 = _GEN_396 | ~_T_755 | _GEN_395 | ~_T_764; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_14; // @[lsu.scala:1665:22] wire _l_mask_mask_T_210 = ldq_14_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_211 = ldq_14_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_212 = 15'h1 << _l_mask_mask_T_211; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_213 = ldq_14_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_214 = ldq_14_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_215 = {_l_mask_mask_T_214, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_216 = 15'h3 << _l_mask_mask_T_215; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_217 = ldq_14_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_218 = ldq_14_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_219 = _l_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_220 = &ldq_14_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_222 = _l_mask_mask_T_217 ? _l_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_223 = _l_mask_mask_T_213 ? _l_mask_mask_T_216 : {7'h0, _l_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_224 = _l_mask_mask_T_210 ? _l_mask_mask_T_212 : _l_mask_mask_T_223; // @[Mux.scala:126:16] assign l_mask_14 = _l_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_28 = wb_forward_ldq_idx_0 == 5'hE; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_29 = wb_forward_valid_0 & _l_forwarders_T_28; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_14_0 = _l_forwarders_T_29; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_14 = l_forwarders_14_0 ? wb_forward_stq_idx_0 : ldq_14_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_43 = ldq_14_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_57 = ldq_14_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_398 = l_mask_14 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_28; // @[lsu.scala:1083:46] assign _mask_match_T_28 = _GEN_398; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1084:46] assign _mask_overlap_T_28 = _GEN_398; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_29 = _mask_match_T_28 == l_mask_14; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_29 = |_mask_overlap_T_28; // @[lsu.scala:1084:{46,62}] wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:263:49, :1084:62] wire _T_769 = do_release_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & block_addr_matches_14_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_798 = ldq_14_bits_executed | ldq_14_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_777 = ldq_14_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_781 = do_st_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & (_T_798 | l_forwarders_14_0) & ~ldq_14_bits_addr_is_virtual & _T_777[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_56 = l_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_57 = l_forward_stq_idx_14 < ldq_14_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < ldq_14_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:363:{58,72,78}] wire _T_785 = ~ldq_14_bits_forward_std_val | l_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:363:72] wire _T_791 = do_ld_search_0 & ldq_14_valid & ldq_14_bits_addr_valid & ~ldq_14_bits_addr_is_virtual & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_56 = lcam_ldq_idx_0 < 5'hE; // @[util.scala:363:52] wire _searcher_is_older_T_58 = _searcher_is_older_T_56 ^ _searcher_is_older_T_57; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_59 = ldq_head > 5'hE; // @[util.scala:363:78] wire searcher_is_older_14 = _searcher_is_older_T_58 ^ _searcher_is_older_T_59; // @[util.scala:363:{58,72,78}] wire _GEN_399 = _T_791 & searcher_is_older_14 & (_T_798 | l_forwarders_14_0) & ~s1_executing_loads_14 & ldq_14_bits_observed; // @[util.scala:363:72] assign failed_loads_14 = ~_T_769 & (_T_781 ? _T_785 : _GEN_399); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_14; // @[lsu.scala:1129:57] wire older_nacked_14 = nacking_loads_14 | older_nacked_REG_14; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_800 = ~_T_798 | older_nacked_14; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_400 = searcher_is_older_14 | _GEN_322; // @[util.scala:363:72] wire _GEN_401 = _T_769 | _T_781; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_14; // @[lsu.scala:1132:58] wire _GEN_402 = _GEN_401 | ~_T_791 | _GEN_400 | ~_T_800; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_15; // @[lsu.scala:1665:22] wire _l_mask_mask_T_225 = ldq_15_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_226 = ldq_15_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_227 = 15'h1 << _l_mask_mask_T_226; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_228 = ldq_15_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_229 = ldq_15_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_230 = {_l_mask_mask_T_229, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_231 = 15'h3 << _l_mask_mask_T_230; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_232 = ldq_15_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_233 = ldq_15_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_234 = _l_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_235 = &ldq_15_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_237 = _l_mask_mask_T_232 ? _l_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_238 = _l_mask_mask_T_228 ? _l_mask_mask_T_231 : {7'h0, _l_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_239 = _l_mask_mask_T_225 ? _l_mask_mask_T_227 : _l_mask_mask_T_238; // @[Mux.scala:126:16] assign l_mask_15 = _l_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_30 = wb_forward_ldq_idx_0 == 5'hF; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_31 = wb_forward_valid_0 & _l_forwarders_T_30; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_15_0 = _l_forwarders_T_31; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_15 = l_forwarders_15_0 ? wb_forward_stq_idx_0 : ldq_15_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_46 = ldq_15_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_61 = ldq_15_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_403 = l_mask_15 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_30; // @[lsu.scala:1083:46] assign _mask_match_T_30 = _GEN_403; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1084:46] assign _mask_overlap_T_30 = _GEN_403; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_31 = _mask_match_T_30 == l_mask_15; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_31 = |_mask_overlap_T_30; // @[lsu.scala:1084:{46,62}] wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:263:49, :1084:62] wire _T_805 = do_release_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & block_addr_matches_15_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_834 = ldq_15_bits_executed | ldq_15_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_813 = ldq_15_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_817 = do_st_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & (_T_834 | l_forwarders_15_0) & ~ldq_15_bits_addr_is_virtual & _T_813[0] & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_60 = l_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_61 = l_forward_stq_idx_15 < ldq_15_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < ldq_15_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:363:{58,72,78}] wire _T_821 = ~ldq_15_bits_forward_std_val | l_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15; // @[util.scala:363:72] wire _T_827 = do_ld_search_0 & ldq_15_valid & ldq_15_bits_addr_valid & ~ldq_15_bits_addr_is_virtual & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_60 = lcam_ldq_idx_0 < 5'hF; // @[util.scala:363:52] wire _searcher_is_older_T_62 = _searcher_is_older_T_60 ^ _searcher_is_older_T_61; // @[util.scala:363:{52,58,64}] wire searcher_is_older_15 = _searcher_is_older_T_62 ^ _searcher_is_older_T_63; // @[util.scala:363:{58,72,78}] wire _GEN_404 = _T_827 & searcher_is_older_15 & (_T_834 | l_forwarders_15_0) & ~s1_executing_loads_15 & ldq_15_bits_observed; // @[util.scala:363:72] assign failed_loads_15 = ~_T_805 & (_T_817 ? _T_821 : _GEN_404); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_15; // @[lsu.scala:1129:57] wire older_nacked_15 = nacking_loads_15 | older_nacked_REG_15; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_836 = ~_T_834 | older_nacked_15; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_405 = searcher_is_older_15 | _GEN_323; // @[util.scala:363:72] wire _GEN_406 = _T_805 | _T_817; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_15; // @[lsu.scala:1132:58] wire _GEN_407 = _GEN_406 | ~_T_827 | _GEN_405 | ~_T_836; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_16; // @[lsu.scala:1665:22] wire _l_mask_mask_T_240 = ldq_16_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_241 = ldq_16_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_242 = 15'h1 << _l_mask_mask_T_241; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_243 = ldq_16_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_244 = ldq_16_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_245 = {_l_mask_mask_T_244, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_246 = 15'h3 << _l_mask_mask_T_245; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_247 = ldq_16_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_248 = ldq_16_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_249 = _l_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_250 = &ldq_16_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_252 = _l_mask_mask_T_247 ? _l_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_253 = _l_mask_mask_T_243 ? _l_mask_mask_T_246 : {7'h0, _l_mask_mask_T_252}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_254 = _l_mask_mask_T_240 ? _l_mask_mask_T_242 : _l_mask_mask_T_253; // @[Mux.scala:126:16] assign l_mask_16 = _l_mask_mask_T_254[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_32 = wb_forward_ldq_idx_0 == 5'h10; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_33 = wb_forward_valid_0 & _l_forwarders_T_32; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_16_0 = _l_forwarders_T_33; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_16 = l_forwarders_16_0 ? wb_forward_stq_idx_0 : ldq_16_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_49 = ldq_16_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_50 = _block_addr_matches_T_48 == _block_addr_matches_T_49; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_16_0 = _block_addr_matches_T_50; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_65 = ldq_16_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_67 = block_addr_matches_16_0 & _dword_addr_matches_T_66; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_16_0 = _dword_addr_matches_T_67; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_408 = l_mask_16 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_32; // @[lsu.scala:1083:46] assign _mask_match_T_32 = _GEN_408; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_32; // @[lsu.scala:1084:46] assign _mask_overlap_T_32 = _GEN_408; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_33 = _mask_match_T_32 == l_mask_16; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_16_0 = _mask_match_T_33; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_33 = |_mask_overlap_T_32; // @[lsu.scala:1084:{46,62}] wire mask_overlap_16_0 = _mask_overlap_T_33; // @[lsu.scala:263:49, :1084:62] wire _T_841 = do_release_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & block_addr_matches_16_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_870 = ldq_16_bits_executed | ldq_16_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_849 = ldq_16_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_853 = do_st_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & (_T_870 | l_forwarders_16_0) & ~ldq_16_bits_addr_is_virtual & _T_849[0] & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_64 = l_forward_stq_idx_16 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_65 = l_forward_stq_idx_16 < ldq_16_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < ldq_16_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:363:{58,72,78}] wire _T_857 = ~ldq_16_bits_forward_std_val | l_forward_stq_idx_16 != lcam_stq_idx_0 & forwarded_is_older_16; // @[util.scala:363:72] wire _T_863 = do_ld_search_0 & ldq_16_valid & ldq_16_bits_addr_valid & ~ldq_16_bits_addr_is_virtual & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_64 = ~(lcam_ldq_idx_0[4]); // @[util.scala:363:52] wire _searcher_is_older_T_66 = _searcher_is_older_T_64 ^ _searcher_is_older_T_65; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_67 = ldq_head > 5'h10; // @[util.scala:363:78] wire searcher_is_older_16 = _searcher_is_older_T_66 ^ _searcher_is_older_T_67; // @[util.scala:363:{58,72,78}] wire _GEN_409 = _T_863 & searcher_is_older_16 & (_T_870 | l_forwarders_16_0) & ~s1_executing_loads_16 & ldq_16_bits_observed; // @[util.scala:363:72] assign failed_loads_16 = ~_T_841 & (_T_853 ? _T_857 : _GEN_409); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_16; // @[lsu.scala:1129:57] wire older_nacked_16 = nacking_loads_16 | older_nacked_REG_16; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_872 = ~_T_870 | older_nacked_16; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_410 = searcher_is_older_16 | _GEN_324; // @[util.scala:363:72] wire _GEN_411 = _T_841 | _T_853; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_16; // @[lsu.scala:1132:58] wire _GEN_412 = _GEN_411 | ~_T_863 | _GEN_410 | ~_T_872; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_17; // @[lsu.scala:1665:22] wire _l_mask_mask_T_255 = ldq_17_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_256 = ldq_17_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_257 = 15'h1 << _l_mask_mask_T_256; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_258 = ldq_17_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_259 = ldq_17_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_260 = {_l_mask_mask_T_259, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_261 = 15'h3 << _l_mask_mask_T_260; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_262 = ldq_17_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_263 = ldq_17_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_264 = _l_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_265 = &ldq_17_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_267 = _l_mask_mask_T_262 ? _l_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_268 = _l_mask_mask_T_258 ? _l_mask_mask_T_261 : {7'h0, _l_mask_mask_T_267}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_269 = _l_mask_mask_T_255 ? _l_mask_mask_T_257 : _l_mask_mask_T_268; // @[Mux.scala:126:16] assign l_mask_17 = _l_mask_mask_T_269[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_34 = wb_forward_ldq_idx_0 == 5'h11; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_35 = wb_forward_valid_0 & _l_forwarders_T_34; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_17_0 = _l_forwarders_T_35; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_17 = l_forwarders_17_0 ? wb_forward_stq_idx_0 : ldq_17_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_52 = ldq_17_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_53 = _block_addr_matches_T_51 == _block_addr_matches_T_52; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_17_0 = _block_addr_matches_T_53; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_69 = ldq_17_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_71 = block_addr_matches_17_0 & _dword_addr_matches_T_70; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_17_0 = _dword_addr_matches_T_71; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_413 = l_mask_17 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_34; // @[lsu.scala:1083:46] assign _mask_match_T_34 = _GEN_413; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_34; // @[lsu.scala:1084:46] assign _mask_overlap_T_34 = _GEN_413; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_35 = _mask_match_T_34 == l_mask_17; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_17_0 = _mask_match_T_35; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_35 = |_mask_overlap_T_34; // @[lsu.scala:1084:{46,62}] wire mask_overlap_17_0 = _mask_overlap_T_35; // @[lsu.scala:263:49, :1084:62] wire _T_877 = do_release_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & block_addr_matches_17_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_906 = ldq_17_bits_executed | ldq_17_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_885 = ldq_17_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_889 = do_st_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & (_T_906 | l_forwarders_17_0) & ~ldq_17_bits_addr_is_virtual & _T_885[0] & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_68 = l_forward_stq_idx_17 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_69 = l_forward_stq_idx_17 < ldq_17_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_70 = _forwarded_is_older_T_68 ^ _forwarded_is_older_T_69; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_71 = lcam_stq_idx_0 < ldq_17_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_17 = _forwarded_is_older_T_70 ^ _forwarded_is_older_T_71; // @[util.scala:363:{58,72,78}] wire _T_893 = ~ldq_17_bits_forward_std_val | l_forward_stq_idx_17 != lcam_stq_idx_0 & forwarded_is_older_17; // @[util.scala:363:72] wire _T_899 = do_ld_search_0 & ldq_17_valid & ldq_17_bits_addr_valid & ~ldq_17_bits_addr_is_virtual & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_68 = lcam_ldq_idx_0 < 5'h11; // @[util.scala:363:52] wire _searcher_is_older_T_70 = _searcher_is_older_T_68 ^ _searcher_is_older_T_69; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_71 = ldq_head > 5'h11; // @[util.scala:363:78] wire searcher_is_older_17 = _searcher_is_older_T_70 ^ _searcher_is_older_T_71; // @[util.scala:363:{58,72,78}] wire _GEN_414 = _T_899 & searcher_is_older_17 & (_T_906 | l_forwarders_17_0) & ~s1_executing_loads_17 & ldq_17_bits_observed; // @[util.scala:363:72] assign failed_loads_17 = ~_T_877 & (_T_889 ? _T_893 : _GEN_414); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_17; // @[lsu.scala:1129:57] wire older_nacked_17 = nacking_loads_17 | older_nacked_REG_17; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_908 = ~_T_906 | older_nacked_17; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_415 = searcher_is_older_17 | _GEN_325; // @[util.scala:363:72] wire _GEN_416 = _T_877 | _T_889; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_17; // @[lsu.scala:1132:58] wire _GEN_417 = _GEN_416 | ~_T_899 | _GEN_415 | ~_T_908; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_18; // @[lsu.scala:1665:22] wire _l_mask_mask_T_270 = ldq_18_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_271 = ldq_18_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_272 = 15'h1 << _l_mask_mask_T_271; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_273 = ldq_18_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_274 = ldq_18_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_275 = {_l_mask_mask_T_274, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_276 = 15'h3 << _l_mask_mask_T_275; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_277 = ldq_18_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_278 = ldq_18_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_279 = _l_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_280 = &ldq_18_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_282 = _l_mask_mask_T_277 ? _l_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_283 = _l_mask_mask_T_273 ? _l_mask_mask_T_276 : {7'h0, _l_mask_mask_T_282}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_284 = _l_mask_mask_T_270 ? _l_mask_mask_T_272 : _l_mask_mask_T_283; // @[Mux.scala:126:16] assign l_mask_18 = _l_mask_mask_T_284[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_36 = wb_forward_ldq_idx_0 == 5'h12; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_37 = wb_forward_valid_0 & _l_forwarders_T_36; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_18_0 = _l_forwarders_T_37; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_18 = l_forwarders_18_0 ? wb_forward_stq_idx_0 : ldq_18_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_55 = ldq_18_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_56 = _block_addr_matches_T_54 == _block_addr_matches_T_55; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_18_0 = _block_addr_matches_T_56; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_73 = ldq_18_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 == _dword_addr_matches_T_73; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_75 = block_addr_matches_18_0 & _dword_addr_matches_T_74; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_18_0 = _dword_addr_matches_T_75; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_418 = l_mask_18 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_36; // @[lsu.scala:1083:46] assign _mask_match_T_36 = _GEN_418; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_36; // @[lsu.scala:1084:46] assign _mask_overlap_T_36 = _GEN_418; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_37 = _mask_match_T_36 == l_mask_18; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_18_0 = _mask_match_T_37; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_37 = |_mask_overlap_T_36; // @[lsu.scala:1084:{46,62}] wire mask_overlap_18_0 = _mask_overlap_T_37; // @[lsu.scala:263:49, :1084:62] wire _T_913 = do_release_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & block_addr_matches_18_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_942 = ldq_18_bits_executed | ldq_18_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_921 = ldq_18_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_925 = do_st_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & (_T_942 | l_forwarders_18_0) & ~ldq_18_bits_addr_is_virtual & _T_921[0] & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_72 = l_forward_stq_idx_18 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_73 = l_forward_stq_idx_18 < ldq_18_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_74 = _forwarded_is_older_T_72 ^ _forwarded_is_older_T_73; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_75 = lcam_stq_idx_0 < ldq_18_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_18 = _forwarded_is_older_T_74 ^ _forwarded_is_older_T_75; // @[util.scala:363:{58,72,78}] wire _T_929 = ~ldq_18_bits_forward_std_val | l_forward_stq_idx_18 != lcam_stq_idx_0 & forwarded_is_older_18; // @[util.scala:363:72] wire _T_935 = do_ld_search_0 & ldq_18_valid & ldq_18_bits_addr_valid & ~ldq_18_bits_addr_is_virtual & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_72 = lcam_ldq_idx_0 < 5'h12; // @[util.scala:363:52] wire _searcher_is_older_T_74 = _searcher_is_older_T_72 ^ _searcher_is_older_T_73; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_75 = ldq_head > 5'h12; // @[util.scala:363:78] wire searcher_is_older_18 = _searcher_is_older_T_74 ^ _searcher_is_older_T_75; // @[util.scala:363:{58,72,78}] wire _GEN_419 = _T_935 & searcher_is_older_18 & (_T_942 | l_forwarders_18_0) & ~s1_executing_loads_18 & ldq_18_bits_observed; // @[util.scala:363:72] assign failed_loads_18 = ~_T_913 & (_T_925 ? _T_929 : _GEN_419); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_18; // @[lsu.scala:1129:57] wire older_nacked_18 = nacking_loads_18 | older_nacked_REG_18; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_944 = ~_T_942 | older_nacked_18; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_420 = searcher_is_older_18 | _GEN_326; // @[util.scala:363:72] wire _GEN_421 = _T_913 | _T_925; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_18; // @[lsu.scala:1132:58] wire _GEN_422 = _GEN_421 | ~_T_935 | _GEN_420 | ~_T_944; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_19; // @[lsu.scala:1665:22] wire _l_mask_mask_T_285 = ldq_19_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_286 = ldq_19_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_287 = 15'h1 << _l_mask_mask_T_286; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_288 = ldq_19_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_289 = ldq_19_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_290 = {_l_mask_mask_T_289, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_291 = 15'h3 << _l_mask_mask_T_290; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_292 = ldq_19_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_293 = ldq_19_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_294 = _l_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_295 = &ldq_19_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_297 = _l_mask_mask_T_292 ? _l_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_298 = _l_mask_mask_T_288 ? _l_mask_mask_T_291 : {7'h0, _l_mask_mask_T_297}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_299 = _l_mask_mask_T_285 ? _l_mask_mask_T_287 : _l_mask_mask_T_298; // @[Mux.scala:126:16] assign l_mask_19 = _l_mask_mask_T_299[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_38 = wb_forward_ldq_idx_0 == 5'h13; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_39 = wb_forward_valid_0 & _l_forwarders_T_38; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_19_0 = _l_forwarders_T_39; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_19 = l_forwarders_19_0 ? wb_forward_stq_idx_0 : ldq_19_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_58 = ldq_19_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_59 = _block_addr_matches_T_57 == _block_addr_matches_T_58; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_19_0 = _block_addr_matches_T_59; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_77 = ldq_19_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_79 = block_addr_matches_19_0 & _dword_addr_matches_T_78; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_19_0 = _dword_addr_matches_T_79; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_423 = l_mask_19 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_38; // @[lsu.scala:1083:46] assign _mask_match_T_38 = _GEN_423; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_38; // @[lsu.scala:1084:46] assign _mask_overlap_T_38 = _GEN_423; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_39 = _mask_match_T_38 == l_mask_19; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_19_0 = _mask_match_T_39; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_39 = |_mask_overlap_T_38; // @[lsu.scala:1084:{46,62}] wire mask_overlap_19_0 = _mask_overlap_T_39; // @[lsu.scala:263:49, :1084:62] wire _T_949 = do_release_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & block_addr_matches_19_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_978 = ldq_19_bits_executed | ldq_19_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_957 = ldq_19_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_961 = do_st_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & (_T_978 | l_forwarders_19_0) & ~ldq_19_bits_addr_is_virtual & _T_957[0] & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_76 = l_forward_stq_idx_19 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_77 = l_forward_stq_idx_19 < ldq_19_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_78 = _forwarded_is_older_T_76 ^ _forwarded_is_older_T_77; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_79 = lcam_stq_idx_0 < ldq_19_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_19 = _forwarded_is_older_T_78 ^ _forwarded_is_older_T_79; // @[util.scala:363:{58,72,78}] wire _T_965 = ~ldq_19_bits_forward_std_val | l_forward_stq_idx_19 != lcam_stq_idx_0 & forwarded_is_older_19; // @[util.scala:363:72] wire _T_971 = do_ld_search_0 & ldq_19_valid & ldq_19_bits_addr_valid & ~ldq_19_bits_addr_is_virtual & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_76 = lcam_ldq_idx_0 < 5'h13; // @[util.scala:363:52] wire _searcher_is_older_T_78 = _searcher_is_older_T_76 ^ _searcher_is_older_T_77; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_79 = ldq_head > 5'h13; // @[util.scala:363:78] wire searcher_is_older_19 = _searcher_is_older_T_78 ^ _searcher_is_older_T_79; // @[util.scala:363:{58,72,78}] wire _GEN_424 = _T_971 & searcher_is_older_19 & (_T_978 | l_forwarders_19_0) & ~s1_executing_loads_19 & ldq_19_bits_observed; // @[util.scala:363:72] assign failed_loads_19 = ~_T_949 & (_T_961 ? _T_965 : _GEN_424); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_19; // @[lsu.scala:1129:57] wire older_nacked_19 = nacking_loads_19 | older_nacked_REG_19; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_980 = ~_T_978 | older_nacked_19; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_425 = searcher_is_older_19 | _GEN_327; // @[util.scala:363:72] wire _GEN_426 = _T_949 | _T_961; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_19; // @[lsu.scala:1132:58] wire _GEN_427 = _GEN_426 | ~_T_971 | _GEN_425 | ~_T_980; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_20; // @[lsu.scala:1665:22] wire _l_mask_mask_T_300 = ldq_20_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_301 = ldq_20_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_302 = 15'h1 << _l_mask_mask_T_301; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_303 = ldq_20_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_304 = ldq_20_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_305 = {_l_mask_mask_T_304, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_306 = 15'h3 << _l_mask_mask_T_305; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_307 = ldq_20_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_308 = ldq_20_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_309 = _l_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_310 = &ldq_20_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_312 = _l_mask_mask_T_307 ? _l_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_313 = _l_mask_mask_T_303 ? _l_mask_mask_T_306 : {7'h0, _l_mask_mask_T_312}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_314 = _l_mask_mask_T_300 ? _l_mask_mask_T_302 : _l_mask_mask_T_313; // @[Mux.scala:126:16] assign l_mask_20 = _l_mask_mask_T_314[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_40 = wb_forward_ldq_idx_0 == 5'h14; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_41 = wb_forward_valid_0 & _l_forwarders_T_40; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_20_0 = _l_forwarders_T_41; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_20 = l_forwarders_20_0 ? wb_forward_stq_idx_0 : ldq_20_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_61 = ldq_20_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_62 = _block_addr_matches_T_60 == _block_addr_matches_T_61; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_20_0 = _block_addr_matches_T_62; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_81 = ldq_20_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_82 = _dword_addr_matches_T_80 == _dword_addr_matches_T_81; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_83 = block_addr_matches_20_0 & _dword_addr_matches_T_82; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_20_0 = _dword_addr_matches_T_83; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_428 = l_mask_20 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_40; // @[lsu.scala:1083:46] assign _mask_match_T_40 = _GEN_428; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_40; // @[lsu.scala:1084:46] assign _mask_overlap_T_40 = _GEN_428; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_41 = _mask_match_T_40 == l_mask_20; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_20_0 = _mask_match_T_41; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_41 = |_mask_overlap_T_40; // @[lsu.scala:1084:{46,62}] wire mask_overlap_20_0 = _mask_overlap_T_41; // @[lsu.scala:263:49, :1084:62] wire _T_985 = do_release_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & block_addr_matches_20_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_1014 = ldq_20_bits_executed | ldq_20_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_993 = ldq_20_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_997 = do_st_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & (_T_1014 | l_forwarders_20_0) & ~ldq_20_bits_addr_is_virtual & _T_993[0] & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_80 = l_forward_stq_idx_20 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_81 = l_forward_stq_idx_20 < ldq_20_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_82 = _forwarded_is_older_T_80 ^ _forwarded_is_older_T_81; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_83 = lcam_stq_idx_0 < ldq_20_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_20 = _forwarded_is_older_T_82 ^ _forwarded_is_older_T_83; // @[util.scala:363:{58,72,78}] wire _T_1001 = ~ldq_20_bits_forward_std_val | l_forward_stq_idx_20 != lcam_stq_idx_0 & forwarded_is_older_20; // @[util.scala:363:72] wire _T_1007 = do_ld_search_0 & ldq_20_valid & ldq_20_bits_addr_valid & ~ldq_20_bits_addr_is_virtual & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_80 = lcam_ldq_idx_0 < 5'h14; // @[util.scala:363:52] wire _searcher_is_older_T_82 = _searcher_is_older_T_80 ^ _searcher_is_older_T_81; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_83 = ldq_head > 5'h14; // @[util.scala:363:78] wire searcher_is_older_20 = _searcher_is_older_T_82 ^ _searcher_is_older_T_83; // @[util.scala:363:{58,72,78}] wire _GEN_429 = _T_1007 & searcher_is_older_20 & (_T_1014 | l_forwarders_20_0) & ~s1_executing_loads_20 & ldq_20_bits_observed; // @[util.scala:363:72] assign failed_loads_20 = ~_T_985 & (_T_997 ? _T_1001 : _GEN_429); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_20; // @[lsu.scala:1129:57] wire older_nacked_20 = nacking_loads_20 | older_nacked_REG_20; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_1016 = ~_T_1014 | older_nacked_20; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_430 = searcher_is_older_20 | _GEN_328; // @[util.scala:363:72] wire _GEN_431 = _T_985 | _T_997; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_20; // @[lsu.scala:1132:58] wire _GEN_432 = _GEN_431 | ~_T_1007 | _GEN_430 | ~_T_1016; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_21; // @[lsu.scala:1665:22] wire _l_mask_mask_T_315 = ldq_21_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_316 = ldq_21_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_317 = 15'h1 << _l_mask_mask_T_316; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_318 = ldq_21_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_319 = ldq_21_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_320 = {_l_mask_mask_T_319, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_321 = 15'h3 << _l_mask_mask_T_320; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_322 = ldq_21_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_323 = ldq_21_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_324 = _l_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_325 = &ldq_21_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_327 = _l_mask_mask_T_322 ? _l_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_328 = _l_mask_mask_T_318 ? _l_mask_mask_T_321 : {7'h0, _l_mask_mask_T_327}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_329 = _l_mask_mask_T_315 ? _l_mask_mask_T_317 : _l_mask_mask_T_328; // @[Mux.scala:126:16] assign l_mask_21 = _l_mask_mask_T_329[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_42 = wb_forward_ldq_idx_0 == 5'h15; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_43 = wb_forward_valid_0 & _l_forwarders_T_42; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_21_0 = _l_forwarders_T_43; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_21 = l_forwarders_21_0 ? wb_forward_stq_idx_0 : ldq_21_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_64 = ldq_21_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_65 = _block_addr_matches_T_63 == _block_addr_matches_T_64; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_21_0 = _block_addr_matches_T_65; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_85 = ldq_21_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_86 = _dword_addr_matches_T_84 == _dword_addr_matches_T_85; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_87 = block_addr_matches_21_0 & _dword_addr_matches_T_86; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_21_0 = _dword_addr_matches_T_87; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_433 = l_mask_21 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_42; // @[lsu.scala:1083:46] assign _mask_match_T_42 = _GEN_433; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_42; // @[lsu.scala:1084:46] assign _mask_overlap_T_42 = _GEN_433; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_43 = _mask_match_T_42 == l_mask_21; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_21_0 = _mask_match_T_43; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_43 = |_mask_overlap_T_42; // @[lsu.scala:1084:{46,62}] wire mask_overlap_21_0 = _mask_overlap_T_43; // @[lsu.scala:263:49, :1084:62] wire _T_1021 = do_release_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & block_addr_matches_21_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_1050 = ldq_21_bits_executed | ldq_21_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_1029 = ldq_21_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_1033 = do_st_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & (_T_1050 | l_forwarders_21_0) & ~ldq_21_bits_addr_is_virtual & _T_1029[0] & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_84 = l_forward_stq_idx_21 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_85 = l_forward_stq_idx_21 < ldq_21_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_86 = _forwarded_is_older_T_84 ^ _forwarded_is_older_T_85; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_87 = lcam_stq_idx_0 < ldq_21_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_21 = _forwarded_is_older_T_86 ^ _forwarded_is_older_T_87; // @[util.scala:363:{58,72,78}] wire _T_1037 = ~ldq_21_bits_forward_std_val | l_forward_stq_idx_21 != lcam_stq_idx_0 & forwarded_is_older_21; // @[util.scala:363:72] wire _T_1043 = do_ld_search_0 & ldq_21_valid & ldq_21_bits_addr_valid & ~ldq_21_bits_addr_is_virtual & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_84 = lcam_ldq_idx_0 < 5'h15; // @[util.scala:363:52] wire _searcher_is_older_T_86 = _searcher_is_older_T_84 ^ _searcher_is_older_T_85; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_87 = ldq_head > 5'h15; // @[util.scala:363:78] wire searcher_is_older_21 = _searcher_is_older_T_86 ^ _searcher_is_older_T_87; // @[util.scala:363:{58,72,78}] wire _GEN_434 = _T_1043 & searcher_is_older_21 & (_T_1050 | l_forwarders_21_0) & ~s1_executing_loads_21 & ldq_21_bits_observed; // @[util.scala:363:72] assign failed_loads_21 = ~_T_1021 & (_T_1033 ? _T_1037 : _GEN_434); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_21; // @[lsu.scala:1129:57] wire older_nacked_21 = nacking_loads_21 | older_nacked_REG_21; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_1052 = ~_T_1050 | older_nacked_21; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_435 = searcher_is_older_21 | _GEN_329; // @[util.scala:363:72] wire _GEN_436 = _T_1021 | _T_1033; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_21; // @[lsu.scala:1132:58] wire _GEN_437 = _GEN_436 | ~_T_1043 | _GEN_435 | ~_T_1052; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_22; // @[lsu.scala:1665:22] wire _l_mask_mask_T_330 = ldq_22_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_331 = ldq_22_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_332 = 15'h1 << _l_mask_mask_T_331; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_333 = ldq_22_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_334 = ldq_22_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_335 = {_l_mask_mask_T_334, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_336 = 15'h3 << _l_mask_mask_T_335; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_337 = ldq_22_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_338 = ldq_22_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_339 = _l_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_340 = &ldq_22_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_342 = _l_mask_mask_T_337 ? _l_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_343 = _l_mask_mask_T_333 ? _l_mask_mask_T_336 : {7'h0, _l_mask_mask_T_342}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_344 = _l_mask_mask_T_330 ? _l_mask_mask_T_332 : _l_mask_mask_T_343; // @[Mux.scala:126:16] assign l_mask_22 = _l_mask_mask_T_344[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_44 = wb_forward_ldq_idx_0 == 5'h16; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_45 = wb_forward_valid_0 & _l_forwarders_T_44; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_22_0 = _l_forwarders_T_45; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_22 = l_forwarders_22_0 ? wb_forward_stq_idx_0 : ldq_22_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_67 = ldq_22_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_68 = _block_addr_matches_T_66 == _block_addr_matches_T_67; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_22_0 = _block_addr_matches_T_68; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_89 = ldq_22_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_90 = _dword_addr_matches_T_88 == _dword_addr_matches_T_89; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_91 = block_addr_matches_22_0 & _dword_addr_matches_T_90; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_22_0 = _dword_addr_matches_T_91; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_438 = l_mask_22 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_44; // @[lsu.scala:1083:46] assign _mask_match_T_44 = _GEN_438; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_44; // @[lsu.scala:1084:46] assign _mask_overlap_T_44 = _GEN_438; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_45 = _mask_match_T_44 == l_mask_22; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_22_0 = _mask_match_T_45; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_45 = |_mask_overlap_T_44; // @[lsu.scala:1084:{46,62}] wire mask_overlap_22_0 = _mask_overlap_T_45; // @[lsu.scala:263:49, :1084:62] wire _T_1057 = do_release_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & block_addr_matches_22_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_1086 = ldq_22_bits_executed | ldq_22_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_1065 = ldq_22_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_1069 = do_st_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & (_T_1086 | l_forwarders_22_0) & ~ldq_22_bits_addr_is_virtual & _T_1065[0] & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_88 = l_forward_stq_idx_22 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_89 = l_forward_stq_idx_22 < ldq_22_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_90 = _forwarded_is_older_T_88 ^ _forwarded_is_older_T_89; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_91 = lcam_stq_idx_0 < ldq_22_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_22 = _forwarded_is_older_T_90 ^ _forwarded_is_older_T_91; // @[util.scala:363:{58,72,78}] wire _T_1073 = ~ldq_22_bits_forward_std_val | l_forward_stq_idx_22 != lcam_stq_idx_0 & forwarded_is_older_22; // @[util.scala:363:72] wire _T_1079 = do_ld_search_0 & ldq_22_valid & ldq_22_bits_addr_valid & ~ldq_22_bits_addr_is_virtual & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_88 = lcam_ldq_idx_0 < 5'h16; // @[util.scala:363:52] wire _searcher_is_older_T_90 = _searcher_is_older_T_88 ^ _searcher_is_older_T_89; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_91 = ldq_head > 5'h16; // @[util.scala:363:78] wire searcher_is_older_22 = _searcher_is_older_T_90 ^ _searcher_is_older_T_91; // @[util.scala:363:{58,72,78}] wire _GEN_439 = _T_1079 & searcher_is_older_22 & (_T_1086 | l_forwarders_22_0) & ~s1_executing_loads_22 & ldq_22_bits_observed; // @[util.scala:363:72] assign failed_loads_22 = ~_T_1057 & (_T_1069 ? _T_1073 : _GEN_439); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_22; // @[lsu.scala:1129:57] wire older_nacked_22 = nacking_loads_22 | older_nacked_REG_22; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_1088 = ~_T_1086 | older_nacked_22; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_440 = searcher_is_older_22 | _GEN_330; // @[util.scala:363:72] wire _GEN_441 = _T_1057 | _T_1069; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] reg io_dmem_s1_kill_0_REG_22; // @[lsu.scala:1132:58] wire _GEN_442 = _GEN_441 | ~_T_1079 | _GEN_440 | ~_T_1088; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire [7:0] l_mask_23; // @[lsu.scala:1665:22] wire _l_mask_mask_T_345 = ldq_23_bits_uop_mem_size == 2'h0; // @[lsu.scala:208:16, :1667:26] wire [2:0] _l_mask_mask_T_346 = ldq_23_bits_addr_bits[2:0]; // @[lsu.scala:208:16, :1667:55] wire [14:0] _l_mask_mask_T_347 = 15'h1 << _l_mask_mask_T_346; // @[lsu.scala:1667:{48,55}] wire _l_mask_mask_T_348 = ldq_23_bits_uop_mem_size == 2'h1; // @[lsu.scala:208:16, :1668:26] wire [1:0] _l_mask_mask_T_349 = ldq_23_bits_addr_bits[2:1]; // @[lsu.scala:208:16, :1668:56] wire [2:0] _l_mask_mask_T_350 = {_l_mask_mask_T_349, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _l_mask_mask_T_351 = 15'h3 << _l_mask_mask_T_350; // @[lsu.scala:1668:{48,62}] wire _l_mask_mask_T_352 = ldq_23_bits_uop_mem_size == 2'h2; // @[lsu.scala:208:16, :1669:26] wire _l_mask_mask_T_353 = ldq_23_bits_addr_bits[2]; // @[lsu.scala:208:16, :1669:46] wire [7:0] _l_mask_mask_T_354 = _l_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _l_mask_mask_T_355 = &ldq_23_bits_uop_mem_size; // @[lsu.scala:208:16, :1670:26] wire [7:0] _l_mask_mask_T_357 = _l_mask_mask_T_352 ? _l_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_358 = _l_mask_mask_T_348 ? _l_mask_mask_T_351 : {7'h0, _l_mask_mask_T_357}; // @[Mux.scala:126:16] wire [14:0] _l_mask_mask_T_359 = _l_mask_mask_T_345 ? _l_mask_mask_T_347 : _l_mask_mask_T_358; // @[Mux.scala:126:16] assign l_mask_23 = _l_mask_mask_T_359[7:0]; // @[Mux.scala:126:16] wire _l_forwarders_T_46 = wb_forward_ldq_idx_0 == 5'h17; // @[lsu.scala:1066:36, :1076:88] wire _l_forwarders_T_47 = wb_forward_valid_0 & _l_forwarders_T_46; // @[lsu.scala:1065:36, :1076:{63,88}] wire l_forwarders_23_0 = _l_forwarders_T_47; // @[lsu.scala:263:49, :1076:63] wire [4:0] l_forward_stq_idx_23 = l_forwarders_23_0 ? wb_forward_stq_idx_0 : ldq_23_bits_forward_stq_idx; // @[lsu.scala:208:16, :263:49, :1068:36, :1078:32] wire [33:0] _block_addr_matches_T_70 = ldq_23_bits_addr_bits[39:6]; // @[lsu.scala:208:16, :1081:84] wire _block_addr_matches_T_71 = _block_addr_matches_T_69 == _block_addr_matches_T_70; // @[lsu.scala:1081:{57,73,84}] wire block_addr_matches_23_0 = _block_addr_matches_T_71; // @[lsu.scala:263:49, :1081:73] wire [2:0] _dword_addr_matches_T_93 = ldq_23_bits_addr_bits[5:3]; // @[lsu.scala:208:16, :1082:110] wire _dword_addr_matches_T_94 = _dword_addr_matches_T_92 == _dword_addr_matches_T_93; // @[lsu.scala:1082:{81,100,110}] wire _dword_addr_matches_T_95 = block_addr_matches_23_0 & _dword_addr_matches_T_94; // @[lsu.scala:263:49, :1082:{66,100}] wire dword_addr_matches_23_0 = _dword_addr_matches_T_95; // @[lsu.scala:263:49, :1082:66] wire [7:0] _GEN_443 = l_mask_23 & lcam_mask_0; // @[lsu.scala:263:49, :1083:46, :1665:22] wire [7:0] _mask_match_T_46; // @[lsu.scala:1083:46] assign _mask_match_T_46 = _GEN_443; // @[lsu.scala:1083:46] wire [7:0] _mask_overlap_T_46; // @[lsu.scala:1084:46] assign _mask_overlap_T_46 = _GEN_443; // @[lsu.scala:1083:46, :1084:46] wire _mask_match_T_47 = _mask_match_T_46 == l_mask_23; // @[lsu.scala:1083:{46,62}, :1665:22] wire mask_match_23_0 = _mask_match_T_47; // @[lsu.scala:263:49, :1083:62] wire _mask_overlap_T_47 = |_mask_overlap_T_46; // @[lsu.scala:1084:{46,62}] wire mask_overlap_23_0 = _mask_overlap_T_47; // @[lsu.scala:263:49, :1084:62] wire _T_1093 = do_release_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & block_addr_matches_23_0; // @[lsu.scala:208:16, :263:49, :1089:34, :1090:34, :1091:34] wire _T_1122 = ldq_23_bits_executed | ldq_23_bits_succeeded; // @[lsu.scala:208:16, :1099:37] wire [23:0] _T_1101 = ldq_23_bits_st_dep_mask >> _GEN_305; // @[lsu.scala:208:16, :1101:38] wire _T_1105 = do_st_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & (_T_1122 | l_forwarders_23_0) & ~ldq_23_bits_addr_is_virtual & _T_1101[0] & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:208:16, :263:49, :432:52, :1096:131, :1097:131, :1098:131, :1099:{37,57,131}, :1100:131, :1101:{38,131}, :1102:131] wire _forwarded_is_older_T_92 = l_forward_stq_idx_23 < lcam_stq_idx_0; // @[util.scala:363:52] wire _forwarded_is_older_T_93 = l_forward_stq_idx_23 < ldq_23_bits_youngest_stq_idx; // @[util.scala:363:64] wire _forwarded_is_older_T_94 = _forwarded_is_older_T_92 ^ _forwarded_is_older_T_93; // @[util.scala:363:{52,58,64}] wire _forwarded_is_older_T_95 = lcam_stq_idx_0 < ldq_23_bits_youngest_stq_idx; // @[util.scala:363:78] wire forwarded_is_older_23 = _forwarded_is_older_T_94 ^ _forwarded_is_older_T_95; // @[util.scala:363:{58,72,78}] wire _T_1109 = ~ldq_23_bits_forward_std_val | l_forward_stq_idx_23 != lcam_stq_idx_0 & forwarded_is_older_23; // @[util.scala:363:72] wire _T_1115 = do_ld_search_0 & ldq_23_valid & ldq_23_bits_addr_valid & ~ldq_23_bits_addr_is_virtual & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:208:16, :263:49, :432:52, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47] wire _searcher_is_older_T_92 = lcam_ldq_idx_0 < 5'h17; // @[util.scala:363:52] wire _searcher_is_older_T_94 = _searcher_is_older_T_92 ^ _searcher_is_older_T_93; // @[util.scala:363:{52,58,64}] wire _searcher_is_older_T_95 = ldq_head > 5'h17; // @[util.scala:363:78] wire searcher_is_older_23 = _searcher_is_older_T_94 ^ _searcher_is_older_T_95; // @[util.scala:363:{58,72,78}] wire _GEN_444 = _T_1115 & searcher_is_older_23 & (_T_1122 | l_forwarders_23_0) & ~s1_executing_loads_23 & ldq_23_bits_observed; // @[util.scala:363:72] assign failed_loads_23 = ~_T_1093 & (_T_1105 ? _T_1109 : _GEN_444); // @[lsu.scala:303:5, :1054:34, :1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1107:39, :1108:76, :1117:37, :1119:34, :1120:74, :1121:40, :1122:34, :1123:36] reg older_nacked_REG_23; // @[lsu.scala:1129:57] wire older_nacked_23 = nacking_loads_23 | older_nacked_REG_23; // @[lsu.scala:1055:34, :1129:{47,57}] wire _T_1124 = ~_T_1122 | older_nacked_23; // @[lsu.scala:1099:37, :1129:47, :1130:{17,56}] wire _GEN_445 = searcher_is_older_23 | _GEN_331; // @[util.scala:363:72] wire _GEN_446 = _T_1093 | _T_1105; // @[lsu.scala:1089:34, :1090:34, :1091:34, :1092:36, :1096:131, :1097:131, :1098:131, :1099:131, :1100:131, :1101:131, :1102:131, :1103:37, :1117:37] wire _GEN_447 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _searcher_is_older_T_4)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _searcher_is_older_T_4)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _searcher_is_older_T_4)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _searcher_is_older_T_4)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _searcher_is_older_T_4)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _searcher_is_older_T_4)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _searcher_is_older_T_4)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _searcher_is_older_T_4)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _searcher_is_older_T_4)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _searcher_is_older_T_4)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _searcher_is_older_T_4)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _searcher_is_older_T_4)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _searcher_is_older_T_4)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _searcher_is_older_T_4)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _searcher_is_older_T_4)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _searcher_is_older_T_4)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _searcher_is_older_T_4)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _searcher_is_older_T_4)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _searcher_is_older_T_4)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _searcher_is_older_T_4)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _searcher_is_older_T_4)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _searcher_is_older_T_4)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _searcher_is_older_T_4)) & s1_executing_loads_0; // @[util.scala:363:52] wire _GEN_448 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_309)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_309)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_309)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_309)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_309)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_309)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_309)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_309)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_309)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_309)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_309)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_309)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_309)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_309)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_309)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_309)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_309)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_309)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_309)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_309)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_309)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_309)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_309)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_309)) & s1_executing_loads_1; // @[util.scala:363:72] wire _GEN_449 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_310)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_310)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_310)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_310)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_310)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_310)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_310)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_310)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_310)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_310)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_310)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_310)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_310)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_310)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_310)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_310)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_310)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_310)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_310)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_310)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_310)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_310)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_310)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_310)) & s1_executing_loads_2; // @[util.scala:363:72] wire _GEN_450 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_311)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_311)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_311)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_311)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_311)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_311)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_311)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_311)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_311)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_311)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_311)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_311)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_311)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_311)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_311)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_311)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_311)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_311)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_311)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_311)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_311)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_311)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_311)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_311)) & s1_executing_loads_3; // @[util.scala:363:72] wire _GEN_451 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_312)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_312)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_312)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_312)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_312)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_312)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_312)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_312)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_312)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_312)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_312)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_312)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_312)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_312)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_312)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_312)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_312)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_312)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_312)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_312)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_312)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_312)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_312)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_312)) & s1_executing_loads_4; // @[util.scala:363:72] wire _GEN_452 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_313)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_313)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_313)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_313)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_313)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_313)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_313)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_313)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_313)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_313)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_313)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_313)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_313)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_313)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_313)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_313)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_313)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_313)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_313)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_313)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_313)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_313)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_313)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_313)) & s1_executing_loads_5; // @[util.scala:363:72] wire _GEN_453 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_314)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_314)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_314)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_314)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_314)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_314)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_314)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_314)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_314)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_314)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_314)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_314)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_314)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_314)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_314)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_314)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_314)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_314)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_314)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_314)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_314)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_314)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_314)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_314)) & s1_executing_loads_6; // @[util.scala:363:72] wire _GEN_454 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_315)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_315)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_315)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_315)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_315)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_315)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_315)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_315)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_315)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_315)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_315)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_315)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_315)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_315)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_315)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_315)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_315)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_315)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_315)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_315)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_315)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_315)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_315)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_315)) & s1_executing_loads_7; // @[util.scala:363:72] wire _GEN_455 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_316)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_316)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_316)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_316)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_316)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_316)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_316)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_316)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_316)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_316)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_316)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_316)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_316)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_316)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_316)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_316)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_316)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_316)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_316)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_316)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_316)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_316)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_316)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_316)) & s1_executing_loads_8; // @[util.scala:363:72] wire _GEN_456 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_317)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_317)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_317)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_317)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_317)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_317)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_317)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_317)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_317)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_317)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_317)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_317)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_317)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_317)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_317)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_317)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_317)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_317)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_317)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_317)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_317)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_317)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_317)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_317)) & s1_executing_loads_9; // @[util.scala:363:72] wire _GEN_457 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_318)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_318)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_318)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_318)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_318)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_318)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_318)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_318)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_318)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_318)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_318)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_318)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_318)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_318)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_318)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_318)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_318)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_318)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_318)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_318)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_318)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_318)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_318)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_318)) & s1_executing_loads_10; // @[util.scala:363:72] wire _GEN_458 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_319)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_319)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_319)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_319)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_319)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_319)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_319)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_319)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_319)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_319)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_319)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_319)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_319)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_319)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_319)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_319)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_319)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_319)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_319)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_319)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_319)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_319)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_319)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_319)) & s1_executing_loads_11; // @[util.scala:363:72] wire _GEN_459 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_320)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_320)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_320)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_320)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_320)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_320)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_320)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_320)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_320)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_320)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_320)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_320)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_320)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_320)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_320)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_320)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_320)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_320)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_320)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_320)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_320)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_320)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_320)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_320)) & s1_executing_loads_12; // @[util.scala:363:72] wire _GEN_460 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_321)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_321)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_321)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_321)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_321)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_321)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_321)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_321)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_321)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_321)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_321)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_321)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_321)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_321)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_321)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_321)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_321)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_321)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_321)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_321)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_321)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_321)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_321)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_321)) & s1_executing_loads_13; // @[util.scala:363:72] wire _GEN_461 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_322)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_322)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_322)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_322)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_322)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_322)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_322)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_322)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_322)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_322)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_322)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_322)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_322)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_322)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_322)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_322)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_322)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_322)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_322)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_322)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_322)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_322)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_322)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_322)) & s1_executing_loads_14; // @[util.scala:363:72] wire _GEN_462 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_323)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_323)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_323)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_323)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_323)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_323)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_323)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_323)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_323)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_323)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_323)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_323)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_323)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_323)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_323)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_323)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_323)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_323)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_323)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_323)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_323)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_323)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_323)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_323)) & s1_executing_loads_15; // @[util.scala:363:72] wire _GEN_463 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_324)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_324)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_324)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_324)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_324)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_324)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_324)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_324)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_324)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_324)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_324)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_324)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_324)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_324)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_324)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_324)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_324)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_324)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_324)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_324)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_324)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_324)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_324)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_324)) & s1_executing_loads_16; // @[util.scala:363:72] wire _GEN_464 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_325)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_325)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_325)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_325)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_325)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_325)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_325)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_325)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_325)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_325)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_325)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_325)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_325)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_325)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_325)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_325)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_325)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_325)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_325)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_325)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_325)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_325)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_325)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_325)) & s1_executing_loads_17; // @[util.scala:363:72] wire _GEN_465 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_326)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_326)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_326)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_326)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_326)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_326)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_326)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_326)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_326)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_326)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_326)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_326)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_326)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_326)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_326)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_326)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_326)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_326)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_326)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_326)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_326)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_326)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_326)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_326)) & s1_executing_loads_18; // @[util.scala:363:72] wire _GEN_466 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_327)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_327)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_327)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_327)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_327)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_327)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_327)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_327)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_327)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_327)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_327)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_327)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_327)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_327)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_327)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_327)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_327)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_327)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_327)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_327)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_327)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_327)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_327)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_327)) & s1_executing_loads_19; // @[util.scala:363:72] wire _GEN_467 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_328)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_328)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_328)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_328)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_328)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_328)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_328)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_328)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_328)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_328)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_328)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_328)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_328)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_328)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_328)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_328)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_328)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_328)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_328)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_328)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_328)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_328)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_328)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_328)) & s1_executing_loads_20; // @[util.scala:363:72] wire _GEN_468 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_329)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_329)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_329)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_329)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_329)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_329)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_329)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_329)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_329)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_329)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_329)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_329)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_329)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_329)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_329)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_329)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_329)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_329)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_329)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_329)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_329)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_329)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_329)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_329)) & s1_executing_loads_21; // @[util.scala:363:72] wire _GEN_469 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_330)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_330)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_330)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_330)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_330)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_330)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_330)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_330)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_330)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_330)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_330)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_330)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_330)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_330)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_330)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_330)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_330)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_330)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_330)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_330)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_330)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_330)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_330)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_330)) & s1_executing_loads_22; // @[util.scala:363:72] wire _GEN_470 = (_GEN_446 | ~_T_1115 | _GEN_445 | ~(_T_1124 & _GEN_331)) & (_GEN_441 | ~_T_1079 | _GEN_440 | ~(_T_1088 & _GEN_331)) & (_GEN_436 | ~_T_1043 | _GEN_435 | ~(_T_1052 & _GEN_331)) & (_GEN_431 | ~_T_1007 | _GEN_430 | ~(_T_1016 & _GEN_331)) & (_GEN_426 | ~_T_971 | _GEN_425 | ~(_T_980 & _GEN_331)) & (_GEN_421 | ~_T_935 | _GEN_420 | ~(_T_944 & _GEN_331)) & (_GEN_416 | ~_T_899 | _GEN_415 | ~(_T_908 & _GEN_331)) & (_GEN_411 | ~_T_863 | _GEN_410 | ~(_T_872 & _GEN_331)) & (_GEN_406 | ~_T_827 | _GEN_405 | ~(_T_836 & _GEN_331)) & (_GEN_401 | ~_T_791 | _GEN_400 | ~(_T_800 & _GEN_331)) & (_GEN_396 | ~_T_755 | _GEN_395 | ~(_T_764 & _GEN_331)) & (_GEN_391 | ~_T_719 | _GEN_390 | ~(_T_728 & _GEN_331)) & (_GEN_386 | ~_T_683 | _GEN_385 | ~(_T_692 & _GEN_331)) & (_GEN_381 | ~_T_647 | _GEN_380 | ~(_T_656 & _GEN_331)) & (_GEN_376 | ~_T_611 | _GEN_375 | ~(_T_620 & _GEN_331)) & (_GEN_371 | ~_T_575 | _GEN_370 | ~(_T_584 & _GEN_331)) & (_GEN_366 | ~_T_539 | _GEN_365 | ~(_T_548 & _GEN_331)) & (_GEN_361 | ~_T_503 | _GEN_360 | ~(_T_512 & _GEN_331)) & (_GEN_356 | ~_T_467 | _GEN_355 | ~(_T_476 & _GEN_331)) & (_GEN_351 | ~_T_431 | _GEN_350 | ~(_T_440 & _GEN_331)) & (_GEN_346 | ~_T_395 | _GEN_345 | ~(_T_404 & _GEN_331)) & (_GEN_341 | ~_T_359 | _GEN_340 | ~(_T_368 & _GEN_331)) & (_GEN_336 | ~_T_323 | _GEN_335 | ~(_T_332 & _GEN_331)) & (_GEN_308 | ~_T_287 | searcher_is_older | ~((|lcam_ldq_idx_0) & _T_296 & _GEN_331)) & s1_executing_loads_23; // @[util.scala:363:72] reg io_dmem_s1_kill_0_REG_23; // @[lsu.scala:1132:58] wire _GEN_471 = _GEN_446 | ~_T_1115 | _GEN_445 | ~_T_1124; // @[lsu.scala:1092:36, :1103:37, :1112:47, :1113:47, :1114:47, :1115:47, :1116:47, :1117:37, :1119:34, :1126:{38,47}, :1130:{56,73}] wire _GEN_472 = _GEN_471 ? (_GEN_442 ? (_GEN_437 ? (_GEN_432 ? (_GEN_427 ? (_GEN_422 ? (_GEN_417 ? (_GEN_412 ? (_GEN_407 ? (_GEN_402 ? (_GEN_397 ? (_GEN_392 ? (_GEN_387 ? (_GEN_382 ? (_GEN_377 ? (_GEN_372 ? (_GEN_367 ? (_GEN_362 ? (_GEN_357 ? (_GEN_352 ? (_GEN_347 ? (_GEN_342 ? (_GEN_337 ? ~_GEN_308 & _T_287 & ~searcher_is_older & _GEN_332 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7) : io_dmem_s1_kill_0_REG_8) : io_dmem_s1_kill_0_REG_9) : io_dmem_s1_kill_0_REG_10) : io_dmem_s1_kill_0_REG_11) : io_dmem_s1_kill_0_REG_12) : io_dmem_s1_kill_0_REG_13) : io_dmem_s1_kill_0_REG_14) : io_dmem_s1_kill_0_REG_15) : io_dmem_s1_kill_0_REG_16) : io_dmem_s1_kill_0_REG_17) : io_dmem_s1_kill_0_REG_18) : io_dmem_s1_kill_0_REG_19) : io_dmem_s1_kill_0_REG_20) : io_dmem_s1_kill_0_REG_21) : io_dmem_s1_kill_0_REG_22) : io_dmem_s1_kill_0_REG_23; // @[util.scala:363:72] assign can_forward_0 = _GEN_471 & _GEN_442 & _GEN_437 & _GEN_432 & _GEN_427 & _GEN_422 & _GEN_417 & _GEN_412 & _GEN_407 & _GEN_402 & _GEN_397 & _GEN_392 & _GEN_387 & _GEN_382 & _GEN_377 & _GEN_372 & _GEN_367 & _GEN_362 & _GEN_357 & _GEN_352 & _GEN_347 & _GEN_342 & _GEN_337 & (_GEN_308 | ~_T_287 | searcher_is_older | ~_GEN_332) & _can_forward_WIRE_0; // @[util.scala:363:72] wire _dword_addr_matches_T_96 = ~stq_0_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_97 = stq_0_bits_addr_valid & _dword_addr_matches_T_96; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_98 = stq_0_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire [28:0] _dword_addr_matches_T_99 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_105 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_111 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_117 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_123 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_129 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_135 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_141 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_147 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_153 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_159 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_165 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_171 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_177 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_183 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_189 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_195 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_201 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_207 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_213 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_219 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_225 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_231 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire [28:0] _dword_addr_matches_T_237 = lcam_addr_0[31:3]; // @[lsu.scala:263:49, :1146:74] wire _dword_addr_matches_T_100 = _dword_addr_matches_T_98 == _dword_addr_matches_T_99; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_101 = _dword_addr_matches_T_97 & _dword_addr_matches_T_100; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_24_0 = _dword_addr_matches_T_101; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask; // @[lsu.scala:1665:22] wire _write_mask_mask_T = stq_0_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_1 = stq_0_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_3 = stq_0_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_4 = stq_0_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_7 = stq_0_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_8 = stq_0_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_10 = &stq_0_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _T_1129 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1140 = lcam_mask_0 & write_mask; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1137 = _T_1140 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_24_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_0 = _T_1129 & _T_1137; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_24; // @[lsu.scala:1154:56] wire _T_1142 = (|_T_1140) & dword_addr_matches_24_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_25; // @[lsu.scala:1160:56] wire _T_1145 = stq_0_bits_uop_is_fence | stq_0_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_0 = _T_1129 & (_T_1137 | _T_1142 | _T_1145); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_26; // @[lsu.scala:1166:56] wire _GEN_473 = _T_1129 ? (_T_1137 ? io_dmem_s1_kill_0_REG_24 : _T_1142 ? io_dmem_s1_kill_0_REG_25 : _T_1145 ? io_dmem_s1_kill_0_REG_26 : _GEN_472) : _GEN_472; // @[lsu.scala:1092:36, :1103:37, :1117:37, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_474 = _T_1137 | _T_1142; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_475 = _T_1129 ? (_GEN_474 ? ~_searcher_is_older_T_4 & _GEN_447 : ~(_T_1145 & _searcher_is_older_T_4) & _GEN_447) : _GEN_447; // @[util.scala:363:52] wire _GEN_476 = _T_1129 ? (_GEN_474 ? ~_GEN_309 & _GEN_448 : ~(_T_1145 & _GEN_309) & _GEN_448) : _GEN_448; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_477 = _T_1129 ? (_GEN_474 ? ~_GEN_310 & _GEN_449 : ~(_T_1145 & _GEN_310) & _GEN_449) : _GEN_449; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_478 = _T_1129 ? (_GEN_474 ? ~_GEN_311 & _GEN_450 : ~(_T_1145 & _GEN_311) & _GEN_450) : _GEN_450; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_479 = _T_1129 ? (_GEN_474 ? ~_GEN_312 & _GEN_451 : ~(_T_1145 & _GEN_312) & _GEN_451) : _GEN_451; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_480 = _T_1129 ? (_GEN_474 ? ~_GEN_313 & _GEN_452 : ~(_T_1145 & _GEN_313) & _GEN_452) : _GEN_452; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_481 = _T_1129 ? (_GEN_474 ? ~_GEN_314 & _GEN_453 : ~(_T_1145 & _GEN_314) & _GEN_453) : _GEN_453; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_482 = _T_1129 ? (_GEN_474 ? ~_GEN_315 & _GEN_454 : ~(_T_1145 & _GEN_315) & _GEN_454) : _GEN_454; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_483 = _T_1129 ? (_GEN_474 ? ~_GEN_316 & _GEN_455 : ~(_T_1145 & _GEN_316) & _GEN_455) : _GEN_455; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_484 = _T_1129 ? (_GEN_474 ? ~_GEN_317 & _GEN_456 : ~(_T_1145 & _GEN_317) & _GEN_456) : _GEN_456; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_485 = _T_1129 ? (_GEN_474 ? ~_GEN_318 & _GEN_457 : ~(_T_1145 & _GEN_318) & _GEN_457) : _GEN_457; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_486 = _T_1129 ? (_GEN_474 ? ~_GEN_319 & _GEN_458 : ~(_T_1145 & _GEN_319) & _GEN_458) : _GEN_458; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_487 = _T_1129 ? (_GEN_474 ? ~_GEN_320 & _GEN_459 : ~(_T_1145 & _GEN_320) & _GEN_459) : _GEN_459; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_488 = _T_1129 ? (_GEN_474 ? ~_GEN_321 & _GEN_460 : ~(_T_1145 & _GEN_321) & _GEN_460) : _GEN_460; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_489 = _T_1129 ? (_GEN_474 ? ~_GEN_322 & _GEN_461 : ~(_T_1145 & _GEN_322) & _GEN_461) : _GEN_461; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_490 = _T_1129 ? (_GEN_474 ? ~_GEN_323 & _GEN_462 : ~(_T_1145 & _GEN_323) & _GEN_462) : _GEN_462; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_491 = _T_1129 ? (_GEN_474 ? ~_GEN_324 & _GEN_463 : ~(_T_1145 & _GEN_324) & _GEN_463) : _GEN_463; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_492 = _T_1129 ? (_GEN_474 ? ~_GEN_325 & _GEN_464 : ~(_T_1145 & _GEN_325) & _GEN_464) : _GEN_464; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_493 = _T_1129 ? (_GEN_474 ? ~_GEN_326 & _GEN_465 : ~(_T_1145 & _GEN_326) & _GEN_465) : _GEN_465; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_494 = _T_1129 ? (_GEN_474 ? ~_GEN_327 & _GEN_466 : ~(_T_1145 & _GEN_327) & _GEN_466) : _GEN_466; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_495 = _T_1129 ? (_GEN_474 ? ~_GEN_328 & _GEN_467 : ~(_T_1145 & _GEN_328) & _GEN_467) : _GEN_467; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_496 = _T_1129 ? (_GEN_474 ? ~_GEN_329 & _GEN_468 : ~(_T_1145 & _GEN_329) & _GEN_468) : _GEN_468; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_497 = _T_1129 ? (_GEN_474 ? ~_GEN_330 & _GEN_469 : ~(_T_1145 & _GEN_330) & _GEN_469) : _GEN_469; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_498 = _T_1129 ? (_GEN_474 ? ~_GEN_331 & _GEN_470 : ~(_T_1145 & _GEN_331) & _GEN_470) : _GEN_470; // @[lsu.scala:1058:36, :1092:36, :1103:37, :1117:37, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_102 = ~stq_1_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_103 = stq_1_bits_addr_valid & _dword_addr_matches_T_102; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_104 = stq_1_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_106 = _dword_addr_matches_T_104 == _dword_addr_matches_T_105; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_107 = _dword_addr_matches_T_103 & _dword_addr_matches_T_106; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_25_0 = _dword_addr_matches_T_107; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_1; // @[lsu.scala:1665:22] wire _write_mask_mask_T_15 = stq_1_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_16 = stq_1_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_18 = stq_1_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_19 = stq_1_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_22 = stq_1_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_23 = stq_1_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_25 = &stq_1_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _T_1150 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1161 = lcam_mask_0 & write_mask_1; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1158 = _T_1161 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_25_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_1 = _T_1150 & _T_1158; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_27; // @[lsu.scala:1154:56] wire _T_1163 = (|_T_1161) & dword_addr_matches_25_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_28; // @[lsu.scala:1160:56] wire _T_1166 = stq_1_bits_uop_is_fence | stq_1_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_1 = _T_1150 & (_T_1158 | _T_1163 | _T_1166); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_29; // @[lsu.scala:1166:56] wire _GEN_499 = _T_1150 ? (_T_1158 ? io_dmem_s1_kill_0_REG_27 : _T_1163 ? io_dmem_s1_kill_0_REG_28 : _T_1166 ? io_dmem_s1_kill_0_REG_29 : _GEN_473) : _GEN_473; // @[lsu.scala:1092:36, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_500 = _T_1158 | _T_1163; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_501 = _T_1150 ? (_GEN_500 ? ~_searcher_is_older_T_4 & _GEN_475 : ~(_T_1166 & _searcher_is_older_T_4) & _GEN_475) : _GEN_475; // @[util.scala:363:52] wire _GEN_502 = _T_1150 ? (_GEN_500 ? ~_GEN_309 & _GEN_476 : ~(_T_1166 & _GEN_309) & _GEN_476) : _GEN_476; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_503 = _T_1150 ? (_GEN_500 ? ~_GEN_310 & _GEN_477 : ~(_T_1166 & _GEN_310) & _GEN_477) : _GEN_477; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_504 = _T_1150 ? (_GEN_500 ? ~_GEN_311 & _GEN_478 : ~(_T_1166 & _GEN_311) & _GEN_478) : _GEN_478; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_505 = _T_1150 ? (_GEN_500 ? ~_GEN_312 & _GEN_479 : ~(_T_1166 & _GEN_312) & _GEN_479) : _GEN_479; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_506 = _T_1150 ? (_GEN_500 ? ~_GEN_313 & _GEN_480 : ~(_T_1166 & _GEN_313) & _GEN_480) : _GEN_480; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_507 = _T_1150 ? (_GEN_500 ? ~_GEN_314 & _GEN_481 : ~(_T_1166 & _GEN_314) & _GEN_481) : _GEN_481; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_508 = _T_1150 ? (_GEN_500 ? ~_GEN_315 & _GEN_482 : ~(_T_1166 & _GEN_315) & _GEN_482) : _GEN_482; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_509 = _T_1150 ? (_GEN_500 ? ~_GEN_316 & _GEN_483 : ~(_T_1166 & _GEN_316) & _GEN_483) : _GEN_483; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_510 = _T_1150 ? (_GEN_500 ? ~_GEN_317 & _GEN_484 : ~(_T_1166 & _GEN_317) & _GEN_484) : _GEN_484; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_511 = _T_1150 ? (_GEN_500 ? ~_GEN_318 & _GEN_485 : ~(_T_1166 & _GEN_318) & _GEN_485) : _GEN_485; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_512 = _T_1150 ? (_GEN_500 ? ~_GEN_319 & _GEN_486 : ~(_T_1166 & _GEN_319) & _GEN_486) : _GEN_486; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_513 = _T_1150 ? (_GEN_500 ? ~_GEN_320 & _GEN_487 : ~(_T_1166 & _GEN_320) & _GEN_487) : _GEN_487; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_514 = _T_1150 ? (_GEN_500 ? ~_GEN_321 & _GEN_488 : ~(_T_1166 & _GEN_321) & _GEN_488) : _GEN_488; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_515 = _T_1150 ? (_GEN_500 ? ~_GEN_322 & _GEN_489 : ~(_T_1166 & _GEN_322) & _GEN_489) : _GEN_489; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_516 = _T_1150 ? (_GEN_500 ? ~_GEN_323 & _GEN_490 : ~(_T_1166 & _GEN_323) & _GEN_490) : _GEN_490; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_517 = _T_1150 ? (_GEN_500 ? ~_GEN_324 & _GEN_491 : ~(_T_1166 & _GEN_324) & _GEN_491) : _GEN_491; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_518 = _T_1150 ? (_GEN_500 ? ~_GEN_325 & _GEN_492 : ~(_T_1166 & _GEN_325) & _GEN_492) : _GEN_492; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_519 = _T_1150 ? (_GEN_500 ? ~_GEN_326 & _GEN_493 : ~(_T_1166 & _GEN_326) & _GEN_493) : _GEN_493; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_520 = _T_1150 ? (_GEN_500 ? ~_GEN_327 & _GEN_494 : ~(_T_1166 & _GEN_327) & _GEN_494) : _GEN_494; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_521 = _T_1150 ? (_GEN_500 ? ~_GEN_328 & _GEN_495 : ~(_T_1166 & _GEN_328) & _GEN_495) : _GEN_495; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_522 = _T_1150 ? (_GEN_500 ? ~_GEN_329 & _GEN_496 : ~(_T_1166 & _GEN_329) & _GEN_496) : _GEN_496; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_523 = _T_1150 ? (_GEN_500 ? ~_GEN_330 & _GEN_497 : ~(_T_1166 & _GEN_330) & _GEN_497) : _GEN_497; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_524 = _T_1150 ? (_GEN_500 ? ~_GEN_331 & _GEN_498 : ~(_T_1166 & _GEN_331) & _GEN_498) : _GEN_498; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_108 = ~stq_2_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_109 = stq_2_bits_addr_valid & _dword_addr_matches_T_108; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_110 = stq_2_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_112 = _dword_addr_matches_T_110 == _dword_addr_matches_T_111; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_113 = _dword_addr_matches_T_109 & _dword_addr_matches_T_112; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_26_0 = _dword_addr_matches_T_113; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_2; // @[lsu.scala:1665:22] wire _write_mask_mask_T_30 = stq_2_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_31 = stq_2_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_33 = stq_2_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_34 = stq_2_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_37 = stq_2_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_38 = stq_2_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_40 = &stq_2_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _T_1171 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1182 = lcam_mask_0 & write_mask_2; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1179 = _T_1182 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_26_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_2 = _T_1171 & _T_1179; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_30; // @[lsu.scala:1154:56] wire _T_1184 = (|_T_1182) & dword_addr_matches_26_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_31; // @[lsu.scala:1160:56] wire _T_1187 = stq_2_bits_uop_is_fence | stq_2_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_2 = _T_1171 & (_T_1179 | _T_1184 | _T_1187); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_32; // @[lsu.scala:1166:56] wire _GEN_525 = _T_1171 ? (_T_1179 ? io_dmem_s1_kill_0_REG_30 : _T_1184 ? io_dmem_s1_kill_0_REG_31 : _T_1187 ? io_dmem_s1_kill_0_REG_32 : _GEN_499) : _GEN_499; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_526 = _T_1179 | _T_1184; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_527 = _T_1171 ? (_GEN_526 ? ~_searcher_is_older_T_4 & _GEN_501 : ~(_T_1187 & _searcher_is_older_T_4) & _GEN_501) : _GEN_501; // @[util.scala:363:52] wire _GEN_528 = _T_1171 ? (_GEN_526 ? ~_GEN_309 & _GEN_502 : ~(_T_1187 & _GEN_309) & _GEN_502) : _GEN_502; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_529 = _T_1171 ? (_GEN_526 ? ~_GEN_310 & _GEN_503 : ~(_T_1187 & _GEN_310) & _GEN_503) : _GEN_503; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_530 = _T_1171 ? (_GEN_526 ? ~_GEN_311 & _GEN_504 : ~(_T_1187 & _GEN_311) & _GEN_504) : _GEN_504; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_531 = _T_1171 ? (_GEN_526 ? ~_GEN_312 & _GEN_505 : ~(_T_1187 & _GEN_312) & _GEN_505) : _GEN_505; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_532 = _T_1171 ? (_GEN_526 ? ~_GEN_313 & _GEN_506 : ~(_T_1187 & _GEN_313) & _GEN_506) : _GEN_506; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_533 = _T_1171 ? (_GEN_526 ? ~_GEN_314 & _GEN_507 : ~(_T_1187 & _GEN_314) & _GEN_507) : _GEN_507; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_534 = _T_1171 ? (_GEN_526 ? ~_GEN_315 & _GEN_508 : ~(_T_1187 & _GEN_315) & _GEN_508) : _GEN_508; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_535 = _T_1171 ? (_GEN_526 ? ~_GEN_316 & _GEN_509 : ~(_T_1187 & _GEN_316) & _GEN_509) : _GEN_509; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_536 = _T_1171 ? (_GEN_526 ? ~_GEN_317 & _GEN_510 : ~(_T_1187 & _GEN_317) & _GEN_510) : _GEN_510; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_537 = _T_1171 ? (_GEN_526 ? ~_GEN_318 & _GEN_511 : ~(_T_1187 & _GEN_318) & _GEN_511) : _GEN_511; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_538 = _T_1171 ? (_GEN_526 ? ~_GEN_319 & _GEN_512 : ~(_T_1187 & _GEN_319) & _GEN_512) : _GEN_512; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_539 = _T_1171 ? (_GEN_526 ? ~_GEN_320 & _GEN_513 : ~(_T_1187 & _GEN_320) & _GEN_513) : _GEN_513; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_540 = _T_1171 ? (_GEN_526 ? ~_GEN_321 & _GEN_514 : ~(_T_1187 & _GEN_321) & _GEN_514) : _GEN_514; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_541 = _T_1171 ? (_GEN_526 ? ~_GEN_322 & _GEN_515 : ~(_T_1187 & _GEN_322) & _GEN_515) : _GEN_515; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_542 = _T_1171 ? (_GEN_526 ? ~_GEN_323 & _GEN_516 : ~(_T_1187 & _GEN_323) & _GEN_516) : _GEN_516; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_543 = _T_1171 ? (_GEN_526 ? ~_GEN_324 & _GEN_517 : ~(_T_1187 & _GEN_324) & _GEN_517) : _GEN_517; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_544 = _T_1171 ? (_GEN_526 ? ~_GEN_325 & _GEN_518 : ~(_T_1187 & _GEN_325) & _GEN_518) : _GEN_518; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_545 = _T_1171 ? (_GEN_526 ? ~_GEN_326 & _GEN_519 : ~(_T_1187 & _GEN_326) & _GEN_519) : _GEN_519; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_546 = _T_1171 ? (_GEN_526 ? ~_GEN_327 & _GEN_520 : ~(_T_1187 & _GEN_327) & _GEN_520) : _GEN_520; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_547 = _T_1171 ? (_GEN_526 ? ~_GEN_328 & _GEN_521 : ~(_T_1187 & _GEN_328) & _GEN_521) : _GEN_521; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_548 = _T_1171 ? (_GEN_526 ? ~_GEN_329 & _GEN_522 : ~(_T_1187 & _GEN_329) & _GEN_522) : _GEN_522; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_549 = _T_1171 ? (_GEN_526 ? ~_GEN_330 & _GEN_523 : ~(_T_1187 & _GEN_330) & _GEN_523) : _GEN_523; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_550 = _T_1171 ? (_GEN_526 ? ~_GEN_331 & _GEN_524 : ~(_T_1187 & _GEN_331) & _GEN_524) : _GEN_524; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_114 = ~stq_3_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_115 = stq_3_bits_addr_valid & _dword_addr_matches_T_114; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_116 = stq_3_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_118 = _dword_addr_matches_T_116 == _dword_addr_matches_T_117; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_119 = _dword_addr_matches_T_115 & _dword_addr_matches_T_118; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_27_0 = _dword_addr_matches_T_119; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_3; // @[lsu.scala:1665:22] wire _write_mask_mask_T_45 = stq_3_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_46 = stq_3_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_48 = stq_3_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_49 = stq_3_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_52 = stq_3_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_53 = stq_3_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_55 = &stq_3_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _T_1192 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1203 = lcam_mask_0 & write_mask_3; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1200 = _T_1203 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_27_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_3 = _T_1192 & _T_1200; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_33; // @[lsu.scala:1154:56] wire _T_1205 = (|_T_1203) & dword_addr_matches_27_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_34; // @[lsu.scala:1160:56] wire _T_1208 = stq_3_bits_uop_is_fence | stq_3_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_3 = _T_1192 & (_T_1200 | _T_1205 | _T_1208); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_35; // @[lsu.scala:1166:56] wire _GEN_551 = _T_1192 ? (_T_1200 ? io_dmem_s1_kill_0_REG_33 : _T_1205 ? io_dmem_s1_kill_0_REG_34 : _T_1208 ? io_dmem_s1_kill_0_REG_35 : _GEN_525) : _GEN_525; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_552 = _T_1200 | _T_1205; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_553 = _T_1192 ? (_GEN_552 ? ~_searcher_is_older_T_4 & _GEN_527 : ~(_T_1208 & _searcher_is_older_T_4) & _GEN_527) : _GEN_527; // @[util.scala:363:52] wire _GEN_554 = _T_1192 ? (_GEN_552 ? ~_GEN_309 & _GEN_528 : ~(_T_1208 & _GEN_309) & _GEN_528) : _GEN_528; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_555 = _T_1192 ? (_GEN_552 ? ~_GEN_310 & _GEN_529 : ~(_T_1208 & _GEN_310) & _GEN_529) : _GEN_529; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_556 = _T_1192 ? (_GEN_552 ? ~_GEN_311 & _GEN_530 : ~(_T_1208 & _GEN_311) & _GEN_530) : _GEN_530; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_557 = _T_1192 ? (_GEN_552 ? ~_GEN_312 & _GEN_531 : ~(_T_1208 & _GEN_312) & _GEN_531) : _GEN_531; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_558 = _T_1192 ? (_GEN_552 ? ~_GEN_313 & _GEN_532 : ~(_T_1208 & _GEN_313) & _GEN_532) : _GEN_532; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_559 = _T_1192 ? (_GEN_552 ? ~_GEN_314 & _GEN_533 : ~(_T_1208 & _GEN_314) & _GEN_533) : _GEN_533; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_560 = _T_1192 ? (_GEN_552 ? ~_GEN_315 & _GEN_534 : ~(_T_1208 & _GEN_315) & _GEN_534) : _GEN_534; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_561 = _T_1192 ? (_GEN_552 ? ~_GEN_316 & _GEN_535 : ~(_T_1208 & _GEN_316) & _GEN_535) : _GEN_535; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_562 = _T_1192 ? (_GEN_552 ? ~_GEN_317 & _GEN_536 : ~(_T_1208 & _GEN_317) & _GEN_536) : _GEN_536; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_563 = _T_1192 ? (_GEN_552 ? ~_GEN_318 & _GEN_537 : ~(_T_1208 & _GEN_318) & _GEN_537) : _GEN_537; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_564 = _T_1192 ? (_GEN_552 ? ~_GEN_319 & _GEN_538 : ~(_T_1208 & _GEN_319) & _GEN_538) : _GEN_538; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_565 = _T_1192 ? (_GEN_552 ? ~_GEN_320 & _GEN_539 : ~(_T_1208 & _GEN_320) & _GEN_539) : _GEN_539; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_566 = _T_1192 ? (_GEN_552 ? ~_GEN_321 & _GEN_540 : ~(_T_1208 & _GEN_321) & _GEN_540) : _GEN_540; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_567 = _T_1192 ? (_GEN_552 ? ~_GEN_322 & _GEN_541 : ~(_T_1208 & _GEN_322) & _GEN_541) : _GEN_541; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_568 = _T_1192 ? (_GEN_552 ? ~_GEN_323 & _GEN_542 : ~(_T_1208 & _GEN_323) & _GEN_542) : _GEN_542; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_569 = _T_1192 ? (_GEN_552 ? ~_GEN_324 & _GEN_543 : ~(_T_1208 & _GEN_324) & _GEN_543) : _GEN_543; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_570 = _T_1192 ? (_GEN_552 ? ~_GEN_325 & _GEN_544 : ~(_T_1208 & _GEN_325) & _GEN_544) : _GEN_544; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_571 = _T_1192 ? (_GEN_552 ? ~_GEN_326 & _GEN_545 : ~(_T_1208 & _GEN_326) & _GEN_545) : _GEN_545; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_572 = _T_1192 ? (_GEN_552 ? ~_GEN_327 & _GEN_546 : ~(_T_1208 & _GEN_327) & _GEN_546) : _GEN_546; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_573 = _T_1192 ? (_GEN_552 ? ~_GEN_328 & _GEN_547 : ~(_T_1208 & _GEN_328) & _GEN_547) : _GEN_547; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_574 = _T_1192 ? (_GEN_552 ? ~_GEN_329 & _GEN_548 : ~(_T_1208 & _GEN_329) & _GEN_548) : _GEN_548; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_575 = _T_1192 ? (_GEN_552 ? ~_GEN_330 & _GEN_549 : ~(_T_1208 & _GEN_330) & _GEN_549) : _GEN_549; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_576 = _T_1192 ? (_GEN_552 ? ~_GEN_331 & _GEN_550 : ~(_T_1208 & _GEN_331) & _GEN_550) : _GEN_550; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_120 = ~stq_4_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_121 = stq_4_bits_addr_valid & _dword_addr_matches_T_120; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_122 = stq_4_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_124 = _dword_addr_matches_T_122 == _dword_addr_matches_T_123; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_125 = _dword_addr_matches_T_121 & _dword_addr_matches_T_124; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_28_0 = _dword_addr_matches_T_125; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_4; // @[lsu.scala:1665:22] wire _write_mask_mask_T_60 = stq_4_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_61 = stq_4_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_63 = stq_4_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_64 = stq_4_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_67 = stq_4_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_68 = stq_4_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_70 = &stq_4_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _T_1213 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1224 = lcam_mask_0 & write_mask_4; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1221 = _T_1224 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_28_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_4 = _T_1213 & _T_1221; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_36; // @[lsu.scala:1154:56] wire _T_1226 = (|_T_1224) & dword_addr_matches_28_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_37; // @[lsu.scala:1160:56] wire _T_1229 = stq_4_bits_uop_is_fence | stq_4_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_4 = _T_1213 & (_T_1221 | _T_1226 | _T_1229); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_38; // @[lsu.scala:1166:56] wire _GEN_577 = _T_1213 ? (_T_1221 ? io_dmem_s1_kill_0_REG_36 : _T_1226 ? io_dmem_s1_kill_0_REG_37 : _T_1229 ? io_dmem_s1_kill_0_REG_38 : _GEN_551) : _GEN_551; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_578 = _T_1221 | _T_1226; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_579 = _T_1213 ? (_GEN_578 ? ~_searcher_is_older_T_4 & _GEN_553 : ~(_T_1229 & _searcher_is_older_T_4) & _GEN_553) : _GEN_553; // @[util.scala:363:52] wire _GEN_580 = _T_1213 ? (_GEN_578 ? ~_GEN_309 & _GEN_554 : ~(_T_1229 & _GEN_309) & _GEN_554) : _GEN_554; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_581 = _T_1213 ? (_GEN_578 ? ~_GEN_310 & _GEN_555 : ~(_T_1229 & _GEN_310) & _GEN_555) : _GEN_555; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_582 = _T_1213 ? (_GEN_578 ? ~_GEN_311 & _GEN_556 : ~(_T_1229 & _GEN_311) & _GEN_556) : _GEN_556; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_583 = _T_1213 ? (_GEN_578 ? ~_GEN_312 & _GEN_557 : ~(_T_1229 & _GEN_312) & _GEN_557) : _GEN_557; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_584 = _T_1213 ? (_GEN_578 ? ~_GEN_313 & _GEN_558 : ~(_T_1229 & _GEN_313) & _GEN_558) : _GEN_558; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_585 = _T_1213 ? (_GEN_578 ? ~_GEN_314 & _GEN_559 : ~(_T_1229 & _GEN_314) & _GEN_559) : _GEN_559; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_586 = _T_1213 ? (_GEN_578 ? ~_GEN_315 & _GEN_560 : ~(_T_1229 & _GEN_315) & _GEN_560) : _GEN_560; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_587 = _T_1213 ? (_GEN_578 ? ~_GEN_316 & _GEN_561 : ~(_T_1229 & _GEN_316) & _GEN_561) : _GEN_561; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_588 = _T_1213 ? (_GEN_578 ? ~_GEN_317 & _GEN_562 : ~(_T_1229 & _GEN_317) & _GEN_562) : _GEN_562; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_589 = _T_1213 ? (_GEN_578 ? ~_GEN_318 & _GEN_563 : ~(_T_1229 & _GEN_318) & _GEN_563) : _GEN_563; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_590 = _T_1213 ? (_GEN_578 ? ~_GEN_319 & _GEN_564 : ~(_T_1229 & _GEN_319) & _GEN_564) : _GEN_564; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_591 = _T_1213 ? (_GEN_578 ? ~_GEN_320 & _GEN_565 : ~(_T_1229 & _GEN_320) & _GEN_565) : _GEN_565; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_592 = _T_1213 ? (_GEN_578 ? ~_GEN_321 & _GEN_566 : ~(_T_1229 & _GEN_321) & _GEN_566) : _GEN_566; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_593 = _T_1213 ? (_GEN_578 ? ~_GEN_322 & _GEN_567 : ~(_T_1229 & _GEN_322) & _GEN_567) : _GEN_567; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_594 = _T_1213 ? (_GEN_578 ? ~_GEN_323 & _GEN_568 : ~(_T_1229 & _GEN_323) & _GEN_568) : _GEN_568; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_595 = _T_1213 ? (_GEN_578 ? ~_GEN_324 & _GEN_569 : ~(_T_1229 & _GEN_324) & _GEN_569) : _GEN_569; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_596 = _T_1213 ? (_GEN_578 ? ~_GEN_325 & _GEN_570 : ~(_T_1229 & _GEN_325) & _GEN_570) : _GEN_570; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_597 = _T_1213 ? (_GEN_578 ? ~_GEN_326 & _GEN_571 : ~(_T_1229 & _GEN_326) & _GEN_571) : _GEN_571; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_598 = _T_1213 ? (_GEN_578 ? ~_GEN_327 & _GEN_572 : ~(_T_1229 & _GEN_327) & _GEN_572) : _GEN_572; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_599 = _T_1213 ? (_GEN_578 ? ~_GEN_328 & _GEN_573 : ~(_T_1229 & _GEN_328) & _GEN_573) : _GEN_573; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_600 = _T_1213 ? (_GEN_578 ? ~_GEN_329 & _GEN_574 : ~(_T_1229 & _GEN_329) & _GEN_574) : _GEN_574; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_601 = _T_1213 ? (_GEN_578 ? ~_GEN_330 & _GEN_575 : ~(_T_1229 & _GEN_330) & _GEN_575) : _GEN_575; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_602 = _T_1213 ? (_GEN_578 ? ~_GEN_331 & _GEN_576 : ~(_T_1229 & _GEN_331) & _GEN_576) : _GEN_576; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_126 = ~stq_5_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_127 = stq_5_bits_addr_valid & _dword_addr_matches_T_126; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_128 = stq_5_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 == _dword_addr_matches_T_129; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_131 = _dword_addr_matches_T_127 & _dword_addr_matches_T_130; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_29_0 = _dword_addr_matches_T_131; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_5; // @[lsu.scala:1665:22] wire _write_mask_mask_T_75 = stq_5_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_76 = stq_5_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_78 = stq_5_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_79 = stq_5_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_82 = stq_5_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_83 = stq_5_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_85 = &stq_5_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _T_1234 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1245 = lcam_mask_0 & write_mask_5; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1242 = _T_1245 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_29_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_5 = _T_1234 & _T_1242; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_39; // @[lsu.scala:1154:56] wire _T_1247 = (|_T_1245) & dword_addr_matches_29_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_40; // @[lsu.scala:1160:56] wire _T_1250 = stq_5_bits_uop_is_fence | stq_5_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_5 = _T_1234 & (_T_1242 | _T_1247 | _T_1250); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_41; // @[lsu.scala:1166:56] wire _GEN_603 = _T_1234 ? (_T_1242 ? io_dmem_s1_kill_0_REG_39 : _T_1247 ? io_dmem_s1_kill_0_REG_40 : _T_1250 ? io_dmem_s1_kill_0_REG_41 : _GEN_577) : _GEN_577; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_604 = _T_1242 | _T_1247; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_605 = _T_1234 ? (_GEN_604 ? ~_searcher_is_older_T_4 & _GEN_579 : ~(_T_1250 & _searcher_is_older_T_4) & _GEN_579) : _GEN_579; // @[util.scala:363:52] wire _GEN_606 = _T_1234 ? (_GEN_604 ? ~_GEN_309 & _GEN_580 : ~(_T_1250 & _GEN_309) & _GEN_580) : _GEN_580; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_607 = _T_1234 ? (_GEN_604 ? ~_GEN_310 & _GEN_581 : ~(_T_1250 & _GEN_310) & _GEN_581) : _GEN_581; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_608 = _T_1234 ? (_GEN_604 ? ~_GEN_311 & _GEN_582 : ~(_T_1250 & _GEN_311) & _GEN_582) : _GEN_582; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_609 = _T_1234 ? (_GEN_604 ? ~_GEN_312 & _GEN_583 : ~(_T_1250 & _GEN_312) & _GEN_583) : _GEN_583; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_610 = _T_1234 ? (_GEN_604 ? ~_GEN_313 & _GEN_584 : ~(_T_1250 & _GEN_313) & _GEN_584) : _GEN_584; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_611 = _T_1234 ? (_GEN_604 ? ~_GEN_314 & _GEN_585 : ~(_T_1250 & _GEN_314) & _GEN_585) : _GEN_585; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_612 = _T_1234 ? (_GEN_604 ? ~_GEN_315 & _GEN_586 : ~(_T_1250 & _GEN_315) & _GEN_586) : _GEN_586; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_613 = _T_1234 ? (_GEN_604 ? ~_GEN_316 & _GEN_587 : ~(_T_1250 & _GEN_316) & _GEN_587) : _GEN_587; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_614 = _T_1234 ? (_GEN_604 ? ~_GEN_317 & _GEN_588 : ~(_T_1250 & _GEN_317) & _GEN_588) : _GEN_588; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_615 = _T_1234 ? (_GEN_604 ? ~_GEN_318 & _GEN_589 : ~(_T_1250 & _GEN_318) & _GEN_589) : _GEN_589; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_616 = _T_1234 ? (_GEN_604 ? ~_GEN_319 & _GEN_590 : ~(_T_1250 & _GEN_319) & _GEN_590) : _GEN_590; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_617 = _T_1234 ? (_GEN_604 ? ~_GEN_320 & _GEN_591 : ~(_T_1250 & _GEN_320) & _GEN_591) : _GEN_591; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_618 = _T_1234 ? (_GEN_604 ? ~_GEN_321 & _GEN_592 : ~(_T_1250 & _GEN_321) & _GEN_592) : _GEN_592; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_619 = _T_1234 ? (_GEN_604 ? ~_GEN_322 & _GEN_593 : ~(_T_1250 & _GEN_322) & _GEN_593) : _GEN_593; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_620 = _T_1234 ? (_GEN_604 ? ~_GEN_323 & _GEN_594 : ~(_T_1250 & _GEN_323) & _GEN_594) : _GEN_594; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_621 = _T_1234 ? (_GEN_604 ? ~_GEN_324 & _GEN_595 : ~(_T_1250 & _GEN_324) & _GEN_595) : _GEN_595; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_622 = _T_1234 ? (_GEN_604 ? ~_GEN_325 & _GEN_596 : ~(_T_1250 & _GEN_325) & _GEN_596) : _GEN_596; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_623 = _T_1234 ? (_GEN_604 ? ~_GEN_326 & _GEN_597 : ~(_T_1250 & _GEN_326) & _GEN_597) : _GEN_597; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_624 = _T_1234 ? (_GEN_604 ? ~_GEN_327 & _GEN_598 : ~(_T_1250 & _GEN_327) & _GEN_598) : _GEN_598; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_625 = _T_1234 ? (_GEN_604 ? ~_GEN_328 & _GEN_599 : ~(_T_1250 & _GEN_328) & _GEN_599) : _GEN_599; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_626 = _T_1234 ? (_GEN_604 ? ~_GEN_329 & _GEN_600 : ~(_T_1250 & _GEN_329) & _GEN_600) : _GEN_600; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_627 = _T_1234 ? (_GEN_604 ? ~_GEN_330 & _GEN_601 : ~(_T_1250 & _GEN_330) & _GEN_601) : _GEN_601; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_628 = _T_1234 ? (_GEN_604 ? ~_GEN_331 & _GEN_602 : ~(_T_1250 & _GEN_331) & _GEN_602) : _GEN_602; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_132 = ~stq_6_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_133 = stq_6_bits_addr_valid & _dword_addr_matches_T_132; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_134 = stq_6_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_136 = _dword_addr_matches_T_134 == _dword_addr_matches_T_135; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_137 = _dword_addr_matches_T_133 & _dword_addr_matches_T_136; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_30_0 = _dword_addr_matches_T_137; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_6; // @[lsu.scala:1665:22] wire _write_mask_mask_T_90 = stq_6_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_91 = stq_6_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_93 = stq_6_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_94 = stq_6_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_97 = stq_6_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_98 = stq_6_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_100 = &stq_6_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _T_1255 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1266 = lcam_mask_0 & write_mask_6; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1263 = _T_1266 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_30_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_6 = _T_1255 & _T_1263; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_42; // @[lsu.scala:1154:56] wire _T_1268 = (|_T_1266) & dword_addr_matches_30_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_43; // @[lsu.scala:1160:56] wire _T_1271 = stq_6_bits_uop_is_fence | stq_6_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_6 = _T_1255 & (_T_1263 | _T_1268 | _T_1271); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_44; // @[lsu.scala:1166:56] wire _GEN_629 = _T_1255 ? (_T_1263 ? io_dmem_s1_kill_0_REG_42 : _T_1268 ? io_dmem_s1_kill_0_REG_43 : _T_1271 ? io_dmem_s1_kill_0_REG_44 : _GEN_603) : _GEN_603; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_630 = _T_1263 | _T_1268; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_631 = _T_1255 ? (_GEN_630 ? ~_searcher_is_older_T_4 & _GEN_605 : ~(_T_1271 & _searcher_is_older_T_4) & _GEN_605) : _GEN_605; // @[util.scala:363:52] wire _GEN_632 = _T_1255 ? (_GEN_630 ? ~_GEN_309 & _GEN_606 : ~(_T_1271 & _GEN_309) & _GEN_606) : _GEN_606; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_633 = _T_1255 ? (_GEN_630 ? ~_GEN_310 & _GEN_607 : ~(_T_1271 & _GEN_310) & _GEN_607) : _GEN_607; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_634 = _T_1255 ? (_GEN_630 ? ~_GEN_311 & _GEN_608 : ~(_T_1271 & _GEN_311) & _GEN_608) : _GEN_608; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_635 = _T_1255 ? (_GEN_630 ? ~_GEN_312 & _GEN_609 : ~(_T_1271 & _GEN_312) & _GEN_609) : _GEN_609; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_636 = _T_1255 ? (_GEN_630 ? ~_GEN_313 & _GEN_610 : ~(_T_1271 & _GEN_313) & _GEN_610) : _GEN_610; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_637 = _T_1255 ? (_GEN_630 ? ~_GEN_314 & _GEN_611 : ~(_T_1271 & _GEN_314) & _GEN_611) : _GEN_611; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_638 = _T_1255 ? (_GEN_630 ? ~_GEN_315 & _GEN_612 : ~(_T_1271 & _GEN_315) & _GEN_612) : _GEN_612; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_639 = _T_1255 ? (_GEN_630 ? ~_GEN_316 & _GEN_613 : ~(_T_1271 & _GEN_316) & _GEN_613) : _GEN_613; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_640 = _T_1255 ? (_GEN_630 ? ~_GEN_317 & _GEN_614 : ~(_T_1271 & _GEN_317) & _GEN_614) : _GEN_614; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_641 = _T_1255 ? (_GEN_630 ? ~_GEN_318 & _GEN_615 : ~(_T_1271 & _GEN_318) & _GEN_615) : _GEN_615; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_642 = _T_1255 ? (_GEN_630 ? ~_GEN_319 & _GEN_616 : ~(_T_1271 & _GEN_319) & _GEN_616) : _GEN_616; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_643 = _T_1255 ? (_GEN_630 ? ~_GEN_320 & _GEN_617 : ~(_T_1271 & _GEN_320) & _GEN_617) : _GEN_617; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_644 = _T_1255 ? (_GEN_630 ? ~_GEN_321 & _GEN_618 : ~(_T_1271 & _GEN_321) & _GEN_618) : _GEN_618; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_645 = _T_1255 ? (_GEN_630 ? ~_GEN_322 & _GEN_619 : ~(_T_1271 & _GEN_322) & _GEN_619) : _GEN_619; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_646 = _T_1255 ? (_GEN_630 ? ~_GEN_323 & _GEN_620 : ~(_T_1271 & _GEN_323) & _GEN_620) : _GEN_620; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_647 = _T_1255 ? (_GEN_630 ? ~_GEN_324 & _GEN_621 : ~(_T_1271 & _GEN_324) & _GEN_621) : _GEN_621; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_648 = _T_1255 ? (_GEN_630 ? ~_GEN_325 & _GEN_622 : ~(_T_1271 & _GEN_325) & _GEN_622) : _GEN_622; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_649 = _T_1255 ? (_GEN_630 ? ~_GEN_326 & _GEN_623 : ~(_T_1271 & _GEN_326) & _GEN_623) : _GEN_623; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_650 = _T_1255 ? (_GEN_630 ? ~_GEN_327 & _GEN_624 : ~(_T_1271 & _GEN_327) & _GEN_624) : _GEN_624; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_651 = _T_1255 ? (_GEN_630 ? ~_GEN_328 & _GEN_625 : ~(_T_1271 & _GEN_328) & _GEN_625) : _GEN_625; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_652 = _T_1255 ? (_GEN_630 ? ~_GEN_329 & _GEN_626 : ~(_T_1271 & _GEN_329) & _GEN_626) : _GEN_626; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_653 = _T_1255 ? (_GEN_630 ? ~_GEN_330 & _GEN_627 : ~(_T_1271 & _GEN_330) & _GEN_627) : _GEN_627; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_654 = _T_1255 ? (_GEN_630 ? ~_GEN_331 & _GEN_628 : ~(_T_1271 & _GEN_331) & _GEN_628) : _GEN_628; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_138 = ~stq_7_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_139 = stq_7_bits_addr_valid & _dword_addr_matches_T_138; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_140 = stq_7_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_142 = _dword_addr_matches_T_140 == _dword_addr_matches_T_141; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_143 = _dword_addr_matches_T_139 & _dword_addr_matches_T_142; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_31_0 = _dword_addr_matches_T_143; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_7; // @[lsu.scala:1665:22] wire _write_mask_mask_T_105 = stq_7_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_106 = stq_7_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_108 = stq_7_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_109 = stq_7_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_112 = stq_7_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_113 = stq_7_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_115 = &stq_7_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _T_1276 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1287 = lcam_mask_0 & write_mask_7; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1284 = _T_1287 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_31_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_7 = _T_1276 & _T_1284; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_45; // @[lsu.scala:1154:56] wire _T_1289 = (|_T_1287) & dword_addr_matches_31_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_46; // @[lsu.scala:1160:56] wire _T_1292 = stq_7_bits_uop_is_fence | stq_7_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_7 = _T_1276 & (_T_1284 | _T_1289 | _T_1292); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_47; // @[lsu.scala:1166:56] wire _GEN_655 = _T_1276 ? (_T_1284 ? io_dmem_s1_kill_0_REG_45 : _T_1289 ? io_dmem_s1_kill_0_REG_46 : _T_1292 ? io_dmem_s1_kill_0_REG_47 : _GEN_629) : _GEN_629; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_656 = _T_1284 | _T_1289; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_657 = _T_1276 ? (_GEN_656 ? ~_searcher_is_older_T_4 & _GEN_631 : ~(_T_1292 & _searcher_is_older_T_4) & _GEN_631) : _GEN_631; // @[util.scala:363:52] wire _GEN_658 = _T_1276 ? (_GEN_656 ? ~_GEN_309 & _GEN_632 : ~(_T_1292 & _GEN_309) & _GEN_632) : _GEN_632; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_659 = _T_1276 ? (_GEN_656 ? ~_GEN_310 & _GEN_633 : ~(_T_1292 & _GEN_310) & _GEN_633) : _GEN_633; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_660 = _T_1276 ? (_GEN_656 ? ~_GEN_311 & _GEN_634 : ~(_T_1292 & _GEN_311) & _GEN_634) : _GEN_634; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_661 = _T_1276 ? (_GEN_656 ? ~_GEN_312 & _GEN_635 : ~(_T_1292 & _GEN_312) & _GEN_635) : _GEN_635; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_662 = _T_1276 ? (_GEN_656 ? ~_GEN_313 & _GEN_636 : ~(_T_1292 & _GEN_313) & _GEN_636) : _GEN_636; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_663 = _T_1276 ? (_GEN_656 ? ~_GEN_314 & _GEN_637 : ~(_T_1292 & _GEN_314) & _GEN_637) : _GEN_637; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_664 = _T_1276 ? (_GEN_656 ? ~_GEN_315 & _GEN_638 : ~(_T_1292 & _GEN_315) & _GEN_638) : _GEN_638; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_665 = _T_1276 ? (_GEN_656 ? ~_GEN_316 & _GEN_639 : ~(_T_1292 & _GEN_316) & _GEN_639) : _GEN_639; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_666 = _T_1276 ? (_GEN_656 ? ~_GEN_317 & _GEN_640 : ~(_T_1292 & _GEN_317) & _GEN_640) : _GEN_640; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_667 = _T_1276 ? (_GEN_656 ? ~_GEN_318 & _GEN_641 : ~(_T_1292 & _GEN_318) & _GEN_641) : _GEN_641; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_668 = _T_1276 ? (_GEN_656 ? ~_GEN_319 & _GEN_642 : ~(_T_1292 & _GEN_319) & _GEN_642) : _GEN_642; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_669 = _T_1276 ? (_GEN_656 ? ~_GEN_320 & _GEN_643 : ~(_T_1292 & _GEN_320) & _GEN_643) : _GEN_643; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_670 = _T_1276 ? (_GEN_656 ? ~_GEN_321 & _GEN_644 : ~(_T_1292 & _GEN_321) & _GEN_644) : _GEN_644; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_671 = _T_1276 ? (_GEN_656 ? ~_GEN_322 & _GEN_645 : ~(_T_1292 & _GEN_322) & _GEN_645) : _GEN_645; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_672 = _T_1276 ? (_GEN_656 ? ~_GEN_323 & _GEN_646 : ~(_T_1292 & _GEN_323) & _GEN_646) : _GEN_646; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_673 = _T_1276 ? (_GEN_656 ? ~_GEN_324 & _GEN_647 : ~(_T_1292 & _GEN_324) & _GEN_647) : _GEN_647; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_674 = _T_1276 ? (_GEN_656 ? ~_GEN_325 & _GEN_648 : ~(_T_1292 & _GEN_325) & _GEN_648) : _GEN_648; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_675 = _T_1276 ? (_GEN_656 ? ~_GEN_326 & _GEN_649 : ~(_T_1292 & _GEN_326) & _GEN_649) : _GEN_649; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_676 = _T_1276 ? (_GEN_656 ? ~_GEN_327 & _GEN_650 : ~(_T_1292 & _GEN_327) & _GEN_650) : _GEN_650; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_677 = _T_1276 ? (_GEN_656 ? ~_GEN_328 & _GEN_651 : ~(_T_1292 & _GEN_328) & _GEN_651) : _GEN_651; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_678 = _T_1276 ? (_GEN_656 ? ~_GEN_329 & _GEN_652 : ~(_T_1292 & _GEN_329) & _GEN_652) : _GEN_652; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_679 = _T_1276 ? (_GEN_656 ? ~_GEN_330 & _GEN_653 : ~(_T_1292 & _GEN_330) & _GEN_653) : _GEN_653; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_680 = _T_1276 ? (_GEN_656 ? ~_GEN_331 & _GEN_654 : ~(_T_1292 & _GEN_331) & _GEN_654) : _GEN_654; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_144 = ~stq_8_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_145 = stq_8_bits_addr_valid & _dword_addr_matches_T_144; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_146 = stq_8_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_148 = _dword_addr_matches_T_146 == _dword_addr_matches_T_147; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_149 = _dword_addr_matches_T_145 & _dword_addr_matches_T_148; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_32_0 = _dword_addr_matches_T_149; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_8; // @[lsu.scala:1665:22] wire _write_mask_mask_T_120 = stq_8_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_121 = stq_8_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_123 = stq_8_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_124 = stq_8_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_127 = stq_8_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_128 = stq_8_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_130 = &stq_8_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16] assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _T_1297 = do_ld_search_0 & stq_8_valid & lcam_st_dep_mask_0[8]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1308 = lcam_mask_0 & write_mask_8; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1305 = _T_1308 == lcam_mask_0 & ~stq_8_bits_uop_is_fence & ~stq_8_bits_uop_is_amo & dword_addr_matches_32_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_8 = _T_1297 & _T_1305; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_48; // @[lsu.scala:1154:56] wire _T_1310 = (|_T_1308) & dword_addr_matches_32_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_49; // @[lsu.scala:1160:56] wire _T_1313 = stq_8_bits_uop_is_fence | stq_8_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_8 = _T_1297 & (_T_1305 | _T_1310 | _T_1313); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_50; // @[lsu.scala:1166:56] wire _GEN_681 = _T_1297 ? (_T_1305 ? io_dmem_s1_kill_0_REG_48 : _T_1310 ? io_dmem_s1_kill_0_REG_49 : _T_1313 ? io_dmem_s1_kill_0_REG_50 : _GEN_655) : _GEN_655; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_682 = _T_1305 | _T_1310; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_683 = _T_1297 ? (_GEN_682 ? ~_searcher_is_older_T_4 & _GEN_657 : ~(_T_1313 & _searcher_is_older_T_4) & _GEN_657) : _GEN_657; // @[util.scala:363:52] wire _GEN_684 = _T_1297 ? (_GEN_682 ? ~_GEN_309 & _GEN_658 : ~(_T_1313 & _GEN_309) & _GEN_658) : _GEN_658; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_685 = _T_1297 ? (_GEN_682 ? ~_GEN_310 & _GEN_659 : ~(_T_1313 & _GEN_310) & _GEN_659) : _GEN_659; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_686 = _T_1297 ? (_GEN_682 ? ~_GEN_311 & _GEN_660 : ~(_T_1313 & _GEN_311) & _GEN_660) : _GEN_660; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_687 = _T_1297 ? (_GEN_682 ? ~_GEN_312 & _GEN_661 : ~(_T_1313 & _GEN_312) & _GEN_661) : _GEN_661; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_688 = _T_1297 ? (_GEN_682 ? ~_GEN_313 & _GEN_662 : ~(_T_1313 & _GEN_313) & _GEN_662) : _GEN_662; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_689 = _T_1297 ? (_GEN_682 ? ~_GEN_314 & _GEN_663 : ~(_T_1313 & _GEN_314) & _GEN_663) : _GEN_663; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_690 = _T_1297 ? (_GEN_682 ? ~_GEN_315 & _GEN_664 : ~(_T_1313 & _GEN_315) & _GEN_664) : _GEN_664; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_691 = _T_1297 ? (_GEN_682 ? ~_GEN_316 & _GEN_665 : ~(_T_1313 & _GEN_316) & _GEN_665) : _GEN_665; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_692 = _T_1297 ? (_GEN_682 ? ~_GEN_317 & _GEN_666 : ~(_T_1313 & _GEN_317) & _GEN_666) : _GEN_666; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_693 = _T_1297 ? (_GEN_682 ? ~_GEN_318 & _GEN_667 : ~(_T_1313 & _GEN_318) & _GEN_667) : _GEN_667; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_694 = _T_1297 ? (_GEN_682 ? ~_GEN_319 & _GEN_668 : ~(_T_1313 & _GEN_319) & _GEN_668) : _GEN_668; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_695 = _T_1297 ? (_GEN_682 ? ~_GEN_320 & _GEN_669 : ~(_T_1313 & _GEN_320) & _GEN_669) : _GEN_669; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_696 = _T_1297 ? (_GEN_682 ? ~_GEN_321 & _GEN_670 : ~(_T_1313 & _GEN_321) & _GEN_670) : _GEN_670; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_697 = _T_1297 ? (_GEN_682 ? ~_GEN_322 & _GEN_671 : ~(_T_1313 & _GEN_322) & _GEN_671) : _GEN_671; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_698 = _T_1297 ? (_GEN_682 ? ~_GEN_323 & _GEN_672 : ~(_T_1313 & _GEN_323) & _GEN_672) : _GEN_672; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_699 = _T_1297 ? (_GEN_682 ? ~_GEN_324 & _GEN_673 : ~(_T_1313 & _GEN_324) & _GEN_673) : _GEN_673; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_700 = _T_1297 ? (_GEN_682 ? ~_GEN_325 & _GEN_674 : ~(_T_1313 & _GEN_325) & _GEN_674) : _GEN_674; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_701 = _T_1297 ? (_GEN_682 ? ~_GEN_326 & _GEN_675 : ~(_T_1313 & _GEN_326) & _GEN_675) : _GEN_675; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_702 = _T_1297 ? (_GEN_682 ? ~_GEN_327 & _GEN_676 : ~(_T_1313 & _GEN_327) & _GEN_676) : _GEN_676; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_703 = _T_1297 ? (_GEN_682 ? ~_GEN_328 & _GEN_677 : ~(_T_1313 & _GEN_328) & _GEN_677) : _GEN_677; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_704 = _T_1297 ? (_GEN_682 ? ~_GEN_329 & _GEN_678 : ~(_T_1313 & _GEN_329) & _GEN_678) : _GEN_678; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_705 = _T_1297 ? (_GEN_682 ? ~_GEN_330 & _GEN_679 : ~(_T_1313 & _GEN_330) & _GEN_679) : _GEN_679; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_706 = _T_1297 ? (_GEN_682 ? ~_GEN_331 & _GEN_680 : ~(_T_1313 & _GEN_331) & _GEN_680) : _GEN_680; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_150 = ~stq_9_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_151 = stq_9_bits_addr_valid & _dword_addr_matches_T_150; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_152 = stq_9_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_154 = _dword_addr_matches_T_152 == _dword_addr_matches_T_153; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_155 = _dword_addr_matches_T_151 & _dword_addr_matches_T_154; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_33_0 = _dword_addr_matches_T_155; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_9; // @[lsu.scala:1665:22] wire _write_mask_mask_T_135 = stq_9_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_136 = stq_9_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_138 = stq_9_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_139 = stq_9_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_142 = stq_9_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_143 = stq_9_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_145 = &stq_9_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16] assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _T_1318 = do_ld_search_0 & stq_9_valid & lcam_st_dep_mask_0[9]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1329 = lcam_mask_0 & write_mask_9; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1326 = _T_1329 == lcam_mask_0 & ~stq_9_bits_uop_is_fence & ~stq_9_bits_uop_is_amo & dword_addr_matches_33_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_9 = _T_1318 & _T_1326; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_51; // @[lsu.scala:1154:56] wire _T_1331 = (|_T_1329) & dword_addr_matches_33_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_52; // @[lsu.scala:1160:56] wire _T_1334 = stq_9_bits_uop_is_fence | stq_9_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_9 = _T_1318 & (_T_1326 | _T_1331 | _T_1334); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_53; // @[lsu.scala:1166:56] wire _GEN_707 = _T_1318 ? (_T_1326 ? io_dmem_s1_kill_0_REG_51 : _T_1331 ? io_dmem_s1_kill_0_REG_52 : _T_1334 ? io_dmem_s1_kill_0_REG_53 : _GEN_681) : _GEN_681; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_708 = _T_1326 | _T_1331; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_709 = _T_1318 ? (_GEN_708 ? ~_searcher_is_older_T_4 & _GEN_683 : ~(_T_1334 & _searcher_is_older_T_4) & _GEN_683) : _GEN_683; // @[util.scala:363:52] wire _GEN_710 = _T_1318 ? (_GEN_708 ? ~_GEN_309 & _GEN_684 : ~(_T_1334 & _GEN_309) & _GEN_684) : _GEN_684; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_711 = _T_1318 ? (_GEN_708 ? ~_GEN_310 & _GEN_685 : ~(_T_1334 & _GEN_310) & _GEN_685) : _GEN_685; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_712 = _T_1318 ? (_GEN_708 ? ~_GEN_311 & _GEN_686 : ~(_T_1334 & _GEN_311) & _GEN_686) : _GEN_686; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_713 = _T_1318 ? (_GEN_708 ? ~_GEN_312 & _GEN_687 : ~(_T_1334 & _GEN_312) & _GEN_687) : _GEN_687; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_714 = _T_1318 ? (_GEN_708 ? ~_GEN_313 & _GEN_688 : ~(_T_1334 & _GEN_313) & _GEN_688) : _GEN_688; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_715 = _T_1318 ? (_GEN_708 ? ~_GEN_314 & _GEN_689 : ~(_T_1334 & _GEN_314) & _GEN_689) : _GEN_689; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_716 = _T_1318 ? (_GEN_708 ? ~_GEN_315 & _GEN_690 : ~(_T_1334 & _GEN_315) & _GEN_690) : _GEN_690; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_717 = _T_1318 ? (_GEN_708 ? ~_GEN_316 & _GEN_691 : ~(_T_1334 & _GEN_316) & _GEN_691) : _GEN_691; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_718 = _T_1318 ? (_GEN_708 ? ~_GEN_317 & _GEN_692 : ~(_T_1334 & _GEN_317) & _GEN_692) : _GEN_692; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_719 = _T_1318 ? (_GEN_708 ? ~_GEN_318 & _GEN_693 : ~(_T_1334 & _GEN_318) & _GEN_693) : _GEN_693; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_720 = _T_1318 ? (_GEN_708 ? ~_GEN_319 & _GEN_694 : ~(_T_1334 & _GEN_319) & _GEN_694) : _GEN_694; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_721 = _T_1318 ? (_GEN_708 ? ~_GEN_320 & _GEN_695 : ~(_T_1334 & _GEN_320) & _GEN_695) : _GEN_695; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_722 = _T_1318 ? (_GEN_708 ? ~_GEN_321 & _GEN_696 : ~(_T_1334 & _GEN_321) & _GEN_696) : _GEN_696; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_723 = _T_1318 ? (_GEN_708 ? ~_GEN_322 & _GEN_697 : ~(_T_1334 & _GEN_322) & _GEN_697) : _GEN_697; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_724 = _T_1318 ? (_GEN_708 ? ~_GEN_323 & _GEN_698 : ~(_T_1334 & _GEN_323) & _GEN_698) : _GEN_698; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_725 = _T_1318 ? (_GEN_708 ? ~_GEN_324 & _GEN_699 : ~(_T_1334 & _GEN_324) & _GEN_699) : _GEN_699; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_726 = _T_1318 ? (_GEN_708 ? ~_GEN_325 & _GEN_700 : ~(_T_1334 & _GEN_325) & _GEN_700) : _GEN_700; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_727 = _T_1318 ? (_GEN_708 ? ~_GEN_326 & _GEN_701 : ~(_T_1334 & _GEN_326) & _GEN_701) : _GEN_701; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_728 = _T_1318 ? (_GEN_708 ? ~_GEN_327 & _GEN_702 : ~(_T_1334 & _GEN_327) & _GEN_702) : _GEN_702; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_729 = _T_1318 ? (_GEN_708 ? ~_GEN_328 & _GEN_703 : ~(_T_1334 & _GEN_328) & _GEN_703) : _GEN_703; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_730 = _T_1318 ? (_GEN_708 ? ~_GEN_329 & _GEN_704 : ~(_T_1334 & _GEN_329) & _GEN_704) : _GEN_704; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_731 = _T_1318 ? (_GEN_708 ? ~_GEN_330 & _GEN_705 : ~(_T_1334 & _GEN_330) & _GEN_705) : _GEN_705; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_732 = _T_1318 ? (_GEN_708 ? ~_GEN_331 & _GEN_706 : ~(_T_1334 & _GEN_331) & _GEN_706) : _GEN_706; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_156 = ~stq_10_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_157 = stq_10_bits_addr_valid & _dword_addr_matches_T_156; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_158 = stq_10_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_160 = _dword_addr_matches_T_158 == _dword_addr_matches_T_159; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_161 = _dword_addr_matches_T_157 & _dword_addr_matches_T_160; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_34_0 = _dword_addr_matches_T_161; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_10; // @[lsu.scala:1665:22] wire _write_mask_mask_T_150 = stq_10_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_151 = stq_10_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_153 = stq_10_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_154 = stq_10_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_157 = stq_10_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_158 = stq_10_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_160 = &stq_10_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16] assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _T_1339 = do_ld_search_0 & stq_10_valid & lcam_st_dep_mask_0[10]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1350 = lcam_mask_0 & write_mask_10; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1347 = _T_1350 == lcam_mask_0 & ~stq_10_bits_uop_is_fence & ~stq_10_bits_uop_is_amo & dword_addr_matches_34_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_10 = _T_1339 & _T_1347; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_54; // @[lsu.scala:1154:56] wire _T_1352 = (|_T_1350) & dword_addr_matches_34_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_55; // @[lsu.scala:1160:56] wire _T_1355 = stq_10_bits_uop_is_fence | stq_10_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_10 = _T_1339 & (_T_1347 | _T_1352 | _T_1355); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_56; // @[lsu.scala:1166:56] wire _GEN_733 = _T_1339 ? (_T_1347 ? io_dmem_s1_kill_0_REG_54 : _T_1352 ? io_dmem_s1_kill_0_REG_55 : _T_1355 ? io_dmem_s1_kill_0_REG_56 : _GEN_707) : _GEN_707; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_734 = _T_1347 | _T_1352; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_735 = _T_1339 ? (_GEN_734 ? ~_searcher_is_older_T_4 & _GEN_709 : ~(_T_1355 & _searcher_is_older_T_4) & _GEN_709) : _GEN_709; // @[util.scala:363:52] wire _GEN_736 = _T_1339 ? (_GEN_734 ? ~_GEN_309 & _GEN_710 : ~(_T_1355 & _GEN_309) & _GEN_710) : _GEN_710; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_737 = _T_1339 ? (_GEN_734 ? ~_GEN_310 & _GEN_711 : ~(_T_1355 & _GEN_310) & _GEN_711) : _GEN_711; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_738 = _T_1339 ? (_GEN_734 ? ~_GEN_311 & _GEN_712 : ~(_T_1355 & _GEN_311) & _GEN_712) : _GEN_712; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_739 = _T_1339 ? (_GEN_734 ? ~_GEN_312 & _GEN_713 : ~(_T_1355 & _GEN_312) & _GEN_713) : _GEN_713; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_740 = _T_1339 ? (_GEN_734 ? ~_GEN_313 & _GEN_714 : ~(_T_1355 & _GEN_313) & _GEN_714) : _GEN_714; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_741 = _T_1339 ? (_GEN_734 ? ~_GEN_314 & _GEN_715 : ~(_T_1355 & _GEN_314) & _GEN_715) : _GEN_715; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_742 = _T_1339 ? (_GEN_734 ? ~_GEN_315 & _GEN_716 : ~(_T_1355 & _GEN_315) & _GEN_716) : _GEN_716; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_743 = _T_1339 ? (_GEN_734 ? ~_GEN_316 & _GEN_717 : ~(_T_1355 & _GEN_316) & _GEN_717) : _GEN_717; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_744 = _T_1339 ? (_GEN_734 ? ~_GEN_317 & _GEN_718 : ~(_T_1355 & _GEN_317) & _GEN_718) : _GEN_718; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_745 = _T_1339 ? (_GEN_734 ? ~_GEN_318 & _GEN_719 : ~(_T_1355 & _GEN_318) & _GEN_719) : _GEN_719; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_746 = _T_1339 ? (_GEN_734 ? ~_GEN_319 & _GEN_720 : ~(_T_1355 & _GEN_319) & _GEN_720) : _GEN_720; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_747 = _T_1339 ? (_GEN_734 ? ~_GEN_320 & _GEN_721 : ~(_T_1355 & _GEN_320) & _GEN_721) : _GEN_721; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_748 = _T_1339 ? (_GEN_734 ? ~_GEN_321 & _GEN_722 : ~(_T_1355 & _GEN_321) & _GEN_722) : _GEN_722; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_749 = _T_1339 ? (_GEN_734 ? ~_GEN_322 & _GEN_723 : ~(_T_1355 & _GEN_322) & _GEN_723) : _GEN_723; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_750 = _T_1339 ? (_GEN_734 ? ~_GEN_323 & _GEN_724 : ~(_T_1355 & _GEN_323) & _GEN_724) : _GEN_724; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_751 = _T_1339 ? (_GEN_734 ? ~_GEN_324 & _GEN_725 : ~(_T_1355 & _GEN_324) & _GEN_725) : _GEN_725; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_752 = _T_1339 ? (_GEN_734 ? ~_GEN_325 & _GEN_726 : ~(_T_1355 & _GEN_325) & _GEN_726) : _GEN_726; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_753 = _T_1339 ? (_GEN_734 ? ~_GEN_326 & _GEN_727 : ~(_T_1355 & _GEN_326) & _GEN_727) : _GEN_727; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_754 = _T_1339 ? (_GEN_734 ? ~_GEN_327 & _GEN_728 : ~(_T_1355 & _GEN_327) & _GEN_728) : _GEN_728; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_755 = _T_1339 ? (_GEN_734 ? ~_GEN_328 & _GEN_729 : ~(_T_1355 & _GEN_328) & _GEN_729) : _GEN_729; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_756 = _T_1339 ? (_GEN_734 ? ~_GEN_329 & _GEN_730 : ~(_T_1355 & _GEN_329) & _GEN_730) : _GEN_730; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_757 = _T_1339 ? (_GEN_734 ? ~_GEN_330 & _GEN_731 : ~(_T_1355 & _GEN_330) & _GEN_731) : _GEN_731; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_758 = _T_1339 ? (_GEN_734 ? ~_GEN_331 & _GEN_732 : ~(_T_1355 & _GEN_331) & _GEN_732) : _GEN_732; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_162 = ~stq_11_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_163 = stq_11_bits_addr_valid & _dword_addr_matches_T_162; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_164 = stq_11_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_166 = _dword_addr_matches_T_164 == _dword_addr_matches_T_165; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_167 = _dword_addr_matches_T_163 & _dword_addr_matches_T_166; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_35_0 = _dword_addr_matches_T_167; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_11; // @[lsu.scala:1665:22] wire _write_mask_mask_T_165 = stq_11_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_166 = stq_11_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_168 = stq_11_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_169 = stq_11_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_172 = stq_11_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_173 = stq_11_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_175 = &stq_11_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16] assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _T_1360 = do_ld_search_0 & stq_11_valid & lcam_st_dep_mask_0[11]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1371 = lcam_mask_0 & write_mask_11; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1368 = _T_1371 == lcam_mask_0 & ~stq_11_bits_uop_is_fence & ~stq_11_bits_uop_is_amo & dword_addr_matches_35_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_11 = _T_1360 & _T_1368; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_57; // @[lsu.scala:1154:56] wire _T_1373 = (|_T_1371) & dword_addr_matches_35_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_58; // @[lsu.scala:1160:56] wire _T_1376 = stq_11_bits_uop_is_fence | stq_11_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_11 = _T_1360 & (_T_1368 | _T_1373 | _T_1376); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_59; // @[lsu.scala:1166:56] wire _GEN_759 = _T_1360 ? (_T_1368 ? io_dmem_s1_kill_0_REG_57 : _T_1373 ? io_dmem_s1_kill_0_REG_58 : _T_1376 ? io_dmem_s1_kill_0_REG_59 : _GEN_733) : _GEN_733; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_760 = _T_1368 | _T_1373; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_761 = _T_1360 ? (_GEN_760 ? ~_searcher_is_older_T_4 & _GEN_735 : ~(_T_1376 & _searcher_is_older_T_4) & _GEN_735) : _GEN_735; // @[util.scala:363:52] wire _GEN_762 = _T_1360 ? (_GEN_760 ? ~_GEN_309 & _GEN_736 : ~(_T_1376 & _GEN_309) & _GEN_736) : _GEN_736; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_763 = _T_1360 ? (_GEN_760 ? ~_GEN_310 & _GEN_737 : ~(_T_1376 & _GEN_310) & _GEN_737) : _GEN_737; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_764 = _T_1360 ? (_GEN_760 ? ~_GEN_311 & _GEN_738 : ~(_T_1376 & _GEN_311) & _GEN_738) : _GEN_738; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_765 = _T_1360 ? (_GEN_760 ? ~_GEN_312 & _GEN_739 : ~(_T_1376 & _GEN_312) & _GEN_739) : _GEN_739; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_766 = _T_1360 ? (_GEN_760 ? ~_GEN_313 & _GEN_740 : ~(_T_1376 & _GEN_313) & _GEN_740) : _GEN_740; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_767 = _T_1360 ? (_GEN_760 ? ~_GEN_314 & _GEN_741 : ~(_T_1376 & _GEN_314) & _GEN_741) : _GEN_741; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_768 = _T_1360 ? (_GEN_760 ? ~_GEN_315 & _GEN_742 : ~(_T_1376 & _GEN_315) & _GEN_742) : _GEN_742; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_769 = _T_1360 ? (_GEN_760 ? ~_GEN_316 & _GEN_743 : ~(_T_1376 & _GEN_316) & _GEN_743) : _GEN_743; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_770 = _T_1360 ? (_GEN_760 ? ~_GEN_317 & _GEN_744 : ~(_T_1376 & _GEN_317) & _GEN_744) : _GEN_744; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_771 = _T_1360 ? (_GEN_760 ? ~_GEN_318 & _GEN_745 : ~(_T_1376 & _GEN_318) & _GEN_745) : _GEN_745; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_772 = _T_1360 ? (_GEN_760 ? ~_GEN_319 & _GEN_746 : ~(_T_1376 & _GEN_319) & _GEN_746) : _GEN_746; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_773 = _T_1360 ? (_GEN_760 ? ~_GEN_320 & _GEN_747 : ~(_T_1376 & _GEN_320) & _GEN_747) : _GEN_747; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_774 = _T_1360 ? (_GEN_760 ? ~_GEN_321 & _GEN_748 : ~(_T_1376 & _GEN_321) & _GEN_748) : _GEN_748; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_775 = _T_1360 ? (_GEN_760 ? ~_GEN_322 & _GEN_749 : ~(_T_1376 & _GEN_322) & _GEN_749) : _GEN_749; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_776 = _T_1360 ? (_GEN_760 ? ~_GEN_323 & _GEN_750 : ~(_T_1376 & _GEN_323) & _GEN_750) : _GEN_750; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_777 = _T_1360 ? (_GEN_760 ? ~_GEN_324 & _GEN_751 : ~(_T_1376 & _GEN_324) & _GEN_751) : _GEN_751; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_778 = _T_1360 ? (_GEN_760 ? ~_GEN_325 & _GEN_752 : ~(_T_1376 & _GEN_325) & _GEN_752) : _GEN_752; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_779 = _T_1360 ? (_GEN_760 ? ~_GEN_326 & _GEN_753 : ~(_T_1376 & _GEN_326) & _GEN_753) : _GEN_753; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_780 = _T_1360 ? (_GEN_760 ? ~_GEN_327 & _GEN_754 : ~(_T_1376 & _GEN_327) & _GEN_754) : _GEN_754; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_781 = _T_1360 ? (_GEN_760 ? ~_GEN_328 & _GEN_755 : ~(_T_1376 & _GEN_328) & _GEN_755) : _GEN_755; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_782 = _T_1360 ? (_GEN_760 ? ~_GEN_329 & _GEN_756 : ~(_T_1376 & _GEN_329) & _GEN_756) : _GEN_756; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_783 = _T_1360 ? (_GEN_760 ? ~_GEN_330 & _GEN_757 : ~(_T_1376 & _GEN_330) & _GEN_757) : _GEN_757; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_784 = _T_1360 ? (_GEN_760 ? ~_GEN_331 & _GEN_758 : ~(_T_1376 & _GEN_331) & _GEN_758) : _GEN_758; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_168 = ~stq_12_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_169 = stq_12_bits_addr_valid & _dword_addr_matches_T_168; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_170 = stq_12_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 == _dword_addr_matches_T_171; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_173 = _dword_addr_matches_T_169 & _dword_addr_matches_T_172; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_36_0 = _dword_addr_matches_T_173; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_12; // @[lsu.scala:1665:22] wire _write_mask_mask_T_180 = stq_12_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_181 = stq_12_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_183 = stq_12_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_184 = stq_12_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_187 = stq_12_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_188 = stq_12_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_190 = &stq_12_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16] assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _T_1381 = do_ld_search_0 & stq_12_valid & lcam_st_dep_mask_0[12]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1392 = lcam_mask_0 & write_mask_12; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1389 = _T_1392 == lcam_mask_0 & ~stq_12_bits_uop_is_fence & ~stq_12_bits_uop_is_amo & dword_addr_matches_36_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_12 = _T_1381 & _T_1389; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_60; // @[lsu.scala:1154:56] wire _T_1394 = (|_T_1392) & dword_addr_matches_36_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_61; // @[lsu.scala:1160:56] wire _T_1397 = stq_12_bits_uop_is_fence | stq_12_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_12 = _T_1381 & (_T_1389 | _T_1394 | _T_1397); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_62; // @[lsu.scala:1166:56] wire _GEN_785 = _T_1381 ? (_T_1389 ? io_dmem_s1_kill_0_REG_60 : _T_1394 ? io_dmem_s1_kill_0_REG_61 : _T_1397 ? io_dmem_s1_kill_0_REG_62 : _GEN_759) : _GEN_759; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_786 = _T_1389 | _T_1394; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_787 = _T_1381 ? (_GEN_786 ? ~_searcher_is_older_T_4 & _GEN_761 : ~(_T_1397 & _searcher_is_older_T_4) & _GEN_761) : _GEN_761; // @[util.scala:363:52] wire _GEN_788 = _T_1381 ? (_GEN_786 ? ~_GEN_309 & _GEN_762 : ~(_T_1397 & _GEN_309) & _GEN_762) : _GEN_762; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_789 = _T_1381 ? (_GEN_786 ? ~_GEN_310 & _GEN_763 : ~(_T_1397 & _GEN_310) & _GEN_763) : _GEN_763; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_790 = _T_1381 ? (_GEN_786 ? ~_GEN_311 & _GEN_764 : ~(_T_1397 & _GEN_311) & _GEN_764) : _GEN_764; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_791 = _T_1381 ? (_GEN_786 ? ~_GEN_312 & _GEN_765 : ~(_T_1397 & _GEN_312) & _GEN_765) : _GEN_765; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_792 = _T_1381 ? (_GEN_786 ? ~_GEN_313 & _GEN_766 : ~(_T_1397 & _GEN_313) & _GEN_766) : _GEN_766; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_793 = _T_1381 ? (_GEN_786 ? ~_GEN_314 & _GEN_767 : ~(_T_1397 & _GEN_314) & _GEN_767) : _GEN_767; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_794 = _T_1381 ? (_GEN_786 ? ~_GEN_315 & _GEN_768 : ~(_T_1397 & _GEN_315) & _GEN_768) : _GEN_768; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_795 = _T_1381 ? (_GEN_786 ? ~_GEN_316 & _GEN_769 : ~(_T_1397 & _GEN_316) & _GEN_769) : _GEN_769; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_796 = _T_1381 ? (_GEN_786 ? ~_GEN_317 & _GEN_770 : ~(_T_1397 & _GEN_317) & _GEN_770) : _GEN_770; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_797 = _T_1381 ? (_GEN_786 ? ~_GEN_318 & _GEN_771 : ~(_T_1397 & _GEN_318) & _GEN_771) : _GEN_771; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_798 = _T_1381 ? (_GEN_786 ? ~_GEN_319 & _GEN_772 : ~(_T_1397 & _GEN_319) & _GEN_772) : _GEN_772; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_799 = _T_1381 ? (_GEN_786 ? ~_GEN_320 & _GEN_773 : ~(_T_1397 & _GEN_320) & _GEN_773) : _GEN_773; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_800 = _T_1381 ? (_GEN_786 ? ~_GEN_321 & _GEN_774 : ~(_T_1397 & _GEN_321) & _GEN_774) : _GEN_774; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_801 = _T_1381 ? (_GEN_786 ? ~_GEN_322 & _GEN_775 : ~(_T_1397 & _GEN_322) & _GEN_775) : _GEN_775; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_802 = _T_1381 ? (_GEN_786 ? ~_GEN_323 & _GEN_776 : ~(_T_1397 & _GEN_323) & _GEN_776) : _GEN_776; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_803 = _T_1381 ? (_GEN_786 ? ~_GEN_324 & _GEN_777 : ~(_T_1397 & _GEN_324) & _GEN_777) : _GEN_777; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_804 = _T_1381 ? (_GEN_786 ? ~_GEN_325 & _GEN_778 : ~(_T_1397 & _GEN_325) & _GEN_778) : _GEN_778; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_805 = _T_1381 ? (_GEN_786 ? ~_GEN_326 & _GEN_779 : ~(_T_1397 & _GEN_326) & _GEN_779) : _GEN_779; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_806 = _T_1381 ? (_GEN_786 ? ~_GEN_327 & _GEN_780 : ~(_T_1397 & _GEN_327) & _GEN_780) : _GEN_780; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_807 = _T_1381 ? (_GEN_786 ? ~_GEN_328 & _GEN_781 : ~(_T_1397 & _GEN_328) & _GEN_781) : _GEN_781; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_808 = _T_1381 ? (_GEN_786 ? ~_GEN_329 & _GEN_782 : ~(_T_1397 & _GEN_329) & _GEN_782) : _GEN_782; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_809 = _T_1381 ? (_GEN_786 ? ~_GEN_330 & _GEN_783 : ~(_T_1397 & _GEN_330) & _GEN_783) : _GEN_783; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_810 = _T_1381 ? (_GEN_786 ? ~_GEN_331 & _GEN_784 : ~(_T_1397 & _GEN_331) & _GEN_784) : _GEN_784; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_174 = ~stq_13_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_175 = stq_13_bits_addr_valid & _dword_addr_matches_T_174; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_176 = stq_13_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_178 = _dword_addr_matches_T_176 == _dword_addr_matches_T_177; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_179 = _dword_addr_matches_T_175 & _dword_addr_matches_T_178; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_37_0 = _dword_addr_matches_T_179; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_13; // @[lsu.scala:1665:22] wire _write_mask_mask_T_195 = stq_13_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_196 = stq_13_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_198 = stq_13_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_199 = stq_13_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_202 = stq_13_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_203 = stq_13_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_205 = &stq_13_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16] assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _T_1402 = do_ld_search_0 & stq_13_valid & lcam_st_dep_mask_0[13]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1413 = lcam_mask_0 & write_mask_13; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1410 = _T_1413 == lcam_mask_0 & ~stq_13_bits_uop_is_fence & ~stq_13_bits_uop_is_amo & dword_addr_matches_37_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_13 = _T_1402 & _T_1410; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_63; // @[lsu.scala:1154:56] wire _T_1415 = (|_T_1413) & dword_addr_matches_37_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_64; // @[lsu.scala:1160:56] wire _T_1418 = stq_13_bits_uop_is_fence | stq_13_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_13 = _T_1402 & (_T_1410 | _T_1415 | _T_1418); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_65; // @[lsu.scala:1166:56] wire _GEN_811 = _T_1402 ? (_T_1410 ? io_dmem_s1_kill_0_REG_63 : _T_1415 ? io_dmem_s1_kill_0_REG_64 : _T_1418 ? io_dmem_s1_kill_0_REG_65 : _GEN_785) : _GEN_785; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_812 = _T_1410 | _T_1415; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_813 = _T_1402 ? (_GEN_812 ? ~_searcher_is_older_T_4 & _GEN_787 : ~(_T_1418 & _searcher_is_older_T_4) & _GEN_787) : _GEN_787; // @[util.scala:363:52] wire _GEN_814 = _T_1402 ? (_GEN_812 ? ~_GEN_309 & _GEN_788 : ~(_T_1418 & _GEN_309) & _GEN_788) : _GEN_788; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_815 = _T_1402 ? (_GEN_812 ? ~_GEN_310 & _GEN_789 : ~(_T_1418 & _GEN_310) & _GEN_789) : _GEN_789; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_816 = _T_1402 ? (_GEN_812 ? ~_GEN_311 & _GEN_790 : ~(_T_1418 & _GEN_311) & _GEN_790) : _GEN_790; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_817 = _T_1402 ? (_GEN_812 ? ~_GEN_312 & _GEN_791 : ~(_T_1418 & _GEN_312) & _GEN_791) : _GEN_791; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_818 = _T_1402 ? (_GEN_812 ? ~_GEN_313 & _GEN_792 : ~(_T_1418 & _GEN_313) & _GEN_792) : _GEN_792; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_819 = _T_1402 ? (_GEN_812 ? ~_GEN_314 & _GEN_793 : ~(_T_1418 & _GEN_314) & _GEN_793) : _GEN_793; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_820 = _T_1402 ? (_GEN_812 ? ~_GEN_315 & _GEN_794 : ~(_T_1418 & _GEN_315) & _GEN_794) : _GEN_794; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_821 = _T_1402 ? (_GEN_812 ? ~_GEN_316 & _GEN_795 : ~(_T_1418 & _GEN_316) & _GEN_795) : _GEN_795; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_822 = _T_1402 ? (_GEN_812 ? ~_GEN_317 & _GEN_796 : ~(_T_1418 & _GEN_317) & _GEN_796) : _GEN_796; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_823 = _T_1402 ? (_GEN_812 ? ~_GEN_318 & _GEN_797 : ~(_T_1418 & _GEN_318) & _GEN_797) : _GEN_797; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_824 = _T_1402 ? (_GEN_812 ? ~_GEN_319 & _GEN_798 : ~(_T_1418 & _GEN_319) & _GEN_798) : _GEN_798; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_825 = _T_1402 ? (_GEN_812 ? ~_GEN_320 & _GEN_799 : ~(_T_1418 & _GEN_320) & _GEN_799) : _GEN_799; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_826 = _T_1402 ? (_GEN_812 ? ~_GEN_321 & _GEN_800 : ~(_T_1418 & _GEN_321) & _GEN_800) : _GEN_800; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_827 = _T_1402 ? (_GEN_812 ? ~_GEN_322 & _GEN_801 : ~(_T_1418 & _GEN_322) & _GEN_801) : _GEN_801; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_828 = _T_1402 ? (_GEN_812 ? ~_GEN_323 & _GEN_802 : ~(_T_1418 & _GEN_323) & _GEN_802) : _GEN_802; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_829 = _T_1402 ? (_GEN_812 ? ~_GEN_324 & _GEN_803 : ~(_T_1418 & _GEN_324) & _GEN_803) : _GEN_803; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_830 = _T_1402 ? (_GEN_812 ? ~_GEN_325 & _GEN_804 : ~(_T_1418 & _GEN_325) & _GEN_804) : _GEN_804; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_831 = _T_1402 ? (_GEN_812 ? ~_GEN_326 & _GEN_805 : ~(_T_1418 & _GEN_326) & _GEN_805) : _GEN_805; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_832 = _T_1402 ? (_GEN_812 ? ~_GEN_327 & _GEN_806 : ~(_T_1418 & _GEN_327) & _GEN_806) : _GEN_806; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_833 = _T_1402 ? (_GEN_812 ? ~_GEN_328 & _GEN_807 : ~(_T_1418 & _GEN_328) & _GEN_807) : _GEN_807; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_834 = _T_1402 ? (_GEN_812 ? ~_GEN_329 & _GEN_808 : ~(_T_1418 & _GEN_329) & _GEN_808) : _GEN_808; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_835 = _T_1402 ? (_GEN_812 ? ~_GEN_330 & _GEN_809 : ~(_T_1418 & _GEN_330) & _GEN_809) : _GEN_809; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_836 = _T_1402 ? (_GEN_812 ? ~_GEN_331 & _GEN_810 : ~(_T_1418 & _GEN_331) & _GEN_810) : _GEN_810; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_180 = ~stq_14_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_181 = stq_14_bits_addr_valid & _dword_addr_matches_T_180; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_182 = stq_14_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_184 = _dword_addr_matches_T_182 == _dword_addr_matches_T_183; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_185 = _dword_addr_matches_T_181 & _dword_addr_matches_T_184; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_38_0 = _dword_addr_matches_T_185; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_14; // @[lsu.scala:1665:22] wire _write_mask_mask_T_210 = stq_14_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_211 = stq_14_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_213 = stq_14_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_214 = stq_14_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_217 = stq_14_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_218 = stq_14_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_220 = &stq_14_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16] assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _T_1423 = do_ld_search_0 & stq_14_valid & lcam_st_dep_mask_0[14]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1434 = lcam_mask_0 & write_mask_14; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1431 = _T_1434 == lcam_mask_0 & ~stq_14_bits_uop_is_fence & ~stq_14_bits_uop_is_amo & dword_addr_matches_38_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_14 = _T_1423 & _T_1431; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_66; // @[lsu.scala:1154:56] wire _T_1436 = (|_T_1434) & dword_addr_matches_38_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_67; // @[lsu.scala:1160:56] wire _T_1439 = stq_14_bits_uop_is_fence | stq_14_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_14 = _T_1423 & (_T_1431 | _T_1436 | _T_1439); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_68; // @[lsu.scala:1166:56] wire _GEN_837 = _T_1423 ? (_T_1431 ? io_dmem_s1_kill_0_REG_66 : _T_1436 ? io_dmem_s1_kill_0_REG_67 : _T_1439 ? io_dmem_s1_kill_0_REG_68 : _GEN_811) : _GEN_811; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_838 = _T_1431 | _T_1436; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_839 = _T_1423 ? (_GEN_838 ? ~_searcher_is_older_T_4 & _GEN_813 : ~(_T_1439 & _searcher_is_older_T_4) & _GEN_813) : _GEN_813; // @[util.scala:363:52] wire _GEN_840 = _T_1423 ? (_GEN_838 ? ~_GEN_309 & _GEN_814 : ~(_T_1439 & _GEN_309) & _GEN_814) : _GEN_814; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_841 = _T_1423 ? (_GEN_838 ? ~_GEN_310 & _GEN_815 : ~(_T_1439 & _GEN_310) & _GEN_815) : _GEN_815; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_842 = _T_1423 ? (_GEN_838 ? ~_GEN_311 & _GEN_816 : ~(_T_1439 & _GEN_311) & _GEN_816) : _GEN_816; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_843 = _T_1423 ? (_GEN_838 ? ~_GEN_312 & _GEN_817 : ~(_T_1439 & _GEN_312) & _GEN_817) : _GEN_817; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_844 = _T_1423 ? (_GEN_838 ? ~_GEN_313 & _GEN_818 : ~(_T_1439 & _GEN_313) & _GEN_818) : _GEN_818; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_845 = _T_1423 ? (_GEN_838 ? ~_GEN_314 & _GEN_819 : ~(_T_1439 & _GEN_314) & _GEN_819) : _GEN_819; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_846 = _T_1423 ? (_GEN_838 ? ~_GEN_315 & _GEN_820 : ~(_T_1439 & _GEN_315) & _GEN_820) : _GEN_820; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_847 = _T_1423 ? (_GEN_838 ? ~_GEN_316 & _GEN_821 : ~(_T_1439 & _GEN_316) & _GEN_821) : _GEN_821; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_848 = _T_1423 ? (_GEN_838 ? ~_GEN_317 & _GEN_822 : ~(_T_1439 & _GEN_317) & _GEN_822) : _GEN_822; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_849 = _T_1423 ? (_GEN_838 ? ~_GEN_318 & _GEN_823 : ~(_T_1439 & _GEN_318) & _GEN_823) : _GEN_823; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_850 = _T_1423 ? (_GEN_838 ? ~_GEN_319 & _GEN_824 : ~(_T_1439 & _GEN_319) & _GEN_824) : _GEN_824; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_851 = _T_1423 ? (_GEN_838 ? ~_GEN_320 & _GEN_825 : ~(_T_1439 & _GEN_320) & _GEN_825) : _GEN_825; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_852 = _T_1423 ? (_GEN_838 ? ~_GEN_321 & _GEN_826 : ~(_T_1439 & _GEN_321) & _GEN_826) : _GEN_826; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_853 = _T_1423 ? (_GEN_838 ? ~_GEN_322 & _GEN_827 : ~(_T_1439 & _GEN_322) & _GEN_827) : _GEN_827; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_854 = _T_1423 ? (_GEN_838 ? ~_GEN_323 & _GEN_828 : ~(_T_1439 & _GEN_323) & _GEN_828) : _GEN_828; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_855 = _T_1423 ? (_GEN_838 ? ~_GEN_324 & _GEN_829 : ~(_T_1439 & _GEN_324) & _GEN_829) : _GEN_829; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_856 = _T_1423 ? (_GEN_838 ? ~_GEN_325 & _GEN_830 : ~(_T_1439 & _GEN_325) & _GEN_830) : _GEN_830; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_857 = _T_1423 ? (_GEN_838 ? ~_GEN_326 & _GEN_831 : ~(_T_1439 & _GEN_326) & _GEN_831) : _GEN_831; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_858 = _T_1423 ? (_GEN_838 ? ~_GEN_327 & _GEN_832 : ~(_T_1439 & _GEN_327) & _GEN_832) : _GEN_832; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_859 = _T_1423 ? (_GEN_838 ? ~_GEN_328 & _GEN_833 : ~(_T_1439 & _GEN_328) & _GEN_833) : _GEN_833; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_860 = _T_1423 ? (_GEN_838 ? ~_GEN_329 & _GEN_834 : ~(_T_1439 & _GEN_329) & _GEN_834) : _GEN_834; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_861 = _T_1423 ? (_GEN_838 ? ~_GEN_330 & _GEN_835 : ~(_T_1439 & _GEN_330) & _GEN_835) : _GEN_835; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_862 = _T_1423 ? (_GEN_838 ? ~_GEN_331 & _GEN_836 : ~(_T_1439 & _GEN_331) & _GEN_836) : _GEN_836; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_186 = ~stq_15_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_187 = stq_15_bits_addr_valid & _dword_addr_matches_T_186; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_188 = stq_15_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_190 = _dword_addr_matches_T_188 == _dword_addr_matches_T_189; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_191 = _dword_addr_matches_T_187 & _dword_addr_matches_T_190; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_39_0 = _dword_addr_matches_T_191; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_15; // @[lsu.scala:1665:22] wire _write_mask_mask_T_225 = stq_15_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_226 = stq_15_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_228 = stq_15_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_229 = stq_15_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_232 = stq_15_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_233 = stq_15_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_235 = &stq_15_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16] assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _T_1444 = do_ld_search_0 & stq_15_valid & lcam_st_dep_mask_0[15]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1455 = lcam_mask_0 & write_mask_15; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1452 = _T_1455 == lcam_mask_0 & ~stq_15_bits_uop_is_fence & ~stq_15_bits_uop_is_amo & dword_addr_matches_39_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_15 = _T_1444 & _T_1452; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_69; // @[lsu.scala:1154:56] wire _T_1457 = (|_T_1455) & dword_addr_matches_39_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_70; // @[lsu.scala:1160:56] wire _T_1460 = stq_15_bits_uop_is_fence | stq_15_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_15 = _T_1444 & (_T_1452 | _T_1457 | _T_1460); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_71; // @[lsu.scala:1166:56] wire _GEN_863 = _T_1444 ? (_T_1452 ? io_dmem_s1_kill_0_REG_69 : _T_1457 ? io_dmem_s1_kill_0_REG_70 : _T_1460 ? io_dmem_s1_kill_0_REG_71 : _GEN_837) : _GEN_837; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_864 = _T_1452 | _T_1457; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_865 = _T_1444 ? (_GEN_864 ? ~_searcher_is_older_T_4 & _GEN_839 : ~(_T_1460 & _searcher_is_older_T_4) & _GEN_839) : _GEN_839; // @[util.scala:363:52] wire _GEN_866 = _T_1444 ? (_GEN_864 ? ~_GEN_309 & _GEN_840 : ~(_T_1460 & _GEN_309) & _GEN_840) : _GEN_840; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_867 = _T_1444 ? (_GEN_864 ? ~_GEN_310 & _GEN_841 : ~(_T_1460 & _GEN_310) & _GEN_841) : _GEN_841; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_868 = _T_1444 ? (_GEN_864 ? ~_GEN_311 & _GEN_842 : ~(_T_1460 & _GEN_311) & _GEN_842) : _GEN_842; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_869 = _T_1444 ? (_GEN_864 ? ~_GEN_312 & _GEN_843 : ~(_T_1460 & _GEN_312) & _GEN_843) : _GEN_843; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_870 = _T_1444 ? (_GEN_864 ? ~_GEN_313 & _GEN_844 : ~(_T_1460 & _GEN_313) & _GEN_844) : _GEN_844; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_871 = _T_1444 ? (_GEN_864 ? ~_GEN_314 & _GEN_845 : ~(_T_1460 & _GEN_314) & _GEN_845) : _GEN_845; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_872 = _T_1444 ? (_GEN_864 ? ~_GEN_315 & _GEN_846 : ~(_T_1460 & _GEN_315) & _GEN_846) : _GEN_846; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_873 = _T_1444 ? (_GEN_864 ? ~_GEN_316 & _GEN_847 : ~(_T_1460 & _GEN_316) & _GEN_847) : _GEN_847; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_874 = _T_1444 ? (_GEN_864 ? ~_GEN_317 & _GEN_848 : ~(_T_1460 & _GEN_317) & _GEN_848) : _GEN_848; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_875 = _T_1444 ? (_GEN_864 ? ~_GEN_318 & _GEN_849 : ~(_T_1460 & _GEN_318) & _GEN_849) : _GEN_849; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_876 = _T_1444 ? (_GEN_864 ? ~_GEN_319 & _GEN_850 : ~(_T_1460 & _GEN_319) & _GEN_850) : _GEN_850; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_877 = _T_1444 ? (_GEN_864 ? ~_GEN_320 & _GEN_851 : ~(_T_1460 & _GEN_320) & _GEN_851) : _GEN_851; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_878 = _T_1444 ? (_GEN_864 ? ~_GEN_321 & _GEN_852 : ~(_T_1460 & _GEN_321) & _GEN_852) : _GEN_852; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_879 = _T_1444 ? (_GEN_864 ? ~_GEN_322 & _GEN_853 : ~(_T_1460 & _GEN_322) & _GEN_853) : _GEN_853; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_880 = _T_1444 ? (_GEN_864 ? ~_GEN_323 & _GEN_854 : ~(_T_1460 & _GEN_323) & _GEN_854) : _GEN_854; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_881 = _T_1444 ? (_GEN_864 ? ~_GEN_324 & _GEN_855 : ~(_T_1460 & _GEN_324) & _GEN_855) : _GEN_855; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_882 = _T_1444 ? (_GEN_864 ? ~_GEN_325 & _GEN_856 : ~(_T_1460 & _GEN_325) & _GEN_856) : _GEN_856; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_883 = _T_1444 ? (_GEN_864 ? ~_GEN_326 & _GEN_857 : ~(_T_1460 & _GEN_326) & _GEN_857) : _GEN_857; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_884 = _T_1444 ? (_GEN_864 ? ~_GEN_327 & _GEN_858 : ~(_T_1460 & _GEN_327) & _GEN_858) : _GEN_858; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_885 = _T_1444 ? (_GEN_864 ? ~_GEN_328 & _GEN_859 : ~(_T_1460 & _GEN_328) & _GEN_859) : _GEN_859; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_886 = _T_1444 ? (_GEN_864 ? ~_GEN_329 & _GEN_860 : ~(_T_1460 & _GEN_329) & _GEN_860) : _GEN_860; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_887 = _T_1444 ? (_GEN_864 ? ~_GEN_330 & _GEN_861 : ~(_T_1460 & _GEN_330) & _GEN_861) : _GEN_861; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_888 = _T_1444 ? (_GEN_864 ? ~_GEN_331 & _GEN_862 : ~(_T_1460 & _GEN_331) & _GEN_862) : _GEN_862; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_192 = ~stq_16_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_193 = stq_16_bits_addr_valid & _dword_addr_matches_T_192; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_194 = stq_16_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_196 = _dword_addr_matches_T_194 == _dword_addr_matches_T_195; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_197 = _dword_addr_matches_T_193 & _dword_addr_matches_T_196; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_40_0 = _dword_addr_matches_T_197; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_16; // @[lsu.scala:1665:22] wire _write_mask_mask_T_240 = stq_16_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_241 = stq_16_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_242 = 15'h1 << _write_mask_mask_T_241; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_243 = stq_16_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_244 = stq_16_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_245 = {_write_mask_mask_T_244, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_246 = 15'h3 << _write_mask_mask_T_245; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_247 = stq_16_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_248 = stq_16_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_249 = _write_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_250 = &stq_16_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_252 = _write_mask_mask_T_247 ? _write_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_253 = _write_mask_mask_T_243 ? _write_mask_mask_T_246 : {7'h0, _write_mask_mask_T_252}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_254 = _write_mask_mask_T_240 ? _write_mask_mask_T_242 : _write_mask_mask_T_253; // @[Mux.scala:126:16] assign write_mask_16 = _write_mask_mask_T_254[7:0]; // @[Mux.scala:126:16] wire _T_1465 = do_ld_search_0 & stq_16_valid & lcam_st_dep_mask_0[16]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1476 = lcam_mask_0 & write_mask_16; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1473 = _T_1476 == lcam_mask_0 & ~stq_16_bits_uop_is_fence & ~stq_16_bits_uop_is_amo & dword_addr_matches_40_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_16 = _T_1465 & _T_1473; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_72; // @[lsu.scala:1154:56] wire _T_1478 = (|_T_1476) & dword_addr_matches_40_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_73; // @[lsu.scala:1160:56] wire _T_1481 = stq_16_bits_uop_is_fence | stq_16_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_16 = _T_1465 & (_T_1473 | _T_1478 | _T_1481); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_74; // @[lsu.scala:1166:56] wire _GEN_889 = _T_1465 ? (_T_1473 ? io_dmem_s1_kill_0_REG_72 : _T_1478 ? io_dmem_s1_kill_0_REG_73 : _T_1481 ? io_dmem_s1_kill_0_REG_74 : _GEN_863) : _GEN_863; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_890 = _T_1473 | _T_1478; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_891 = _T_1465 ? (_GEN_890 ? ~_searcher_is_older_T_4 & _GEN_865 : ~(_T_1481 & _searcher_is_older_T_4) & _GEN_865) : _GEN_865; // @[util.scala:363:52] wire _GEN_892 = _T_1465 ? (_GEN_890 ? ~_GEN_309 & _GEN_866 : ~(_T_1481 & _GEN_309) & _GEN_866) : _GEN_866; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_893 = _T_1465 ? (_GEN_890 ? ~_GEN_310 & _GEN_867 : ~(_T_1481 & _GEN_310) & _GEN_867) : _GEN_867; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_894 = _T_1465 ? (_GEN_890 ? ~_GEN_311 & _GEN_868 : ~(_T_1481 & _GEN_311) & _GEN_868) : _GEN_868; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_895 = _T_1465 ? (_GEN_890 ? ~_GEN_312 & _GEN_869 : ~(_T_1481 & _GEN_312) & _GEN_869) : _GEN_869; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_896 = _T_1465 ? (_GEN_890 ? ~_GEN_313 & _GEN_870 : ~(_T_1481 & _GEN_313) & _GEN_870) : _GEN_870; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_897 = _T_1465 ? (_GEN_890 ? ~_GEN_314 & _GEN_871 : ~(_T_1481 & _GEN_314) & _GEN_871) : _GEN_871; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_898 = _T_1465 ? (_GEN_890 ? ~_GEN_315 & _GEN_872 : ~(_T_1481 & _GEN_315) & _GEN_872) : _GEN_872; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_899 = _T_1465 ? (_GEN_890 ? ~_GEN_316 & _GEN_873 : ~(_T_1481 & _GEN_316) & _GEN_873) : _GEN_873; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_900 = _T_1465 ? (_GEN_890 ? ~_GEN_317 & _GEN_874 : ~(_T_1481 & _GEN_317) & _GEN_874) : _GEN_874; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_901 = _T_1465 ? (_GEN_890 ? ~_GEN_318 & _GEN_875 : ~(_T_1481 & _GEN_318) & _GEN_875) : _GEN_875; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_902 = _T_1465 ? (_GEN_890 ? ~_GEN_319 & _GEN_876 : ~(_T_1481 & _GEN_319) & _GEN_876) : _GEN_876; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_903 = _T_1465 ? (_GEN_890 ? ~_GEN_320 & _GEN_877 : ~(_T_1481 & _GEN_320) & _GEN_877) : _GEN_877; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_904 = _T_1465 ? (_GEN_890 ? ~_GEN_321 & _GEN_878 : ~(_T_1481 & _GEN_321) & _GEN_878) : _GEN_878; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_905 = _T_1465 ? (_GEN_890 ? ~_GEN_322 & _GEN_879 : ~(_T_1481 & _GEN_322) & _GEN_879) : _GEN_879; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_906 = _T_1465 ? (_GEN_890 ? ~_GEN_323 & _GEN_880 : ~(_T_1481 & _GEN_323) & _GEN_880) : _GEN_880; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_907 = _T_1465 ? (_GEN_890 ? ~_GEN_324 & _GEN_881 : ~(_T_1481 & _GEN_324) & _GEN_881) : _GEN_881; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_908 = _T_1465 ? (_GEN_890 ? ~_GEN_325 & _GEN_882 : ~(_T_1481 & _GEN_325) & _GEN_882) : _GEN_882; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_909 = _T_1465 ? (_GEN_890 ? ~_GEN_326 & _GEN_883 : ~(_T_1481 & _GEN_326) & _GEN_883) : _GEN_883; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_910 = _T_1465 ? (_GEN_890 ? ~_GEN_327 & _GEN_884 : ~(_T_1481 & _GEN_327) & _GEN_884) : _GEN_884; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_911 = _T_1465 ? (_GEN_890 ? ~_GEN_328 & _GEN_885 : ~(_T_1481 & _GEN_328) & _GEN_885) : _GEN_885; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_912 = _T_1465 ? (_GEN_890 ? ~_GEN_329 & _GEN_886 : ~(_T_1481 & _GEN_329) & _GEN_886) : _GEN_886; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_913 = _T_1465 ? (_GEN_890 ? ~_GEN_330 & _GEN_887 : ~(_T_1481 & _GEN_330) & _GEN_887) : _GEN_887; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_914 = _T_1465 ? (_GEN_890 ? ~_GEN_331 & _GEN_888 : ~(_T_1481 & _GEN_331) & _GEN_888) : _GEN_888; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_198 = ~stq_17_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_199 = stq_17_bits_addr_valid & _dword_addr_matches_T_198; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_200 = stq_17_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_202 = _dword_addr_matches_T_200 == _dword_addr_matches_T_201; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_203 = _dword_addr_matches_T_199 & _dword_addr_matches_T_202; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_41_0 = _dword_addr_matches_T_203; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_17; // @[lsu.scala:1665:22] wire _write_mask_mask_T_255 = stq_17_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_256 = stq_17_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_257 = 15'h1 << _write_mask_mask_T_256; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_258 = stq_17_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_259 = stq_17_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_260 = {_write_mask_mask_T_259, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_261 = 15'h3 << _write_mask_mask_T_260; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_262 = stq_17_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_263 = stq_17_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_264 = _write_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_265 = &stq_17_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_267 = _write_mask_mask_T_262 ? _write_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_268 = _write_mask_mask_T_258 ? _write_mask_mask_T_261 : {7'h0, _write_mask_mask_T_267}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_269 = _write_mask_mask_T_255 ? _write_mask_mask_T_257 : _write_mask_mask_T_268; // @[Mux.scala:126:16] assign write_mask_17 = _write_mask_mask_T_269[7:0]; // @[Mux.scala:126:16] wire _T_1486 = do_ld_search_0 & stq_17_valid & lcam_st_dep_mask_0[17]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1497 = lcam_mask_0 & write_mask_17; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1494 = _T_1497 == lcam_mask_0 & ~stq_17_bits_uop_is_fence & ~stq_17_bits_uop_is_amo & dword_addr_matches_41_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_17 = _T_1486 & _T_1494; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_75; // @[lsu.scala:1154:56] wire _T_1499 = (|_T_1497) & dword_addr_matches_41_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_76; // @[lsu.scala:1160:56] wire _T_1502 = stq_17_bits_uop_is_fence | stq_17_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_17 = _T_1486 & (_T_1494 | _T_1499 | _T_1502); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_77; // @[lsu.scala:1166:56] wire _GEN_915 = _T_1486 ? (_T_1494 ? io_dmem_s1_kill_0_REG_75 : _T_1499 ? io_dmem_s1_kill_0_REG_76 : _T_1502 ? io_dmem_s1_kill_0_REG_77 : _GEN_889) : _GEN_889; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_916 = _T_1494 | _T_1499; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_917 = _T_1486 ? (_GEN_916 ? ~_searcher_is_older_T_4 & _GEN_891 : ~(_T_1502 & _searcher_is_older_T_4) & _GEN_891) : _GEN_891; // @[util.scala:363:52] wire _GEN_918 = _T_1486 ? (_GEN_916 ? ~_GEN_309 & _GEN_892 : ~(_T_1502 & _GEN_309) & _GEN_892) : _GEN_892; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_919 = _T_1486 ? (_GEN_916 ? ~_GEN_310 & _GEN_893 : ~(_T_1502 & _GEN_310) & _GEN_893) : _GEN_893; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_920 = _T_1486 ? (_GEN_916 ? ~_GEN_311 & _GEN_894 : ~(_T_1502 & _GEN_311) & _GEN_894) : _GEN_894; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_921 = _T_1486 ? (_GEN_916 ? ~_GEN_312 & _GEN_895 : ~(_T_1502 & _GEN_312) & _GEN_895) : _GEN_895; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_922 = _T_1486 ? (_GEN_916 ? ~_GEN_313 & _GEN_896 : ~(_T_1502 & _GEN_313) & _GEN_896) : _GEN_896; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_923 = _T_1486 ? (_GEN_916 ? ~_GEN_314 & _GEN_897 : ~(_T_1502 & _GEN_314) & _GEN_897) : _GEN_897; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_924 = _T_1486 ? (_GEN_916 ? ~_GEN_315 & _GEN_898 : ~(_T_1502 & _GEN_315) & _GEN_898) : _GEN_898; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_925 = _T_1486 ? (_GEN_916 ? ~_GEN_316 & _GEN_899 : ~(_T_1502 & _GEN_316) & _GEN_899) : _GEN_899; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_926 = _T_1486 ? (_GEN_916 ? ~_GEN_317 & _GEN_900 : ~(_T_1502 & _GEN_317) & _GEN_900) : _GEN_900; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_927 = _T_1486 ? (_GEN_916 ? ~_GEN_318 & _GEN_901 : ~(_T_1502 & _GEN_318) & _GEN_901) : _GEN_901; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_928 = _T_1486 ? (_GEN_916 ? ~_GEN_319 & _GEN_902 : ~(_T_1502 & _GEN_319) & _GEN_902) : _GEN_902; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_929 = _T_1486 ? (_GEN_916 ? ~_GEN_320 & _GEN_903 : ~(_T_1502 & _GEN_320) & _GEN_903) : _GEN_903; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_930 = _T_1486 ? (_GEN_916 ? ~_GEN_321 & _GEN_904 : ~(_T_1502 & _GEN_321) & _GEN_904) : _GEN_904; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_931 = _T_1486 ? (_GEN_916 ? ~_GEN_322 & _GEN_905 : ~(_T_1502 & _GEN_322) & _GEN_905) : _GEN_905; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_932 = _T_1486 ? (_GEN_916 ? ~_GEN_323 & _GEN_906 : ~(_T_1502 & _GEN_323) & _GEN_906) : _GEN_906; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_933 = _T_1486 ? (_GEN_916 ? ~_GEN_324 & _GEN_907 : ~(_T_1502 & _GEN_324) & _GEN_907) : _GEN_907; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_934 = _T_1486 ? (_GEN_916 ? ~_GEN_325 & _GEN_908 : ~(_T_1502 & _GEN_325) & _GEN_908) : _GEN_908; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_935 = _T_1486 ? (_GEN_916 ? ~_GEN_326 & _GEN_909 : ~(_T_1502 & _GEN_326) & _GEN_909) : _GEN_909; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_936 = _T_1486 ? (_GEN_916 ? ~_GEN_327 & _GEN_910 : ~(_T_1502 & _GEN_327) & _GEN_910) : _GEN_910; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_937 = _T_1486 ? (_GEN_916 ? ~_GEN_328 & _GEN_911 : ~(_T_1502 & _GEN_328) & _GEN_911) : _GEN_911; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_938 = _T_1486 ? (_GEN_916 ? ~_GEN_329 & _GEN_912 : ~(_T_1502 & _GEN_329) & _GEN_912) : _GEN_912; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_939 = _T_1486 ? (_GEN_916 ? ~_GEN_330 & _GEN_913 : ~(_T_1502 & _GEN_330) & _GEN_913) : _GEN_913; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_940 = _T_1486 ? (_GEN_916 ? ~_GEN_331 & _GEN_914 : ~(_T_1502 & _GEN_331) & _GEN_914) : _GEN_914; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_204 = ~stq_18_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_205 = stq_18_bits_addr_valid & _dword_addr_matches_T_204; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_206 = stq_18_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_208 = _dword_addr_matches_T_206 == _dword_addr_matches_T_207; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_209 = _dword_addr_matches_T_205 & _dword_addr_matches_T_208; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_42_0 = _dword_addr_matches_T_209; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_18; // @[lsu.scala:1665:22] wire _write_mask_mask_T_270 = stq_18_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_271 = stq_18_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_272 = 15'h1 << _write_mask_mask_T_271; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_273 = stq_18_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_274 = stq_18_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_275 = {_write_mask_mask_T_274, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_276 = 15'h3 << _write_mask_mask_T_275; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_277 = stq_18_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_278 = stq_18_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_279 = _write_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_280 = &stq_18_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_282 = _write_mask_mask_T_277 ? _write_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_283 = _write_mask_mask_T_273 ? _write_mask_mask_T_276 : {7'h0, _write_mask_mask_T_282}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_284 = _write_mask_mask_T_270 ? _write_mask_mask_T_272 : _write_mask_mask_T_283; // @[Mux.scala:126:16] assign write_mask_18 = _write_mask_mask_T_284[7:0]; // @[Mux.scala:126:16] wire _T_1507 = do_ld_search_0 & stq_18_valid & lcam_st_dep_mask_0[18]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1518 = lcam_mask_0 & write_mask_18; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1515 = _T_1518 == lcam_mask_0 & ~stq_18_bits_uop_is_fence & ~stq_18_bits_uop_is_amo & dword_addr_matches_42_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_18 = _T_1507 & _T_1515; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_78; // @[lsu.scala:1154:56] wire _T_1520 = (|_T_1518) & dword_addr_matches_42_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_79; // @[lsu.scala:1160:56] wire _T_1523 = stq_18_bits_uop_is_fence | stq_18_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_18 = _T_1507 & (_T_1515 | _T_1520 | _T_1523); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_80; // @[lsu.scala:1166:56] wire _GEN_941 = _T_1507 ? (_T_1515 ? io_dmem_s1_kill_0_REG_78 : _T_1520 ? io_dmem_s1_kill_0_REG_79 : _T_1523 ? io_dmem_s1_kill_0_REG_80 : _GEN_915) : _GEN_915; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_942 = _T_1515 | _T_1520; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_943 = _T_1507 ? (_GEN_942 ? ~_searcher_is_older_T_4 & _GEN_917 : ~(_T_1523 & _searcher_is_older_T_4) & _GEN_917) : _GEN_917; // @[util.scala:363:52] wire _GEN_944 = _T_1507 ? (_GEN_942 ? ~_GEN_309 & _GEN_918 : ~(_T_1523 & _GEN_309) & _GEN_918) : _GEN_918; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_945 = _T_1507 ? (_GEN_942 ? ~_GEN_310 & _GEN_919 : ~(_T_1523 & _GEN_310) & _GEN_919) : _GEN_919; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_946 = _T_1507 ? (_GEN_942 ? ~_GEN_311 & _GEN_920 : ~(_T_1523 & _GEN_311) & _GEN_920) : _GEN_920; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_947 = _T_1507 ? (_GEN_942 ? ~_GEN_312 & _GEN_921 : ~(_T_1523 & _GEN_312) & _GEN_921) : _GEN_921; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_948 = _T_1507 ? (_GEN_942 ? ~_GEN_313 & _GEN_922 : ~(_T_1523 & _GEN_313) & _GEN_922) : _GEN_922; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_949 = _T_1507 ? (_GEN_942 ? ~_GEN_314 & _GEN_923 : ~(_T_1523 & _GEN_314) & _GEN_923) : _GEN_923; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_950 = _T_1507 ? (_GEN_942 ? ~_GEN_315 & _GEN_924 : ~(_T_1523 & _GEN_315) & _GEN_924) : _GEN_924; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_951 = _T_1507 ? (_GEN_942 ? ~_GEN_316 & _GEN_925 : ~(_T_1523 & _GEN_316) & _GEN_925) : _GEN_925; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_952 = _T_1507 ? (_GEN_942 ? ~_GEN_317 & _GEN_926 : ~(_T_1523 & _GEN_317) & _GEN_926) : _GEN_926; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_953 = _T_1507 ? (_GEN_942 ? ~_GEN_318 & _GEN_927 : ~(_T_1523 & _GEN_318) & _GEN_927) : _GEN_927; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_954 = _T_1507 ? (_GEN_942 ? ~_GEN_319 & _GEN_928 : ~(_T_1523 & _GEN_319) & _GEN_928) : _GEN_928; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_955 = _T_1507 ? (_GEN_942 ? ~_GEN_320 & _GEN_929 : ~(_T_1523 & _GEN_320) & _GEN_929) : _GEN_929; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_956 = _T_1507 ? (_GEN_942 ? ~_GEN_321 & _GEN_930 : ~(_T_1523 & _GEN_321) & _GEN_930) : _GEN_930; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_957 = _T_1507 ? (_GEN_942 ? ~_GEN_322 & _GEN_931 : ~(_T_1523 & _GEN_322) & _GEN_931) : _GEN_931; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_958 = _T_1507 ? (_GEN_942 ? ~_GEN_323 & _GEN_932 : ~(_T_1523 & _GEN_323) & _GEN_932) : _GEN_932; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_959 = _T_1507 ? (_GEN_942 ? ~_GEN_324 & _GEN_933 : ~(_T_1523 & _GEN_324) & _GEN_933) : _GEN_933; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_960 = _T_1507 ? (_GEN_942 ? ~_GEN_325 & _GEN_934 : ~(_T_1523 & _GEN_325) & _GEN_934) : _GEN_934; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_961 = _T_1507 ? (_GEN_942 ? ~_GEN_326 & _GEN_935 : ~(_T_1523 & _GEN_326) & _GEN_935) : _GEN_935; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_962 = _T_1507 ? (_GEN_942 ? ~_GEN_327 & _GEN_936 : ~(_T_1523 & _GEN_327) & _GEN_936) : _GEN_936; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_963 = _T_1507 ? (_GEN_942 ? ~_GEN_328 & _GEN_937 : ~(_T_1523 & _GEN_328) & _GEN_937) : _GEN_937; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_964 = _T_1507 ? (_GEN_942 ? ~_GEN_329 & _GEN_938 : ~(_T_1523 & _GEN_329) & _GEN_938) : _GEN_938; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_965 = _T_1507 ? (_GEN_942 ? ~_GEN_330 & _GEN_939 : ~(_T_1523 & _GEN_330) & _GEN_939) : _GEN_939; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_966 = _T_1507 ? (_GEN_942 ? ~_GEN_331 & _GEN_940 : ~(_T_1523 & _GEN_331) & _GEN_940) : _GEN_940; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_210 = ~stq_19_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_211 = stq_19_bits_addr_valid & _dword_addr_matches_T_210; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_212 = stq_19_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_214 = _dword_addr_matches_T_212 == _dword_addr_matches_T_213; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_215 = _dword_addr_matches_T_211 & _dword_addr_matches_T_214; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_43_0 = _dword_addr_matches_T_215; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_19; // @[lsu.scala:1665:22] wire _write_mask_mask_T_285 = stq_19_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_286 = stq_19_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_287 = 15'h1 << _write_mask_mask_T_286; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_288 = stq_19_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_289 = stq_19_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_290 = {_write_mask_mask_T_289, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_291 = 15'h3 << _write_mask_mask_T_290; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_292 = stq_19_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_293 = stq_19_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_294 = _write_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_295 = &stq_19_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_297 = _write_mask_mask_T_292 ? _write_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_298 = _write_mask_mask_T_288 ? _write_mask_mask_T_291 : {7'h0, _write_mask_mask_T_297}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_299 = _write_mask_mask_T_285 ? _write_mask_mask_T_287 : _write_mask_mask_T_298; // @[Mux.scala:126:16] assign write_mask_19 = _write_mask_mask_T_299[7:0]; // @[Mux.scala:126:16] wire _T_1528 = do_ld_search_0 & stq_19_valid & lcam_st_dep_mask_0[19]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1539 = lcam_mask_0 & write_mask_19; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1536 = _T_1539 == lcam_mask_0 & ~stq_19_bits_uop_is_fence & ~stq_19_bits_uop_is_amo & dword_addr_matches_43_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_19 = _T_1528 & _T_1536; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_81; // @[lsu.scala:1154:56] wire _T_1541 = (|_T_1539) & dword_addr_matches_43_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_82; // @[lsu.scala:1160:56] wire _T_1544 = stq_19_bits_uop_is_fence | stq_19_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_19 = _T_1528 & (_T_1536 | _T_1541 | _T_1544); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_83; // @[lsu.scala:1166:56] wire _GEN_967 = _T_1528 ? (_T_1536 ? io_dmem_s1_kill_0_REG_81 : _T_1541 ? io_dmem_s1_kill_0_REG_82 : _T_1544 ? io_dmem_s1_kill_0_REG_83 : _GEN_941) : _GEN_941; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_968 = _T_1536 | _T_1541; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_969 = _T_1528 ? (_GEN_968 ? ~_searcher_is_older_T_4 & _GEN_943 : ~(_T_1544 & _searcher_is_older_T_4) & _GEN_943) : _GEN_943; // @[util.scala:363:52] wire _GEN_970 = _T_1528 ? (_GEN_968 ? ~_GEN_309 & _GEN_944 : ~(_T_1544 & _GEN_309) & _GEN_944) : _GEN_944; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_971 = _T_1528 ? (_GEN_968 ? ~_GEN_310 & _GEN_945 : ~(_T_1544 & _GEN_310) & _GEN_945) : _GEN_945; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_972 = _T_1528 ? (_GEN_968 ? ~_GEN_311 & _GEN_946 : ~(_T_1544 & _GEN_311) & _GEN_946) : _GEN_946; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_973 = _T_1528 ? (_GEN_968 ? ~_GEN_312 & _GEN_947 : ~(_T_1544 & _GEN_312) & _GEN_947) : _GEN_947; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_974 = _T_1528 ? (_GEN_968 ? ~_GEN_313 & _GEN_948 : ~(_T_1544 & _GEN_313) & _GEN_948) : _GEN_948; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_975 = _T_1528 ? (_GEN_968 ? ~_GEN_314 & _GEN_949 : ~(_T_1544 & _GEN_314) & _GEN_949) : _GEN_949; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_976 = _T_1528 ? (_GEN_968 ? ~_GEN_315 & _GEN_950 : ~(_T_1544 & _GEN_315) & _GEN_950) : _GEN_950; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_977 = _T_1528 ? (_GEN_968 ? ~_GEN_316 & _GEN_951 : ~(_T_1544 & _GEN_316) & _GEN_951) : _GEN_951; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_978 = _T_1528 ? (_GEN_968 ? ~_GEN_317 & _GEN_952 : ~(_T_1544 & _GEN_317) & _GEN_952) : _GEN_952; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_979 = _T_1528 ? (_GEN_968 ? ~_GEN_318 & _GEN_953 : ~(_T_1544 & _GEN_318) & _GEN_953) : _GEN_953; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_980 = _T_1528 ? (_GEN_968 ? ~_GEN_319 & _GEN_954 : ~(_T_1544 & _GEN_319) & _GEN_954) : _GEN_954; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_981 = _T_1528 ? (_GEN_968 ? ~_GEN_320 & _GEN_955 : ~(_T_1544 & _GEN_320) & _GEN_955) : _GEN_955; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_982 = _T_1528 ? (_GEN_968 ? ~_GEN_321 & _GEN_956 : ~(_T_1544 & _GEN_321) & _GEN_956) : _GEN_956; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_983 = _T_1528 ? (_GEN_968 ? ~_GEN_322 & _GEN_957 : ~(_T_1544 & _GEN_322) & _GEN_957) : _GEN_957; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_984 = _T_1528 ? (_GEN_968 ? ~_GEN_323 & _GEN_958 : ~(_T_1544 & _GEN_323) & _GEN_958) : _GEN_958; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_985 = _T_1528 ? (_GEN_968 ? ~_GEN_324 & _GEN_959 : ~(_T_1544 & _GEN_324) & _GEN_959) : _GEN_959; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_986 = _T_1528 ? (_GEN_968 ? ~_GEN_325 & _GEN_960 : ~(_T_1544 & _GEN_325) & _GEN_960) : _GEN_960; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_987 = _T_1528 ? (_GEN_968 ? ~_GEN_326 & _GEN_961 : ~(_T_1544 & _GEN_326) & _GEN_961) : _GEN_961; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_988 = _T_1528 ? (_GEN_968 ? ~_GEN_327 & _GEN_962 : ~(_T_1544 & _GEN_327) & _GEN_962) : _GEN_962; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_989 = _T_1528 ? (_GEN_968 ? ~_GEN_328 & _GEN_963 : ~(_T_1544 & _GEN_328) & _GEN_963) : _GEN_963; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_990 = _T_1528 ? (_GEN_968 ? ~_GEN_329 & _GEN_964 : ~(_T_1544 & _GEN_329) & _GEN_964) : _GEN_964; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_991 = _T_1528 ? (_GEN_968 ? ~_GEN_330 & _GEN_965 : ~(_T_1544 & _GEN_330) & _GEN_965) : _GEN_965; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_992 = _T_1528 ? (_GEN_968 ? ~_GEN_331 & _GEN_966 : ~(_T_1544 & _GEN_331) & _GEN_966) : _GEN_966; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_216 = ~stq_20_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_217 = stq_20_bits_addr_valid & _dword_addr_matches_T_216; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_218 = stq_20_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_220 = _dword_addr_matches_T_218 == _dword_addr_matches_T_219; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_221 = _dword_addr_matches_T_217 & _dword_addr_matches_T_220; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_44_0 = _dword_addr_matches_T_221; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_20; // @[lsu.scala:1665:22] wire _write_mask_mask_T_300 = stq_20_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_301 = stq_20_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_302 = 15'h1 << _write_mask_mask_T_301; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_303 = stq_20_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_304 = stq_20_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_305 = {_write_mask_mask_T_304, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_306 = 15'h3 << _write_mask_mask_T_305; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_307 = stq_20_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_308 = stq_20_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_309 = _write_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_310 = &stq_20_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_312 = _write_mask_mask_T_307 ? _write_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_313 = _write_mask_mask_T_303 ? _write_mask_mask_T_306 : {7'h0, _write_mask_mask_T_312}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_314 = _write_mask_mask_T_300 ? _write_mask_mask_T_302 : _write_mask_mask_T_313; // @[Mux.scala:126:16] assign write_mask_20 = _write_mask_mask_T_314[7:0]; // @[Mux.scala:126:16] wire _T_1549 = do_ld_search_0 & stq_20_valid & lcam_st_dep_mask_0[20]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1560 = lcam_mask_0 & write_mask_20; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1557 = _T_1560 == lcam_mask_0 & ~stq_20_bits_uop_is_fence & ~stq_20_bits_uop_is_amo & dword_addr_matches_44_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_20 = _T_1549 & _T_1557; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_84; // @[lsu.scala:1154:56] wire _T_1562 = (|_T_1560) & dword_addr_matches_44_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_85; // @[lsu.scala:1160:56] wire _T_1565 = stq_20_bits_uop_is_fence | stq_20_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_20 = _T_1549 & (_T_1557 | _T_1562 | _T_1565); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_86; // @[lsu.scala:1166:56] wire _GEN_993 = _T_1549 ? (_T_1557 ? io_dmem_s1_kill_0_REG_84 : _T_1562 ? io_dmem_s1_kill_0_REG_85 : _T_1565 ? io_dmem_s1_kill_0_REG_86 : _GEN_967) : _GEN_967; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_994 = _T_1557 | _T_1562; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_995 = _T_1549 ? (_GEN_994 ? ~_searcher_is_older_T_4 & _GEN_969 : ~(_T_1565 & _searcher_is_older_T_4) & _GEN_969) : _GEN_969; // @[util.scala:363:52] wire _GEN_996 = _T_1549 ? (_GEN_994 ? ~_GEN_309 & _GEN_970 : ~(_T_1565 & _GEN_309) & _GEN_970) : _GEN_970; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_997 = _T_1549 ? (_GEN_994 ? ~_GEN_310 & _GEN_971 : ~(_T_1565 & _GEN_310) & _GEN_971) : _GEN_971; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_998 = _T_1549 ? (_GEN_994 ? ~_GEN_311 & _GEN_972 : ~(_T_1565 & _GEN_311) & _GEN_972) : _GEN_972; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_999 = _T_1549 ? (_GEN_994 ? ~_GEN_312 & _GEN_973 : ~(_T_1565 & _GEN_312) & _GEN_973) : _GEN_973; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1000 = _T_1549 ? (_GEN_994 ? ~_GEN_313 & _GEN_974 : ~(_T_1565 & _GEN_313) & _GEN_974) : _GEN_974; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1001 = _T_1549 ? (_GEN_994 ? ~_GEN_314 & _GEN_975 : ~(_T_1565 & _GEN_314) & _GEN_975) : _GEN_975; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1002 = _T_1549 ? (_GEN_994 ? ~_GEN_315 & _GEN_976 : ~(_T_1565 & _GEN_315) & _GEN_976) : _GEN_976; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1003 = _T_1549 ? (_GEN_994 ? ~_GEN_316 & _GEN_977 : ~(_T_1565 & _GEN_316) & _GEN_977) : _GEN_977; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1004 = _T_1549 ? (_GEN_994 ? ~_GEN_317 & _GEN_978 : ~(_T_1565 & _GEN_317) & _GEN_978) : _GEN_978; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1005 = _T_1549 ? (_GEN_994 ? ~_GEN_318 & _GEN_979 : ~(_T_1565 & _GEN_318) & _GEN_979) : _GEN_979; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1006 = _T_1549 ? (_GEN_994 ? ~_GEN_319 & _GEN_980 : ~(_T_1565 & _GEN_319) & _GEN_980) : _GEN_980; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1007 = _T_1549 ? (_GEN_994 ? ~_GEN_320 & _GEN_981 : ~(_T_1565 & _GEN_320) & _GEN_981) : _GEN_981; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1008 = _T_1549 ? (_GEN_994 ? ~_GEN_321 & _GEN_982 : ~(_T_1565 & _GEN_321) & _GEN_982) : _GEN_982; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1009 = _T_1549 ? (_GEN_994 ? ~_GEN_322 & _GEN_983 : ~(_T_1565 & _GEN_322) & _GEN_983) : _GEN_983; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1010 = _T_1549 ? (_GEN_994 ? ~_GEN_323 & _GEN_984 : ~(_T_1565 & _GEN_323) & _GEN_984) : _GEN_984; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1011 = _T_1549 ? (_GEN_994 ? ~_GEN_324 & _GEN_985 : ~(_T_1565 & _GEN_324) & _GEN_985) : _GEN_985; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1012 = _T_1549 ? (_GEN_994 ? ~_GEN_325 & _GEN_986 : ~(_T_1565 & _GEN_325) & _GEN_986) : _GEN_986; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1013 = _T_1549 ? (_GEN_994 ? ~_GEN_326 & _GEN_987 : ~(_T_1565 & _GEN_326) & _GEN_987) : _GEN_987; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1014 = _T_1549 ? (_GEN_994 ? ~_GEN_327 & _GEN_988 : ~(_T_1565 & _GEN_327) & _GEN_988) : _GEN_988; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1015 = _T_1549 ? (_GEN_994 ? ~_GEN_328 & _GEN_989 : ~(_T_1565 & _GEN_328) & _GEN_989) : _GEN_989; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1016 = _T_1549 ? (_GEN_994 ? ~_GEN_329 & _GEN_990 : ~(_T_1565 & _GEN_329) & _GEN_990) : _GEN_990; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1017 = _T_1549 ? (_GEN_994 ? ~_GEN_330 & _GEN_991 : ~(_T_1565 & _GEN_330) & _GEN_991) : _GEN_991; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1018 = _T_1549 ? (_GEN_994 ? ~_GEN_331 & _GEN_992 : ~(_T_1565 & _GEN_331) & _GEN_992) : _GEN_992; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_222 = ~stq_21_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_223 = stq_21_bits_addr_valid & _dword_addr_matches_T_222; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_224 = stq_21_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_226 = _dword_addr_matches_T_224 == _dword_addr_matches_T_225; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_227 = _dword_addr_matches_T_223 & _dword_addr_matches_T_226; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_45_0 = _dword_addr_matches_T_227; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_21; // @[lsu.scala:1665:22] wire _write_mask_mask_T_315 = stq_21_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_316 = stq_21_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_317 = 15'h1 << _write_mask_mask_T_316; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_318 = stq_21_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_319 = stq_21_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_320 = {_write_mask_mask_T_319, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_321 = 15'h3 << _write_mask_mask_T_320; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_322 = stq_21_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_323 = stq_21_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_324 = _write_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_325 = &stq_21_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_327 = _write_mask_mask_T_322 ? _write_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_328 = _write_mask_mask_T_318 ? _write_mask_mask_T_321 : {7'h0, _write_mask_mask_T_327}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_329 = _write_mask_mask_T_315 ? _write_mask_mask_T_317 : _write_mask_mask_T_328; // @[Mux.scala:126:16] assign write_mask_21 = _write_mask_mask_T_329[7:0]; // @[Mux.scala:126:16] wire _T_1570 = do_ld_search_0 & stq_21_valid & lcam_st_dep_mask_0[21]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1581 = lcam_mask_0 & write_mask_21; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1578 = _T_1581 == lcam_mask_0 & ~stq_21_bits_uop_is_fence & ~stq_21_bits_uop_is_amo & dword_addr_matches_45_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_21 = _T_1570 & _T_1578; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_87; // @[lsu.scala:1154:56] wire _T_1583 = (|_T_1581) & dword_addr_matches_45_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_88; // @[lsu.scala:1160:56] wire _T_1586 = stq_21_bits_uop_is_fence | stq_21_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_21 = _T_1570 & (_T_1578 | _T_1583 | _T_1586); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_89; // @[lsu.scala:1166:56] wire _GEN_1019 = _T_1570 ? (_T_1578 ? io_dmem_s1_kill_0_REG_87 : _T_1583 ? io_dmem_s1_kill_0_REG_88 : _T_1586 ? io_dmem_s1_kill_0_REG_89 : _GEN_993) : _GEN_993; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_1020 = _T_1578 | _T_1583; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_1021 = _T_1570 ? (_GEN_1020 ? ~_searcher_is_older_T_4 & _GEN_995 : ~(_T_1586 & _searcher_is_older_T_4) & _GEN_995) : _GEN_995; // @[util.scala:363:52] wire _GEN_1022 = _T_1570 ? (_GEN_1020 ? ~_GEN_309 & _GEN_996 : ~(_T_1586 & _GEN_309) & _GEN_996) : _GEN_996; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1023 = _T_1570 ? (_GEN_1020 ? ~_GEN_310 & _GEN_997 : ~(_T_1586 & _GEN_310) & _GEN_997) : _GEN_997; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1024 = _T_1570 ? (_GEN_1020 ? ~_GEN_311 & _GEN_998 : ~(_T_1586 & _GEN_311) & _GEN_998) : _GEN_998; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1025 = _T_1570 ? (_GEN_1020 ? ~_GEN_312 & _GEN_999 : ~(_T_1586 & _GEN_312) & _GEN_999) : _GEN_999; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1026 = _T_1570 ? (_GEN_1020 ? ~_GEN_313 & _GEN_1000 : ~(_T_1586 & _GEN_313) & _GEN_1000) : _GEN_1000; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1027 = _T_1570 ? (_GEN_1020 ? ~_GEN_314 & _GEN_1001 : ~(_T_1586 & _GEN_314) & _GEN_1001) : _GEN_1001; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1028 = _T_1570 ? (_GEN_1020 ? ~_GEN_315 & _GEN_1002 : ~(_T_1586 & _GEN_315) & _GEN_1002) : _GEN_1002; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1029 = _T_1570 ? (_GEN_1020 ? ~_GEN_316 & _GEN_1003 : ~(_T_1586 & _GEN_316) & _GEN_1003) : _GEN_1003; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1030 = _T_1570 ? (_GEN_1020 ? ~_GEN_317 & _GEN_1004 : ~(_T_1586 & _GEN_317) & _GEN_1004) : _GEN_1004; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1031 = _T_1570 ? (_GEN_1020 ? ~_GEN_318 & _GEN_1005 : ~(_T_1586 & _GEN_318) & _GEN_1005) : _GEN_1005; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1032 = _T_1570 ? (_GEN_1020 ? ~_GEN_319 & _GEN_1006 : ~(_T_1586 & _GEN_319) & _GEN_1006) : _GEN_1006; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1033 = _T_1570 ? (_GEN_1020 ? ~_GEN_320 & _GEN_1007 : ~(_T_1586 & _GEN_320) & _GEN_1007) : _GEN_1007; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1034 = _T_1570 ? (_GEN_1020 ? ~_GEN_321 & _GEN_1008 : ~(_T_1586 & _GEN_321) & _GEN_1008) : _GEN_1008; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1035 = _T_1570 ? (_GEN_1020 ? ~_GEN_322 & _GEN_1009 : ~(_T_1586 & _GEN_322) & _GEN_1009) : _GEN_1009; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1036 = _T_1570 ? (_GEN_1020 ? ~_GEN_323 & _GEN_1010 : ~(_T_1586 & _GEN_323) & _GEN_1010) : _GEN_1010; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1037 = _T_1570 ? (_GEN_1020 ? ~_GEN_324 & _GEN_1011 : ~(_T_1586 & _GEN_324) & _GEN_1011) : _GEN_1011; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1038 = _T_1570 ? (_GEN_1020 ? ~_GEN_325 & _GEN_1012 : ~(_T_1586 & _GEN_325) & _GEN_1012) : _GEN_1012; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1039 = _T_1570 ? (_GEN_1020 ? ~_GEN_326 & _GEN_1013 : ~(_T_1586 & _GEN_326) & _GEN_1013) : _GEN_1013; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1040 = _T_1570 ? (_GEN_1020 ? ~_GEN_327 & _GEN_1014 : ~(_T_1586 & _GEN_327) & _GEN_1014) : _GEN_1014; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1041 = _T_1570 ? (_GEN_1020 ? ~_GEN_328 & _GEN_1015 : ~(_T_1586 & _GEN_328) & _GEN_1015) : _GEN_1015; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1042 = _T_1570 ? (_GEN_1020 ? ~_GEN_329 & _GEN_1016 : ~(_T_1586 & _GEN_329) & _GEN_1016) : _GEN_1016; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1043 = _T_1570 ? (_GEN_1020 ? ~_GEN_330 & _GEN_1017 : ~(_T_1586 & _GEN_330) & _GEN_1017) : _GEN_1017; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1044 = _T_1570 ? (_GEN_1020 ? ~_GEN_331 & _GEN_1018 : ~(_T_1586 & _GEN_331) & _GEN_1018) : _GEN_1018; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_228 = ~stq_22_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_229 = stq_22_bits_addr_valid & _dword_addr_matches_T_228; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_230 = stq_22_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_232 = _dword_addr_matches_T_230 == _dword_addr_matches_T_231; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_233 = _dword_addr_matches_T_229 & _dword_addr_matches_T_232; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_46_0 = _dword_addr_matches_T_233; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_22; // @[lsu.scala:1665:22] wire _write_mask_mask_T_330 = stq_22_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_331 = stq_22_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_332 = 15'h1 << _write_mask_mask_T_331; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_333 = stq_22_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_334 = stq_22_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_335 = {_write_mask_mask_T_334, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_336 = 15'h3 << _write_mask_mask_T_335; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_337 = stq_22_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_338 = stq_22_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_339 = _write_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_340 = &stq_22_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_342 = _write_mask_mask_T_337 ? _write_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_343 = _write_mask_mask_T_333 ? _write_mask_mask_T_336 : {7'h0, _write_mask_mask_T_342}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_344 = _write_mask_mask_T_330 ? _write_mask_mask_T_332 : _write_mask_mask_T_343; // @[Mux.scala:126:16] assign write_mask_22 = _write_mask_mask_T_344[7:0]; // @[Mux.scala:126:16] wire _T_1591 = do_ld_search_0 & stq_22_valid & lcam_st_dep_mask_0[22]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1602 = lcam_mask_0 & write_mask_22; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1599 = _T_1602 == lcam_mask_0 & ~stq_22_bits_uop_is_fence & ~stq_22_bits_uop_is_amo & dword_addr_matches_46_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_22 = _T_1591 & _T_1599; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_90; // @[lsu.scala:1154:56] wire _T_1604 = (|_T_1602) & dword_addr_matches_46_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_91; // @[lsu.scala:1160:56] wire _T_1607 = stq_22_bits_uop_is_fence | stq_22_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_22 = _T_1591 & (_T_1599 | _T_1604 | _T_1607); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_92; // @[lsu.scala:1166:56] wire _GEN_1045 = _T_1591 ? (_T_1599 ? io_dmem_s1_kill_0_REG_90 : _T_1604 ? io_dmem_s1_kill_0_REG_91 : _T_1607 ? io_dmem_s1_kill_0_REG_92 : _GEN_1019) : _GEN_1019; // @[lsu.scala:1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_1046 = _T_1599 | _T_1604; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] wire _GEN_1047 = _T_1591 ? (_GEN_1046 ? ~_searcher_is_older_T_4 & _GEN_1021 : ~(_T_1607 & _searcher_is_older_T_4) & _GEN_1021) : _GEN_1021; // @[util.scala:363:52] wire _GEN_1048 = _T_1591 ? (_GEN_1046 ? ~_GEN_309 & _GEN_1022 : ~(_T_1607 & _GEN_309) & _GEN_1022) : _GEN_1022; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1049 = _T_1591 ? (_GEN_1046 ? ~_GEN_310 & _GEN_1023 : ~(_T_1607 & _GEN_310) & _GEN_1023) : _GEN_1023; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1050 = _T_1591 ? (_GEN_1046 ? ~_GEN_311 & _GEN_1024 : ~(_T_1607 & _GEN_311) & _GEN_1024) : _GEN_1024; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1051 = _T_1591 ? (_GEN_1046 ? ~_GEN_312 & _GEN_1025 : ~(_T_1607 & _GEN_312) & _GEN_1025) : _GEN_1025; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1052 = _T_1591 ? (_GEN_1046 ? ~_GEN_313 & _GEN_1026 : ~(_T_1607 & _GEN_313) & _GEN_1026) : _GEN_1026; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1053 = _T_1591 ? (_GEN_1046 ? ~_GEN_314 & _GEN_1027 : ~(_T_1607 & _GEN_314) & _GEN_1027) : _GEN_1027; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1054 = _T_1591 ? (_GEN_1046 ? ~_GEN_315 & _GEN_1028 : ~(_T_1607 & _GEN_315) & _GEN_1028) : _GEN_1028; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1055 = _T_1591 ? (_GEN_1046 ? ~_GEN_316 & _GEN_1029 : ~(_T_1607 & _GEN_316) & _GEN_1029) : _GEN_1029; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1056 = _T_1591 ? (_GEN_1046 ? ~_GEN_317 & _GEN_1030 : ~(_T_1607 & _GEN_317) & _GEN_1030) : _GEN_1030; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1057 = _T_1591 ? (_GEN_1046 ? ~_GEN_318 & _GEN_1031 : ~(_T_1607 & _GEN_318) & _GEN_1031) : _GEN_1031; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1058 = _T_1591 ? (_GEN_1046 ? ~_GEN_319 & _GEN_1032 : ~(_T_1607 & _GEN_319) & _GEN_1032) : _GEN_1032; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1059 = _T_1591 ? (_GEN_1046 ? ~_GEN_320 & _GEN_1033 : ~(_T_1607 & _GEN_320) & _GEN_1033) : _GEN_1033; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1060 = _T_1591 ? (_GEN_1046 ? ~_GEN_321 & _GEN_1034 : ~(_T_1607 & _GEN_321) & _GEN_1034) : _GEN_1034; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1061 = _T_1591 ? (_GEN_1046 ? ~_GEN_322 & _GEN_1035 : ~(_T_1607 & _GEN_322) & _GEN_1035) : _GEN_1035; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1062 = _T_1591 ? (_GEN_1046 ? ~_GEN_323 & _GEN_1036 : ~(_T_1607 & _GEN_323) & _GEN_1036) : _GEN_1036; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1063 = _T_1591 ? (_GEN_1046 ? ~_GEN_324 & _GEN_1037 : ~(_T_1607 & _GEN_324) & _GEN_1037) : _GEN_1037; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1064 = _T_1591 ? (_GEN_1046 ? ~_GEN_325 & _GEN_1038 : ~(_T_1607 & _GEN_325) & _GEN_1038) : _GEN_1038; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1065 = _T_1591 ? (_GEN_1046 ? ~_GEN_326 & _GEN_1039 : ~(_T_1607 & _GEN_326) & _GEN_1039) : _GEN_1039; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1066 = _T_1591 ? (_GEN_1046 ? ~_GEN_327 & _GEN_1040 : ~(_T_1607 & _GEN_327) & _GEN_1040) : _GEN_1040; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1067 = _T_1591 ? (_GEN_1046 ? ~_GEN_328 & _GEN_1041 : ~(_T_1607 & _GEN_328) & _GEN_1041) : _GEN_1041; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1068 = _T_1591 ? (_GEN_1046 ? ~_GEN_329 & _GEN_1042 : ~(_T_1607 & _GEN_329) & _GEN_1042) : _GEN_1042; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1069 = _T_1591 ? (_GEN_1046 ? ~_GEN_330 & _GEN_1043 : ~(_T_1607 & _GEN_330) & _GEN_1043) : _GEN_1043; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _GEN_1070 = _T_1591 ? (_GEN_1046 ? ~_GEN_331 & _GEN_1044 : ~(_T_1607 & _GEN_331) & _GEN_1044) : _GEN_1044; // @[lsu.scala:1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire _dword_addr_matches_T_234 = ~stq_23_bits_addr_is_virtual; // @[lsu.scala:209:16, :1145:31] wire _dword_addr_matches_T_235 = stq_23_bits_addr_valid & _dword_addr_matches_T_234; // @[lsu.scala:209:16, :1144:60, :1145:31] wire [28:0] _dword_addr_matches_T_236 = stq_23_bits_addr_bits[31:3]; // @[lsu.scala:209:16, :1146:38] wire _dword_addr_matches_T_238 = _dword_addr_matches_T_236 == _dword_addr_matches_T_237; // @[lsu.scala:1146:{38,58,74}] wire _dword_addr_matches_T_239 = _dword_addr_matches_T_235 & _dword_addr_matches_T_238; // @[lsu.scala:1144:60, :1145:60, :1146:58] wire dword_addr_matches_47_0 = _dword_addr_matches_T_239; // @[lsu.scala:263:49, :1145:60] wire [7:0] write_mask_23; // @[lsu.scala:1665:22] wire _write_mask_mask_T_345 = stq_23_bits_uop_mem_size == 2'h0; // @[lsu.scala:209:16, :1667:26] wire [2:0] _write_mask_mask_T_346 = stq_23_bits_addr_bits[2:0]; // @[lsu.scala:209:16, :1667:55] wire [14:0] _write_mask_mask_T_347 = 15'h1 << _write_mask_mask_T_346; // @[lsu.scala:1667:{48,55}] wire _write_mask_mask_T_348 = stq_23_bits_uop_mem_size == 2'h1; // @[lsu.scala:209:16, :1668:26] wire [1:0] _write_mask_mask_T_349 = stq_23_bits_addr_bits[2:1]; // @[lsu.scala:209:16, :1668:56] wire [2:0] _write_mask_mask_T_350 = {_write_mask_mask_T_349, 1'h0}; // @[lsu.scala:1668:{56,62}] wire [14:0] _write_mask_mask_T_351 = 15'h3 << _write_mask_mask_T_350; // @[lsu.scala:1668:{48,62}] wire _write_mask_mask_T_352 = stq_23_bits_uop_mem_size == 2'h2; // @[lsu.scala:209:16, :1669:26] wire _write_mask_mask_T_353 = stq_23_bits_addr_bits[2]; // @[lsu.scala:209:16, :1669:46] wire [7:0] _write_mask_mask_T_354 = _write_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1669:{41,46}] wire _write_mask_mask_T_355 = &stq_23_bits_uop_mem_size; // @[lsu.scala:209:16, :1670:26] wire [7:0] _write_mask_mask_T_357 = _write_mask_mask_T_352 ? _write_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_358 = _write_mask_mask_T_348 ? _write_mask_mask_T_351 : {7'h0, _write_mask_mask_T_357}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_359 = _write_mask_mask_T_345 ? _write_mask_mask_T_347 : _write_mask_mask_T_358; // @[Mux.scala:126:16] assign write_mask_23 = _write_mask_mask_T_359[7:0]; // @[Mux.scala:126:16] wire _T_1612 = do_ld_search_0 & stq_23_valid & lcam_st_dep_mask_0[23]; // @[lsu.scala:209:16, :263:49, :1149:{29,45,67}] wire [7:0] _T_1623 = lcam_mask_0 & write_mask_23; // @[lsu.scala:263:49, :1150:30, :1665:22] wire _T_1620 = _T_1623 == lcam_mask_0 & ~stq_23_bits_uop_is_fence & ~stq_23_bits_uop_is_amo & dword_addr_matches_47_0 & can_forward_0; // @[lsu.scala:209:16, :263:49, :1045:29, :1150:{30,44,62,65,81,84,98,123}] assign ldst_forward_matches_0_23 = _T_1612 & _T_1620; // @[lsu.scala:1052:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1153:46] reg io_dmem_s1_kill_0_REG_93; // @[lsu.scala:1154:56] wire _T_1625 = (|_T_1623) & dword_addr_matches_47_0; // @[lsu.scala:263:49, :1150:30, :1157:{51,60}] reg io_dmem_s1_kill_0_REG_94; // @[lsu.scala:1160:56] wire _T_1628 = stq_23_bits_uop_is_fence | stq_23_bits_uop_is_amo; // @[lsu.scala:209:16, :1163:37] assign ldst_addr_matches_0_23 = _T_1612 & (_T_1620 | _T_1625 | _T_1628); // @[lsu.scala:1050:38, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1152:46, :1157:60, :1158:9, :1159:46, :1163:37, :1164:9, :1165:46] reg io_dmem_s1_kill_0_REG_95; // @[lsu.scala:1166:56] assign io_dmem_s1_kill_0_0 = _T_1612 ? (_T_1620 ? io_dmem_s1_kill_0_REG_93 : _T_1625 ? io_dmem_s1_kill_0_REG_94 : _T_1628 ? io_dmem_s1_kill_0_REG_95 : _GEN_1045) : _GEN_1045; // @[lsu.scala:201:7, :1149:{29,45,72}, :1150:{62,81,98,123}, :1151:9, :1154:{46,56}, :1157:60, :1158:9, :1160:{46,56}, :1163:37, :1164:9, :1166:{46,56}] wire _GEN_1071 = _T_1620 | _T_1625; // @[lsu.scala:1150:{62,81,98,123}, :1151:9, :1155:46, :1157:60, :1158:9] assign s1_set_execute_0 = _T_1612 ? (_GEN_1071 ? ~_searcher_is_older_T_4 & _GEN_1047 : ~(_T_1628 & _searcher_is_older_T_4) & _GEN_1047) : _GEN_1047; // @[util.scala:363:52] assign s1_set_execute_1 = _T_1612 ? (_GEN_1071 ? ~_GEN_309 & _GEN_1048 : ~(_T_1628 & _GEN_309) & _GEN_1048) : _GEN_1048; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_2 = _T_1612 ? (_GEN_1071 ? ~_GEN_310 & _GEN_1049 : ~(_T_1628 & _GEN_310) & _GEN_1049) : _GEN_1049; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_3 = _T_1612 ? (_GEN_1071 ? ~_GEN_311 & _GEN_1050 : ~(_T_1628 & _GEN_311) & _GEN_1050) : _GEN_1050; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_4 = _T_1612 ? (_GEN_1071 ? ~_GEN_312 & _GEN_1051 : ~(_T_1628 & _GEN_312) & _GEN_1051) : _GEN_1051; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_5 = _T_1612 ? (_GEN_1071 ? ~_GEN_313 & _GEN_1052 : ~(_T_1628 & _GEN_313) & _GEN_1052) : _GEN_1052; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_6 = _T_1612 ? (_GEN_1071 ? ~_GEN_314 & _GEN_1053 : ~(_T_1628 & _GEN_314) & _GEN_1053) : _GEN_1053; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_7 = _T_1612 ? (_GEN_1071 ? ~_GEN_315 & _GEN_1054 : ~(_T_1628 & _GEN_315) & _GEN_1054) : _GEN_1054; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_8 = _T_1612 ? (_GEN_1071 ? ~_GEN_316 & _GEN_1055 : ~(_T_1628 & _GEN_316) & _GEN_1055) : _GEN_1055; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_9 = _T_1612 ? (_GEN_1071 ? ~_GEN_317 & _GEN_1056 : ~(_T_1628 & _GEN_317) & _GEN_1056) : _GEN_1056; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_10 = _T_1612 ? (_GEN_1071 ? ~_GEN_318 & _GEN_1057 : ~(_T_1628 & _GEN_318) & _GEN_1057) : _GEN_1057; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_11 = _T_1612 ? (_GEN_1071 ? ~_GEN_319 & _GEN_1058 : ~(_T_1628 & _GEN_319) & _GEN_1058) : _GEN_1058; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_12 = _T_1612 ? (_GEN_1071 ? ~_GEN_320 & _GEN_1059 : ~(_T_1628 & _GEN_320) & _GEN_1059) : _GEN_1059; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_13 = _T_1612 ? (_GEN_1071 ? ~_GEN_321 & _GEN_1060 : ~(_T_1628 & _GEN_321) & _GEN_1060) : _GEN_1060; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_14 = _T_1612 ? (_GEN_1071 ? ~_GEN_322 & _GEN_1061 : ~(_T_1628 & _GEN_322) & _GEN_1061) : _GEN_1061; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_15 = _T_1612 ? (_GEN_1071 ? ~_GEN_323 & _GEN_1062 : ~(_T_1628 & _GEN_323) & _GEN_1062) : _GEN_1062; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_16 = _T_1612 ? (_GEN_1071 ? ~_GEN_324 & _GEN_1063 : ~(_T_1628 & _GEN_324) & _GEN_1063) : _GEN_1063; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_17 = _T_1612 ? (_GEN_1071 ? ~_GEN_325 & _GEN_1064 : ~(_T_1628 & _GEN_325) & _GEN_1064) : _GEN_1064; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_18 = _T_1612 ? (_GEN_1071 ? ~_GEN_326 & _GEN_1065 : ~(_T_1628 & _GEN_326) & _GEN_1065) : _GEN_1065; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_19 = _T_1612 ? (_GEN_1071 ? ~_GEN_327 & _GEN_1066 : ~(_T_1628 & _GEN_327) & _GEN_1066) : _GEN_1066; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_20 = _T_1612 ? (_GEN_1071 ? ~_GEN_328 & _GEN_1067 : ~(_T_1628 & _GEN_328) & _GEN_1067) : _GEN_1067; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_21 = _T_1612 ? (_GEN_1071 ? ~_GEN_329 & _GEN_1068 : ~(_T_1628 & _GEN_329) & _GEN_1068) : _GEN_1068; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_22 = _T_1612 ? (_GEN_1071 ? ~_GEN_330 & _GEN_1069 : ~(_T_1628 & _GEN_330) & _GEN_1069) : _GEN_1069; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] assign s1_set_execute_23 = _T_1612 ? (_GEN_1071 ? ~_GEN_331 & _GEN_1070 : ~(_T_1628 & _GEN_331) & _GEN_1070) : _GEN_1070; // @[lsu.scala:1058:36, :1092:36, :1131:48, :1149:{29,45,72}, :1151:9, :1155:46, :1158:9, :1163:37, :1164:9, :1167:46] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi = {ldst_addr_matches_0_2, ldst_addr_matches_0_1}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_lo_lo = {forwarding_age_logic_0_io_addr_matches_lo_lo_lo_hi, ldst_addr_matches_0_0}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi = {ldst_addr_matches_0_5, ldst_addr_matches_0_4}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_lo_hi = {forwarding_age_logic_0_io_addr_matches_lo_lo_hi_hi, ldst_addr_matches_0_3}; // @[lsu.scala:1050:38, :1181:72] wire [5:0] forwarding_age_logic_0_io_addr_matches_lo_lo = {forwarding_age_logic_0_io_addr_matches_lo_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo_lo}; // @[lsu.scala:1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi = {ldst_addr_matches_0_8, ldst_addr_matches_0_7}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_hi_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi_lo_hi, ldst_addr_matches_0_6}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi = {ldst_addr_matches_0_11, ldst_addr_matches_0_10}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_lo_hi_hi = {forwarding_age_logic_0_io_addr_matches_lo_hi_hi_hi, ldst_addr_matches_0_9}; // @[lsu.scala:1050:38, :1181:72] wire [5:0] forwarding_age_logic_0_io_addr_matches_lo_hi = {forwarding_age_logic_0_io_addr_matches_lo_hi_hi, forwarding_age_logic_0_io_addr_matches_lo_hi_lo}; // @[lsu.scala:1181:72] wire [11:0] forwarding_age_logic_0_io_addr_matches_lo = {forwarding_age_logic_0_io_addr_matches_lo_hi, forwarding_age_logic_0_io_addr_matches_lo_lo}; // @[lsu.scala:1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi = {ldst_addr_matches_0_14, ldst_addr_matches_0_13}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_lo_lo = {forwarding_age_logic_0_io_addr_matches_hi_lo_lo_hi, ldst_addr_matches_0_12}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi = {ldst_addr_matches_0_17, ldst_addr_matches_0_16}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_lo_hi = {forwarding_age_logic_0_io_addr_matches_hi_lo_hi_hi, ldst_addr_matches_0_15}; // @[lsu.scala:1050:38, :1181:72] wire [5:0] forwarding_age_logic_0_io_addr_matches_hi_lo = {forwarding_age_logic_0_io_addr_matches_hi_lo_hi, forwarding_age_logic_0_io_addr_matches_hi_lo_lo}; // @[lsu.scala:1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi = {ldst_addr_matches_0_20, ldst_addr_matches_0_19}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_hi_lo = {forwarding_age_logic_0_io_addr_matches_hi_hi_lo_hi, ldst_addr_matches_0_18}; // @[lsu.scala:1050:38, :1181:72] wire [1:0] forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi = {ldst_addr_matches_0_23, ldst_addr_matches_0_22}; // @[lsu.scala:1050:38, :1181:72] wire [2:0] forwarding_age_logic_0_io_addr_matches_hi_hi_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi_hi_hi, ldst_addr_matches_0_21}; // @[lsu.scala:1050:38, :1181:72] wire [5:0] forwarding_age_logic_0_io_addr_matches_hi_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_hi_lo}; // @[lsu.scala:1181:72] wire [11:0] forwarding_age_logic_0_io_addr_matches_hi = {forwarding_age_logic_0_io_addr_matches_hi_hi, forwarding_age_logic_0_io_addr_matches_hi_lo}; // @[lsu.scala:1181:72] wire [23:0] _forwarding_age_logic_0_io_addr_matches_T = {forwarding_age_logic_0_io_addr_matches_hi, forwarding_age_logic_0_io_addr_matches_lo}; // @[lsu.scala:1181:72] assign mem_forward_stq_idx_0 = forwarding_idx_0; // @[lsu.scala:263:49, :1063:33] wire [31:0] _GEN_1072 = {{ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_0}, {ldst_forward_matches_0_23}, {ldst_forward_matches_0_22}, {ldst_forward_matches_0_21}, {ldst_forward_matches_0_20}, {ldst_forward_matches_0_19}, {ldst_forward_matches_0_18}, {ldst_forward_matches_0_17}, {ldst_forward_matches_0_16}, {ldst_forward_matches_0_15}, {ldst_forward_matches_0_14}, {ldst_forward_matches_0_13}, {ldst_forward_matches_0_12}, {ldst_forward_matches_0_11}, {ldst_forward_matches_0_10}, {ldst_forward_matches_0_9}, {ldst_forward_matches_0_8}, {ldst_forward_matches_0_7}, {ldst_forward_matches_0_6}, {ldst_forward_matches_0_5}, {ldst_forward_matches_0_4}, {ldst_forward_matches_0_3}, {ldst_forward_matches_0_2}, {ldst_forward_matches_0_1}, {ldst_forward_matches_0_0}}; // @[lsu.scala:1052:38, :1188:86] reg REG_1; // @[lsu.scala:1190:64] assign mem_forward_valid_0 = _GEN_1072[forwarding_idx_0] & (io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask) == 16'h0 & ~io_core_exception_0 & ~REG_1; // @[util.scala:118:{51,59}] reg REG_2; // @[lsu.scala:1200:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1205:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1205:36, :1209:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1205:36, :1209:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1209:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1209:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) | REG_2; // @[lsu.scala:499:35, :1200:{18,80}, :1205:36, :1211:{33,43}, :1212:25] wire _io_core_clr_unsafe_0_valid_T = do_st_search_0 | do_ld_search_0; // @[lsu.scala:263:49, :1221:61] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_wakeup_0; // @[lsu.scala:263:49, :1221:84] wire _io_core_clr_unsafe_0_valid_T_2 = _io_core_clr_unsafe_0_valid_T & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:1221:{61,81,84}] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1221:43] reg [6:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1222:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:201:7, :1222:43] wire _temp_bits_T_1 = failed_loads_0 & _temp_bits_T; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_0 = _temp_bits_T_1; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_3 = failed_loads_1 & _temp_bits_T_2; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_1 = _temp_bits_T_3; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_5 = failed_loads_2 & _temp_bits_T_4; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_2 = _temp_bits_T_5; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_7 = failed_loads_3 & _temp_bits_T_6; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_3 = _temp_bits_T_7; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_9 = failed_loads_4 & _temp_bits_T_8; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_4 = _temp_bits_T_9; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_11 = failed_loads_5 & _temp_bits_T_10; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_5 = _temp_bits_T_11; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_13 = failed_loads_6 & _temp_bits_T_12; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_6 = _temp_bits_T_13; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_15 = failed_loads_7 & _temp_bits_T_14; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_7 = _temp_bits_T_15; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_17 = failed_loads_8 & _temp_bits_T_16; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_8 = _temp_bits_T_17; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_19 = failed_loads_9 & _temp_bits_T_18; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_9 = _temp_bits_T_19; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_21 = failed_loads_10 & _temp_bits_T_20; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_10 = _temp_bits_T_21; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_23 = failed_loads_11 & _temp_bits_T_22; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_11 = _temp_bits_T_23; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_25 = failed_loads_12 & _temp_bits_T_24; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_12 = _temp_bits_T_25; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_27 = failed_loads_13 & _temp_bits_T_26; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_13 = _temp_bits_T_27; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_29 = failed_loads_14 & _temp_bits_T_28; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_14 = _temp_bits_T_29; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_30 = ~_searcher_is_older_T_63; // @[util.scala:351:72, :363:78] wire _temp_bits_T_31 = failed_loads_15 & _temp_bits_T_30; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_15 = _temp_bits_T_31; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_33 = failed_loads_16 & _temp_bits_T_32; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_16 = _temp_bits_T_33; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_35 = failed_loads_17 & _temp_bits_T_34; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_17 = _temp_bits_T_35; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_37 = failed_loads_18 & _temp_bits_T_36; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_18 = _temp_bits_T_37; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_39 = failed_loads_19 & _temp_bits_T_38; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_19 = _temp_bits_T_39; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_41 = failed_loads_20 & _temp_bits_T_40; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_20 = _temp_bits_T_41; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_43 = failed_loads_21 & _temp_bits_T_42; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_21 = _temp_bits_T_43; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_45 = failed_loads_22 & _temp_bits_T_44; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_22 = _temp_bits_T_45; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_T_47 = failed_loads_23 & _temp_bits_T_46; // @[lsu.scala:1054:34, :1230:{21,28}] wire _temp_bits_WIRE_23 = _temp_bits_T_47; // @[lsu.scala:1229:59, :1230:21] wire _temp_bits_WIRE_1_0 = _temp_bits_WIRE_0; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_1 = _temp_bits_WIRE_1; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_2 = _temp_bits_WIRE_2; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_3 = _temp_bits_WIRE_3; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_4 = _temp_bits_WIRE_4; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_5 = _temp_bits_WIRE_5; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_6 = _temp_bits_WIRE_6; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_7 = _temp_bits_WIRE_7; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_8 = _temp_bits_WIRE_8; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_9 = _temp_bits_WIRE_9; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_10 = _temp_bits_WIRE_10; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_11 = _temp_bits_WIRE_11; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_12 = _temp_bits_WIRE_12; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_13 = _temp_bits_WIRE_13; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_14 = _temp_bits_WIRE_14; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_15 = _temp_bits_WIRE_15; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_16 = _temp_bits_WIRE_16; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_17 = _temp_bits_WIRE_17; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_18 = _temp_bits_WIRE_18; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_19 = _temp_bits_WIRE_19; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_20 = _temp_bits_WIRE_20; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_21 = _temp_bits_WIRE_21; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_22 = _temp_bits_WIRE_22; // @[lsu.scala:1229:{27,59}] wire _temp_bits_WIRE_1_23 = _temp_bits_WIRE_23; // @[lsu.scala:1229:{27,59}] wire [1:0] temp_bits_lo_lo_lo_lo_hi = {_temp_bits_WIRE_1_2, _temp_bits_WIRE_1_1}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_lo_lo_lo = {temp_bits_lo_lo_lo_lo_hi, _temp_bits_WIRE_1_0}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_lo_lo_hi_hi = {_temp_bits_WIRE_1_5, _temp_bits_WIRE_1_4}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_lo_lo_hi = {temp_bits_lo_lo_lo_hi_hi, _temp_bits_WIRE_1_3}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_lo_lo_lo = {temp_bits_lo_lo_lo_hi, temp_bits_lo_lo_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_lo_lo_hi_lo_hi = {_temp_bits_WIRE_1_8, _temp_bits_WIRE_1_7}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_lo_hi_lo = {temp_bits_lo_lo_hi_lo_hi, _temp_bits_WIRE_1_6}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_lo_hi_hi_hi = {_temp_bits_WIRE_1_11, _temp_bits_WIRE_1_10}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_lo_hi_hi = {temp_bits_lo_lo_hi_hi_hi, _temp_bits_WIRE_1_9}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_lo_lo_hi = {temp_bits_lo_lo_hi_hi, temp_bits_lo_lo_hi_lo}; // @[lsu.scala:1230:59] wire [11:0] temp_bits_lo_lo = {temp_bits_lo_lo_hi, temp_bits_lo_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_lo_hi_lo_lo_hi = {_temp_bits_WIRE_1_14, _temp_bits_WIRE_1_13}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_hi_lo_lo = {temp_bits_lo_hi_lo_lo_hi, _temp_bits_WIRE_1_12}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_hi_lo_hi_hi = {_temp_bits_WIRE_1_17, _temp_bits_WIRE_1_16}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_hi_lo_hi = {temp_bits_lo_hi_lo_hi_hi, _temp_bits_WIRE_1_15}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_lo_hi_lo = {temp_bits_lo_hi_lo_hi, temp_bits_lo_hi_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_lo_hi_hi_lo_hi = {_temp_bits_WIRE_1_20, _temp_bits_WIRE_1_19}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_hi_hi_lo = {temp_bits_lo_hi_hi_lo_hi, _temp_bits_WIRE_1_18}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_lo_hi_hi_hi_hi = {_temp_bits_WIRE_1_23, _temp_bits_WIRE_1_22}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_lo_hi_hi_hi = {temp_bits_lo_hi_hi_hi_hi, _temp_bits_WIRE_1_21}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_lo_hi_hi = {temp_bits_lo_hi_hi_hi, temp_bits_lo_hi_hi_lo}; // @[lsu.scala:1230:59] wire [11:0] temp_bits_lo_hi = {temp_bits_lo_hi_hi, temp_bits_lo_hi_lo}; // @[lsu.scala:1230:59] wire [23:0] temp_bits_lo = {temp_bits_lo_hi, temp_bits_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_lo_lo_lo_hi = {_temp_bits_WIRE_1_26, _temp_bits_WIRE_1_25}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_lo_lo_lo = {temp_bits_hi_lo_lo_lo_hi, _temp_bits_WIRE_1_24}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_lo_lo_hi_hi = {_temp_bits_WIRE_1_29, _temp_bits_WIRE_1_28}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_lo_lo_hi = {temp_bits_hi_lo_lo_hi_hi, _temp_bits_WIRE_1_27}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_hi_lo_lo = {temp_bits_hi_lo_lo_hi, temp_bits_hi_lo_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_lo_hi_lo_hi = {_temp_bits_WIRE_1_32, _temp_bits_WIRE_1_31}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_lo_hi_lo = {temp_bits_hi_lo_hi_lo_hi, _temp_bits_WIRE_1_30}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_lo_hi_hi_hi = {_temp_bits_WIRE_1_35, _temp_bits_WIRE_1_34}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_lo_hi_hi = {temp_bits_hi_lo_hi_hi_hi, _temp_bits_WIRE_1_33}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_hi_lo_hi = {temp_bits_hi_lo_hi_hi, temp_bits_hi_lo_hi_lo}; // @[lsu.scala:1230:59] wire [11:0] temp_bits_hi_lo = {temp_bits_hi_lo_hi, temp_bits_hi_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_hi_lo_lo_hi = {_temp_bits_WIRE_1_38, _temp_bits_WIRE_1_37}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_hi_lo_lo = {temp_bits_hi_hi_lo_lo_hi, _temp_bits_WIRE_1_36}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_hi_lo_hi_hi = {_temp_bits_WIRE_1_41, _temp_bits_WIRE_1_40}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_hi_lo_hi = {temp_bits_hi_hi_lo_hi_hi, _temp_bits_WIRE_1_39}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_hi_hi_lo = {temp_bits_hi_hi_lo_hi, temp_bits_hi_hi_lo_lo}; // @[lsu.scala:1230:59] wire [1:0] temp_bits_hi_hi_hi_lo_hi = {_temp_bits_WIRE_1_44, _temp_bits_WIRE_1_43}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_hi_hi_lo = {temp_bits_hi_hi_hi_lo_hi, _temp_bits_WIRE_1_42}; // @[lsu.scala:1229:27, :1230:59] wire [1:0] temp_bits_hi_hi_hi_hi_hi = {_temp_bits_WIRE_1_47, _temp_bits_WIRE_1_46}; // @[lsu.scala:1229:27, :1230:59] wire [2:0] temp_bits_hi_hi_hi_hi = {temp_bits_hi_hi_hi_hi_hi, _temp_bits_WIRE_1_45}; // @[lsu.scala:1229:27, :1230:59] wire [5:0] temp_bits_hi_hi_hi = {temp_bits_hi_hi_hi_hi, temp_bits_hi_hi_hi_lo}; // @[lsu.scala:1230:59] wire [11:0] temp_bits_hi_hi = {temp_bits_hi_hi_hi, temp_bits_hi_hi_lo}; // @[lsu.scala:1230:59] wire [23:0] temp_bits_hi = {temp_bits_hi_hi, temp_bits_hi_lo}; // @[lsu.scala:1230:59] wire [47:0] temp_bits = {temp_bits_hi, temp_bits_lo}; // @[lsu.scala:1230:59] wire _l_idx_T = temp_bits[0]; // @[OneHot.scala:48:45] wire _l_idx_T_1 = temp_bits[1]; // @[OneHot.scala:48:45] wire _l_idx_T_2 = temp_bits[2]; // @[OneHot.scala:48:45] wire _l_idx_T_3 = temp_bits[3]; // @[OneHot.scala:48:45] wire _l_idx_T_4 = temp_bits[4]; // @[OneHot.scala:48:45] wire _l_idx_T_5 = temp_bits[5]; // @[OneHot.scala:48:45] wire _l_idx_T_6 = temp_bits[6]; // @[OneHot.scala:48:45] wire _l_idx_T_7 = temp_bits[7]; // @[OneHot.scala:48:45] wire _l_idx_T_8 = temp_bits[8]; // @[OneHot.scala:48:45] wire _l_idx_T_9 = temp_bits[9]; // @[OneHot.scala:48:45] wire _l_idx_T_10 = temp_bits[10]; // @[OneHot.scala:48:45] wire _l_idx_T_11 = temp_bits[11]; // @[OneHot.scala:48:45] wire _l_idx_T_12 = temp_bits[12]; // @[OneHot.scala:48:45] wire _l_idx_T_13 = temp_bits[13]; // @[OneHot.scala:48:45] wire _l_idx_T_14 = temp_bits[14]; // @[OneHot.scala:48:45] wire _l_idx_T_15 = temp_bits[15]; // @[OneHot.scala:48:45] wire _l_idx_T_16 = temp_bits[16]; // @[OneHot.scala:48:45] wire _l_idx_T_17 = temp_bits[17]; // @[OneHot.scala:48:45] wire _l_idx_T_18 = temp_bits[18]; // @[OneHot.scala:48:45] wire _l_idx_T_19 = temp_bits[19]; // @[OneHot.scala:48:45] wire _l_idx_T_20 = temp_bits[20]; // @[OneHot.scala:48:45] wire _l_idx_T_21 = temp_bits[21]; // @[OneHot.scala:48:45] wire _l_idx_T_22 = temp_bits[22]; // @[OneHot.scala:48:45] wire _l_idx_T_23 = temp_bits[23]; // @[OneHot.scala:48:45] wire _l_idx_T_24 = temp_bits[24]; // @[OneHot.scala:48:45] wire _l_idx_T_25 = temp_bits[25]; // @[OneHot.scala:48:45] wire _l_idx_T_26 = temp_bits[26]; // @[OneHot.scala:48:45] wire _l_idx_T_27 = temp_bits[27]; // @[OneHot.scala:48:45] wire _l_idx_T_28 = temp_bits[28]; // @[OneHot.scala:48:45] wire _l_idx_T_29 = temp_bits[29]; // @[OneHot.scala:48:45] wire _l_idx_T_30 = temp_bits[30]; // @[OneHot.scala:48:45] wire _l_idx_T_31 = temp_bits[31]; // @[OneHot.scala:48:45] wire _l_idx_T_32 = temp_bits[32]; // @[OneHot.scala:48:45] wire _l_idx_T_33 = temp_bits[33]; // @[OneHot.scala:48:45] wire _l_idx_T_34 = temp_bits[34]; // @[OneHot.scala:48:45] wire _l_idx_T_35 = temp_bits[35]; // @[OneHot.scala:48:45] wire _l_idx_T_36 = temp_bits[36]; // @[OneHot.scala:48:45] wire _l_idx_T_37 = temp_bits[37]; // @[OneHot.scala:48:45] wire _l_idx_T_38 = temp_bits[38]; // @[OneHot.scala:48:45] wire _l_idx_T_39 = temp_bits[39]; // @[OneHot.scala:48:45] wire _l_idx_T_40 = temp_bits[40]; // @[OneHot.scala:48:45] wire _l_idx_T_41 = temp_bits[41]; // @[OneHot.scala:48:45] wire _l_idx_T_42 = temp_bits[42]; // @[OneHot.scala:48:45] wire _l_idx_T_43 = temp_bits[43]; // @[OneHot.scala:48:45] wire _l_idx_T_44 = temp_bits[44]; // @[OneHot.scala:48:45] wire _l_idx_T_45 = temp_bits[45]; // @[OneHot.scala:48:45] wire _l_idx_T_46 = temp_bits[46]; // @[OneHot.scala:48:45] wire _l_idx_T_47 = temp_bits[47]; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_48 = {5'h17, ~_l_idx_T_46}; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_49 = _l_idx_T_45 ? 6'h2D : _l_idx_T_48; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_50 = _l_idx_T_44 ? 6'h2C : _l_idx_T_49; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_51 = _l_idx_T_43 ? 6'h2B : _l_idx_T_50; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_52 = _l_idx_T_42 ? 6'h2A : _l_idx_T_51; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_53 = _l_idx_T_41 ? 6'h29 : _l_idx_T_52; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_54 = _l_idx_T_40 ? 6'h28 : _l_idx_T_53; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_55 = _l_idx_T_39 ? 6'h27 : _l_idx_T_54; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_56 = _l_idx_T_38 ? 6'h26 : _l_idx_T_55; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_57 = _l_idx_T_37 ? 6'h25 : _l_idx_T_56; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_58 = _l_idx_T_36 ? 6'h24 : _l_idx_T_57; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_59 = _l_idx_T_35 ? 6'h23 : _l_idx_T_58; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_60 = _l_idx_T_34 ? 6'h22 : _l_idx_T_59; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_61 = _l_idx_T_33 ? 6'h21 : _l_idx_T_60; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_62 = _l_idx_T_32 ? 6'h20 : _l_idx_T_61; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_63 = _l_idx_T_31 ? 6'h1F : _l_idx_T_62; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_64 = _l_idx_T_30 ? 6'h1E : _l_idx_T_63; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_65 = _l_idx_T_29 ? 6'h1D : _l_idx_T_64; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_66 = _l_idx_T_28 ? 6'h1C : _l_idx_T_65; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_67 = _l_idx_T_27 ? 6'h1B : _l_idx_T_66; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_68 = _l_idx_T_26 ? 6'h1A : _l_idx_T_67; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_69 = _l_idx_T_25 ? 6'h19 : _l_idx_T_68; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_70 = _l_idx_T_24 ? 6'h18 : _l_idx_T_69; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_71 = _l_idx_T_23 ? 6'h17 : _l_idx_T_70; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_72 = _l_idx_T_22 ? 6'h16 : _l_idx_T_71; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_73 = _l_idx_T_21 ? 6'h15 : _l_idx_T_72; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_74 = _l_idx_T_20 ? 6'h14 : _l_idx_T_73; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_75 = _l_idx_T_19 ? 6'h13 : _l_idx_T_74; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_76 = _l_idx_T_18 ? 6'h12 : _l_idx_T_75; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_77 = _l_idx_T_17 ? 6'h11 : _l_idx_T_76; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_78 = _l_idx_T_16 ? 6'h10 : _l_idx_T_77; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_79 = _l_idx_T_15 ? 6'hF : _l_idx_T_78; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_80 = _l_idx_T_14 ? 6'hE : _l_idx_T_79; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_81 = _l_idx_T_13 ? 6'hD : _l_idx_T_80; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_82 = _l_idx_T_12 ? 6'hC : _l_idx_T_81; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_83 = _l_idx_T_11 ? 6'hB : _l_idx_T_82; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_84 = _l_idx_T_10 ? 6'hA : _l_idx_T_83; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_85 = _l_idx_T_9 ? 6'h9 : _l_idx_T_84; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_86 = _l_idx_T_8 ? 6'h8 : _l_idx_T_85; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_87 = _l_idx_T_7 ? 6'h7 : _l_idx_T_86; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_88 = _l_idx_T_6 ? 6'h6 : _l_idx_T_87; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_89 = _l_idx_T_5 ? 6'h5 : _l_idx_T_88; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_90 = _l_idx_T_4 ? 6'h4 : _l_idx_T_89; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_91 = _l_idx_T_3 ? 6'h3 : _l_idx_T_90; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_92 = _l_idx_T_2 ? 6'h2 : _l_idx_T_91; // @[OneHot.scala:48:45] wire [5:0] _l_idx_T_93 = _l_idx_T_1 ? 6'h1 : _l_idx_T_92; // @[OneHot.scala:48:45] wire [5:0] l_idx = _l_idx_T ? 6'h0 : _l_idx_T_93; // @[OneHot.scala:48:45] reg r_xcpt_valid; // @[lsu.scala:1236:29] reg [6:0] r_xcpt_uop_uopc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uopc_0 = r_xcpt_uop_uopc; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:201:7, :1237:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_iq_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iq_type_0 = r_xcpt_uop_iq_type; // @[lsu.scala:201:7, :1237:25] reg [9:0] r_xcpt_uop_fu_code; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fu_code_0 = r_xcpt_uop_fu_code; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_ctrl_br_type; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_br_type_0 = r_xcpt_uop_ctrl_br_type; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op1_sel_0 = r_xcpt_uop_ctrl_op1_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op2_sel_0 = r_xcpt_uop_ctrl_op2_sel; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_imm_sel_0 = r_xcpt_uop_ctrl_imm_sel; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_op_fcn_0 = r_xcpt_uop_ctrl_op_fcn; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_fcn_dw_0 = r_xcpt_uop_ctrl_fcn_dw; // @[lsu.scala:201:7, :1237:25] reg [2:0] r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_csr_cmd_0 = r_xcpt_uop_ctrl_csr_cmd; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_load; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_load_0 = r_xcpt_uop_ctrl_is_load; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_sta_0 = r_xcpt_uop_ctrl_is_sta; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ctrl_is_std; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ctrl_is_std_0 = r_xcpt_uop_ctrl_is_std; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_iw_state; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_state_0 = r_xcpt_uop_iw_state; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p1_poisoned_0 = r_xcpt_uop_iw_p1_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_iw_p2_poisoned_0 = r_xcpt_uop_iw_p2_poisoned; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_br; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_br_0 = r_xcpt_uop_is_br; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jalr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jalr_0 = r_xcpt_uop_is_jalr; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_jal; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_jal_0 = r_xcpt_uop_is_jal; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:201:7, :1237:25] reg [15:0] r_xcpt_uop_br_mask; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:201:7, :1237:25] reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_taken; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:201:7, :1237:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:201:7, :1237:25] reg [11:0] r_xcpt_uop_csr_addr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_csr_addr_0 = r_xcpt_uop_csr_addr; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:201:7, :1237:25] reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_exception; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:201:7, :1237:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bypassable; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bypassable_0 = r_xcpt_uop_bypassable; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:201:7, :1237:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_ldst_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_ldst_val_0 = r_xcpt_uop_ldst_val; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_fp_single; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_fp_single_0 = r_xcpt_uop_fp_single; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:201:7, :1237:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:201:7, :1237:25] reg [1:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:201:7, :1237:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:201:7, :1237:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1237:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:201:7, :1237:25] wire _ld_xcpt_valid_T = failed_loads_0 | failed_loads_1; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_1 = _ld_xcpt_valid_T | failed_loads_2; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T_1 | failed_loads_3; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_3 = _ld_xcpt_valid_T_2 | failed_loads_4; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_4 = _ld_xcpt_valid_T_3 | failed_loads_5; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_5 = _ld_xcpt_valid_T_4 | failed_loads_6; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_6 = _ld_xcpt_valid_T_5 | failed_loads_7; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_7 = _ld_xcpt_valid_T_6 | failed_loads_8; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_8 = _ld_xcpt_valid_T_7 | failed_loads_9; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_9 = _ld_xcpt_valid_T_8 | failed_loads_10; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_10 = _ld_xcpt_valid_T_9 | failed_loads_11; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_11 = _ld_xcpt_valid_T_10 | failed_loads_12; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_12 = _ld_xcpt_valid_T_11 | failed_loads_13; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_13 = _ld_xcpt_valid_T_12 | failed_loads_14; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_14 = _ld_xcpt_valid_T_13 | failed_loads_15; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_15 = _ld_xcpt_valid_T_14 | failed_loads_16; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_16 = _ld_xcpt_valid_T_15 | failed_loads_17; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_17 = _ld_xcpt_valid_T_16 | failed_loads_18; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_18 = _ld_xcpt_valid_T_17 | failed_loads_19; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_19 = _ld_xcpt_valid_T_18 | failed_loads_20; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_20 = _ld_xcpt_valid_T_19 | failed_loads_21; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_valid_T_21 = _ld_xcpt_valid_T_20 | failed_loads_22; // @[lsu.scala:1054:34, :1239:44] wire ld_xcpt_valid = _ld_xcpt_valid_T_21 | failed_loads_23; // @[lsu.scala:1054:34, :1239:44] wire _ld_xcpt_uop_T = l_idx > 6'h17; // @[Mux.scala:50:70] wire [6:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 7'h18; // @[Mux.scala:50:70] wire [5:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[5:0]; // @[lsu.scala:1240:63] wire [5:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[Mux.scala:50:70] wire [4:0] _ld_xcpt_uop_T_4 = _ld_xcpt_uop_T_3[4:0]; // @[lsu.scala:1240:30] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:363:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:363:{52,58,64}] wire _use_mem_xcpt_T_3 = _GEN_133[_ld_xcpt_uop_T_4] < io_core_rob_head_idx_0; // @[util.scala:363:{52,78}] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:363:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:363:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1239:44, :1242:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 | _use_mem_xcpt_T_6; // @[lsu.scala:1242:{38,115,118}] wire [6:0] xcpt_uop_uopc = use_mem_xcpt ? mem_xcpt_uop_uopc : _GEN_101[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : _GEN_102[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : _GEN_103[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : _GEN_104[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : _GEN_105[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_iq_type = use_mem_xcpt ? mem_xcpt_uop_iq_type : _GEN_106[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [9:0] xcpt_uop_fu_code = use_mem_xcpt ? mem_xcpt_uop_fu_code : _GEN_107[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_ctrl_br_type = use_mem_xcpt ? mem_xcpt_uop_ctrl_br_type : _GEN_108[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_ctrl_op1_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op1_sel : _GEN_109[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_op2_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_op2_sel : _GEN_110[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_imm_sel = use_mem_xcpt ? mem_xcpt_uop_ctrl_imm_sel : _GEN_111[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ctrl_op_fcn = use_mem_xcpt ? mem_xcpt_uop_ctrl_op_fcn : _GEN_112[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_ctrl_fcn_dw : _GEN_113[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [2:0] xcpt_uop_ctrl_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_ctrl_csr_cmd : _GEN_114[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_load = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_load : _GEN_115[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_sta = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_sta : _GEN_116[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ctrl_is_std = use_mem_xcpt ? mem_xcpt_uop_ctrl_is_std : _GEN_117[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_iw_state = use_mem_xcpt ? mem_xcpt_uop_iw_state : _GEN_118[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p1_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p1_poisoned : _GEN_119[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_iw_p2_poisoned = use_mem_xcpt ? mem_xcpt_uop_iw_p2_poisoned : _GEN_120[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_br = use_mem_xcpt ? mem_xcpt_uop_is_br : _GEN_121[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jalr = use_mem_xcpt ? mem_xcpt_uop_is_jalr : _GEN_122[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_jal = use_mem_xcpt ? mem_xcpt_uop_is_jal : _GEN_123[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : _GEN_124[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [15:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : _GEN_125[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : _GEN_126[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : _GEN_127[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : _GEN_128[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : _GEN_129[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : _GEN_130[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : _GEN_131[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [11:0] xcpt_uop_csr_addr = use_mem_xcpt ? mem_xcpt_uop_csr_addr : _GEN_132[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [6:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : _GEN_133[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : _GEN_134[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : _GEN_135[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : _GEN_136[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : _GEN_137[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : _GEN_138[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : _GEN_139[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : _GEN_140[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : 5'h0; // @[lsu.scala:360:29, :1242:115, :1244:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : _GEN_141[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : _GEN_142[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : _GEN_143[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ppred_busy = use_mem_xcpt & mem_xcpt_uop_ppred_busy; // @[lsu.scala:360:29, :1242:115, :1244:21] wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : _GEN_144[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : _GEN_145[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : _GEN_146[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bypassable = use_mem_xcpt ? mem_xcpt_uop_bypassable : _GEN_147[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : _GEN_148[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : _GEN_149[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : _GEN_150[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : _GEN_151[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : _GEN_152[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : _GEN_153[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : _GEN_154[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : _GEN_155[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : _GEN_156[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : _GEN_157[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : _GEN_158[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : _GEN_159[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : _GEN_160[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : _GEN_161[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : _GEN_162[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : _GEN_163[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_ldst_val = use_mem_xcpt ? mem_xcpt_uop_ldst_val : _GEN_164[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : _GEN_165[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : _GEN_166[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : _GEN_167[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : _GEN_168[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : _GEN_169[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_fp_single = use_mem_xcpt ? mem_xcpt_uop_fp_single : _GEN_170[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : _GEN_171[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : _GEN_172[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : _GEN_173[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : _GEN_174[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : _GEN_175[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : _GEN_176[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire [1:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : _GEN_177[_ld_xcpt_uop_T_4]; // @[util.scala:363:52] wire _r_xcpt_valid_T = ld_xcpt_valid | mem_xcpt_valid; // @[lsu.scala:358:29, :1239:44, :1246:34] wire _r_xcpt_valid_T_1 = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1247:20] wire _r_xcpt_valid_T_2 = _r_xcpt_valid_T & _r_xcpt_valid_T_1; // @[lsu.scala:1246:{34,53}, :1247:20] wire [15:0] _r_xcpt_valid_T_3 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:118:51] wire _r_xcpt_valid_T_4 = |_r_xcpt_valid_T_3; // @[util.scala:118:{51,59}] wire _r_xcpt_valid_T_5 = ~_r_xcpt_valid_T_4; // @[util.scala:118:59] wire _r_xcpt_valid_T_6 = _r_xcpt_valid_T_2 & _r_xcpt_valid_T_5; // @[lsu.scala:1246:53, :1247:39, :1248:20] wire [15:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:85:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:359:29, :1242:115, :1251:28] wire _io_core_lxcpt_valid_T = ~io_core_exception_0; // @[lsu.scala:201:7, :670:22, :1254:42] wire _io_core_lxcpt_valid_T_1 = r_xcpt_valid & _io_core_lxcpt_valid_T; // @[lsu.scala:1236:29, :1254:{39,42}] wire [15:0] _io_core_lxcpt_valid_T_2 = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:118:51] wire _io_core_lxcpt_valid_T_3 = |_io_core_lxcpt_valid_T_2; // @[util.scala:118:{51,59}] wire _io_core_lxcpt_valid_T_4 = ~_io_core_lxcpt_valid_T_3; // @[util.scala:118:59] assign _io_core_lxcpt_valid_T_5 = _io_core_lxcpt_valid_T_1 & _io_core_lxcpt_valid_T_4; // @[lsu.scala:1254:{39,61,64}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_5; // @[lsu.scala:201:7, :1254:61] wire _io_core_spec_ld_wakeup_0_valid_T_1 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:909:37, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_2 = _io_core_spec_ld_wakeup_0_valid_T & _io_core_spec_ld_wakeup_0_valid_T_1; // @[lsu.scala:1259:69, :1260:69, :1261:40] wire _io_core_spec_ld_wakeup_0_valid_T_3 = |mem_incoming_uop_0_pdst; // @[lsu.scala:909:37, :1262:65] assign _io_core_spec_ld_wakeup_0_valid_T_4 = _io_core_spec_ld_wakeup_0_valid_T_2 & _io_core_spec_ld_wakeup_0_valid_T_3; // @[lsu.scala:1260:69, :1261:69, :1262:65] assign io_core_spec_ld_wakeup_0_valid_0 = _io_core_spec_ld_wakeup_0_valid_T_4; // @[lsu.scala:201:7, :1261:69] wire dmem_resp_fired_0; // @[lsu.scala:1282:33] wire _GEN_1073 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:201:7, :1290:7] wire _GEN_1074 = _GEN_1073 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:201:7, :1290:7, :1294:7, :1295:15] wire _GEN_1075 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h0; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1076 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h1; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1077 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h2; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1078 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h3; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1079 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h4; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1080 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h5; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1081 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h6; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1082 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h7; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1083 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h8; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1084 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h9; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1085 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hA; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1086 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hB; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1087 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hC; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1088 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hD; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1089 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hE; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1090 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'hF; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1091 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h10; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1092 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h11; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1093 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h12; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1094 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h13; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1095 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h14; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1096 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h15; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1097 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h16; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] wire _GEN_1098 = io_dmem_nack_0_bits_uop_uses_ldq_0 & io_dmem_nack_0_bits_uop_ldq_idx_0 == 5'h17; // @[lsu.scala:201:7, :1175:30, :1294:7, :1296:62] assign nacking_loads_0 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1075; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_1 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1076; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_2 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1077; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_3 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1078; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_4 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1079; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_5 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1080; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_6 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1081; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_7 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1082; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_8 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1083; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_9 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1084; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_10 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1085; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_11 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1086; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_12 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1087; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_13 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1088; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_14 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1089; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_15 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1090; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_16 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1091; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_17 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1092; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_18 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1093; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_19 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1094; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_20 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1095; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_21 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1096; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_22 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1097; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] assign nacking_loads_23 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0 & _GEN_1098; // @[lsu.scala:201:7, :1055:34, :1175:30, :1287:5, :1290:7, :1294:7, :1296:62] wire _GEN_1099 = io_dmem_resp_0_valid_0 & io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:201:7, :1311:7] wire send_iresp = _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h0; // @[lsu.scala:201:7, :263:49, :1314:58] wire send_fresp = _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] == 2'h1; // @[lsu.scala:201:7, :263:49, :1314:58, :1315:58] wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 | io_core_exe_0_fresp_valid_0; // @[lsu.scala:201:7, :1327:72] assign dmem_resp_fired_0 = io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 | io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0); // @[lsu.scala:201:7, :1282:33, :1309:5, :1311:7, :1325:28, :1331:7, :1334:48, :1335:30] wire _T_1698 = dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1346:30] wire _T_1700 = ~dmem_resp_fired_0 & wb_forward_valid_0; // @[lsu.scala:1065:36, :1282:33, :1350:{18,38}] wire [4:0] _forward_uop_T_1 = _forward_uop_T; wire [1:0] size_1 = _GEN_149[_forward_uop_T_1]; // @[AMOALU.scala:11:18] wire [15:0] _live_T = io_core_brupdate_b1_mispredict_mask_0 & _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] wire _live_T_1 = |_live_T; // @[util.scala:118:{51,59}] wire live = ~_live_T_1; // @[util.scala:118:59] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_52[wb_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire _GEN_1100 = _GEN_86[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [63:0] _GEN_1101 = _GEN_87[wb_forward_stq_idx_0]; // @[AMOALU.scala:12:8] wire [3:0][63:0] _GEN_1102 = {{_GEN_1101}, {{2{_GEN_1101[31:0]}}}, {{2{{2{_GEN_1101[15:0]}}}}}, {{2{{2{{2{_GEN_1101[7:0]}}}}}}}}; // @[AMOALU.scala:12:8, :29:{13,19,32,69}] wire _io_core_exe_0_iresp_valid_T = _GEN_165[_forward_uop_T_1] == 2'h0; // @[util.scala:118:51] wire _io_core_exe_0_iresp_valid_T_1 = _io_core_exe_0_iresp_valid_T & _GEN_1100; // @[AMOALU.scala:12:8] wire _io_core_exe_0_iresp_valid_T_2 = _io_core_exe_0_iresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1365:{72,86}] wire _GEN_1103 = _T_1698 | ~_T_1700; // @[lsu.scala:1309:5, :1346:30, :1347:5, :1350:38, :1351:5] assign io_core_exe_0_iresp_valid_0 = _GEN_1103 ? io_dmem_resp_0_valid_0 & (io_dmem_resp_0_bits_uop_uses_ldq_0 ? send_iresp : io_dmem_resp_0_bits_uop_uses_stq_0 & io_dmem_resp_0_bits_uop_is_amo_0) : _io_core_exe_0_iresp_valid_T_2; // @[lsu.scala:201:7, :1276:32, :1309:5, :1311:7, :1314:58, :1319:40, :1331:7, :1334:48, :1347:5, :1351:5, :1365:86] wire _io_core_exe_0_fresp_valid_T = _GEN_165[_forward_uop_T_1] == 2'h1; // @[util.scala:118:51] wire _io_core_exe_0_fresp_valid_T_1 = _io_core_exe_0_fresp_valid_T & _GEN_1100; // @[AMOALU.scala:12:8] wire _io_core_exe_0_fresp_valid_T_2 = _io_core_exe_0_fresp_valid_T_1 & live; // @[lsu.scala:1356:25, :1366:{72,86}] assign io_core_exe_0_fresp_valid_0 = _GEN_1103 ? _GEN_1099 & send_fresp : _io_core_exe_0_fresp_valid_T_2; // @[lsu.scala:201:7, :1278:32, :1309:5, :1311:7, :1315:58, :1321:40, :1347:5, :1351:5, :1366:86] assign io_core_exe_0_iresp_bits_uop_uopc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_1[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_2[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_3[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_rvc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_4[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_pc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_5[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iq_type_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_6[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fu_code_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_7[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_br_type_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_8[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_9[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_10[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_11[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_12[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_13[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_14[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_load_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_15[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_sta_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_16[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ctrl_is_std_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_17[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_state_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_18[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_19[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_20[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_br_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_21[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jalr_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_22[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_jal_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_23[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sfb_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_24[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_mask_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_25[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_br_tag_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_26[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ftq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_27[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_edge_inst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_28[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pc_lob_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_29[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_taken_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_30[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_imm_packed_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_31[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_csr_addr_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_32[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rob_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_33[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_34[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_stq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_35[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_rxq_idx_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_36[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_pdst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_39[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_40[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_0 = ~_GEN_1103 | io_dmem_resp_0_bits_uop_uses_ldq_0 ? 5'h0 : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :1309:5, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_prs1_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_42[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs2_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_43[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_142[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_prs3_busy_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_44[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ppred_busy_0 = _GEN_1103 & ~io_dmem_resp_0_bits_uop_uses_ldq_0 & _GEN_45[io_dmem_resp_0_bits_uop_stq_idx_0]; // @[lsu.scala:201:7, :222:42, :767:39, :1309:5, :1311:7, :1317:40, :1331:7, :1333:62, :1347:5, :1351:5] assign io_core_exe_0_iresp_bits_uop_stale_pdst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_46[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exception_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_47[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_exc_cause_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_49[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bypassable_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_50[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_cmd_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_51[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_mem_size_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_52[io_dmem_resp_0_bits_uop_stq_idx_0]) : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_iresp_bits_uop_mem_signed_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_53[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fence_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_54[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_fencei_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_56[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_amo_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_57[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_ldq_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_59[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_uses_stq_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_60[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_is_unique_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_62[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_flush_on_commit_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_63[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_is_rs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_65[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_66[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_67[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs3_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_68[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_ldst_val_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_69[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_dst_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_70[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs1_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_71[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_lrs2_rtype_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_72[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_frs3_en_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_73[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_val_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_fp_single_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_75[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_pf_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_171[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_76[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_171[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ae_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_172[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_77[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_172[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_xcpt_ma_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_173[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_78[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_173[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_debug_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_174[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_79[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_174[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_bp_xcpt_if_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_175[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_80[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_175[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_fsrc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_176[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_81[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_176[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_iresp_bits_uop_debug_tsrc_0 = _GEN_1103 ? (io_dmem_resp_0_bits_uop_uses_ldq_0 ? _GEN_177[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_82[io_dmem_resp_0_bits_uop_stq_idx_0]) : _GEN_177[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uopc_0 = _GEN_1103 ? _GEN_101[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_101[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_inst_0 = _GEN_1103 ? _GEN_102[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_102[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_inst_0 = _GEN_1103 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_103[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_rvc_0 = _GEN_1103 ? _GEN_104[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_104[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_pc_0 = _GEN_1103 ? _GEN_105[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_105[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iq_type_0 = _GEN_1103 ? _GEN_106[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_106[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fu_code_0 = _GEN_1103 ? _GEN_107[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_107[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_br_type_0 = _GEN_1103 ? _GEN_108[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_108[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = _GEN_1103 ? _GEN_109[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_109[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = _GEN_1103 ? _GEN_110[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_110[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = _GEN_1103 ? _GEN_111[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_111[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = _GEN_1103 ? _GEN_112[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_112[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = _GEN_1103 ? _GEN_113[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_113[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = _GEN_1103 ? _GEN_114[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_114[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_load_0 = _GEN_1103 ? _GEN_115[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_115[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_sta_0 = _GEN_1103 ? _GEN_116[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_116[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ctrl_is_std_0 = _GEN_1103 ? _GEN_117[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_117[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_state_0 = _GEN_1103 ? _GEN_118[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_118[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = _GEN_1103 ? _GEN_119[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_119[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = _GEN_1103 ? _GEN_120[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_120[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_br_0 = _GEN_1103 ? _GEN_121[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_121[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jalr_0 = _GEN_1103 ? _GEN_122[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_122[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_jal_0 = _GEN_1103 ? _GEN_123[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_123[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sfb_0 = _GEN_1103 ? _GEN_124[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_124[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_mask_0 = _GEN_1103 ? _GEN_125[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_125[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_br_tag_0 = _GEN_1103 ? _GEN_126[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_126[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ftq_idx_0 = _GEN_1103 ? _GEN_127[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_127[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_edge_inst_0 = _GEN_1103 ? _GEN_128[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_128[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pc_lob_0 = _GEN_1103 ? _GEN_129[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_129[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_taken_0 = _GEN_1103 ? _GEN_130[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_130[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_imm_packed_0 = _GEN_1103 ? _GEN_131[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_131[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_csr_addr_0 = _GEN_1103 ? _GEN_132[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_132[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rob_idx_0 = _GEN_1103 ? _GEN_133[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_133[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldq_idx_0 = _GEN_1103 ? _GEN_134[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_134[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stq_idx_0 = _GEN_1103 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_135[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_rxq_idx_0 = _GEN_1103 ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_136[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_pdst_0 = _GEN_1103 ? _GEN_137[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_137[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_0 = _GEN_1103 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_138[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_0 = _GEN_1103 ? _GEN_139[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_139[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_0 = _GEN_1103 ? _GEN_140[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_140[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs1_busy_0 = _GEN_1103 ? _GEN_141[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_141[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs2_busy_0 = _GEN_1103 ? _GEN_142[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_142[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_prs3_busy_0 = _GEN_1103 ? _GEN_143[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_143[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_stale_pdst_0 = _GEN_1103 ? _GEN_144[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_144[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exception_0 = _GEN_1103 ? _GEN_145[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_145[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_exc_cause_0 = _GEN_1103 ? _GEN_146[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_146[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bypassable_0 = _GEN_1103 ? _GEN_147[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_147[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_cmd_0 = _GEN_1103 ? _GEN_148[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_148[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_mem_size_0 = _GEN_1103 ? _GEN_149[io_dmem_resp_0_bits_uop_ldq_idx_0] : size_1; // @[AMOALU.scala:11:18] assign io_core_exe_0_fresp_bits_uop_mem_signed_0 = _GEN_1103 ? _GEN_150[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_150[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fence_0 = _GEN_1103 ? _GEN_151[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_151[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_fencei_0 = _GEN_1103 ? _GEN_152[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_152[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_amo_0 = _GEN_1103 ? _GEN_153[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_153[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_ldq_0 = _GEN_1103 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_154[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_uses_stq_0 = _GEN_1103 ? _GEN_155[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_155[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = _GEN_1103 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_156[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_is_unique_0 = _GEN_1103 ? _GEN_157[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_157[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_flush_on_commit_0 = _GEN_1103 ? _GEN_158[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_158[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_is_rs1_0 = _GEN_1103 ? _GEN_159[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_159[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_0 = _GEN_1103 ? _GEN_160[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_160[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_0 = _GEN_1103 ? _GEN_161[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_161[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_0 = _GEN_1103 ? _GEN_162[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_162[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs3_0 = _GEN_1103 ? _GEN_163[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_163[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_ldst_val_0 = _GEN_1103 ? _GEN_164[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_164[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_dst_rtype_0 = _GEN_1103 ? _GEN_165[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_165[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs1_rtype_0 = _GEN_1103 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_166[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_lrs2_rtype_0 = _GEN_1103 ? _GEN_167[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_167[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_frs3_en_0 = _GEN_1103 ? _GEN_168[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_168[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_val_0 = _GEN_1103 ? _GEN_169[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_169[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_fp_single_0 = _GEN_1103 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_170[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_pf_if_0 = _GEN_1103 ? _GEN_171[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_171[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ae_if_0 = _GEN_1103 ? _GEN_172[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_172[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_xcpt_ma_if_0 = _GEN_1103 ? _GEN_173[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_173[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_debug_if_0 = _GEN_1103 ? _GEN_174[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_174[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_bp_xcpt_if_0 = _GEN_1103 ? _GEN_175[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_175[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_fsrc_0 = _GEN_1103 ? _GEN_176[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_176[_forward_uop_T_1]; // @[util.scala:118:51] assign io_core_exe_0_fresp_bits_uop_debug_tsrc_0 = _GEN_1103 ? _GEN_177[io_dmem_resp_0_bits_uop_ldq_idx_0] : _GEN_177[_forward_uop_T_1]; // @[util.scala:118:51] wire _io_core_exe_0_iresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T = wb_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_iresp_bits_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _io_core_exe_0_fresp_bits_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_1 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_bits_debug_wb_data_T_5 = _GEN_1102[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _io_core_exe_0_iresp_bits_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _io_core_exe_0_fresp_bits_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_bits_debug_wb_data_shifted_T_2 = _GEN_1102[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] io_core_exe_0_iresp_bits_data_shifted = _io_core_exe_0_iresp_bits_data_shifted_T ? _io_core_exe_0_iresp_bits_data_shifted_T_1 : _io_core_exe_0_iresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = io_core_exe_0_iresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_1104 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T = _GEN_1104; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T = _GEN_1104; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T = _GEN_1104; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_1 = _io_core_exe_0_iresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_2 = io_core_exe_0_iresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_3 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_4 = {32{_io_core_exe_0_iresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_iresp_bits_data_T_6 = _io_core_exe_0_iresp_bits_data_T_1 ? _io_core_exe_0_iresp_bits_data_T_4 : _io_core_exe_0_iresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_7 = {_io_core_exe_0_iresp_bits_data_T_6, io_core_exe_0_iresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_3 = wb_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_4 = _io_core_exe_0_iresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_iresp_bits_data_shifted_T_5 = _io_core_exe_0_iresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_iresp_bits_data_shifted_1 = _io_core_exe_0_iresp_bits_data_shifted_T_3 ? _io_core_exe_0_iresp_bits_data_shifted_T_4 : _io_core_exe_0_iresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = io_core_exe_0_iresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_1105 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_8 = _GEN_1105; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_9 = _io_core_exe_0_iresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_10 = io_core_exe_0_iresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_11 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_12 = {48{_io_core_exe_0_iresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_13 = _io_core_exe_0_iresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_iresp_bits_data_T_14 = _io_core_exe_0_iresp_bits_data_T_9 ? _io_core_exe_0_iresp_bits_data_T_12 : _io_core_exe_0_iresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_15 = {_io_core_exe_0_iresp_bits_data_T_14, io_core_exe_0_iresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_core_exe_0_iresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _io_core_exe_0_fresp_bits_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_bits_debug_wb_data_shifted_T_6 = wb_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_7 = _io_core_exe_0_iresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_iresp_bits_data_shifted_T_8 = _io_core_exe_0_iresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_iresp_bits_data_shifted_2 = _io_core_exe_0_iresp_bits_data_shifted_T_6 ? _io_core_exe_0_iresp_bits_data_shifted_T_7 : _io_core_exe_0_iresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = io_core_exe_0_iresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_1106 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_iresp_bits_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26] wire _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:26] assign _io_core_exe_0_fresp_bits_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26] wire _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_bits_debug_wb_data_T_16 = _GEN_1106; // @[AMOALU.scala:45:26] wire _io_core_exe_0_iresp_bits_data_T_17 = _io_core_exe_0_iresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_iresp_bits_data_T_18 = io_core_exe_0_iresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_iresp_bits_data_T_19 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_iresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_20 = {56{_io_core_exe_0_iresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_21 = _io_core_exe_0_iresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_iresp_bits_data_T_22 = _io_core_exe_0_iresp_bits_data_T_17 ? _io_core_exe_0_iresp_bits_data_T_20 : _io_core_exe_0_iresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_iresp_bits_data_T_23 = {_io_core_exe_0_iresp_bits_data_T_22, io_core_exe_0_iresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_iresp_bits_data_0 = _GEN_1103 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_iresp_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] io_core_exe_0_fresp_bits_data_shifted = _io_core_exe_0_fresp_bits_data_shifted_T ? _io_core_exe_0_fresp_bits_data_shifted_T_1 : _io_core_exe_0_fresp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = io_core_exe_0_fresp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_1 = _io_core_exe_0_fresp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_2 = io_core_exe_0_fresp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_3 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_4 = {32{_io_core_exe_0_fresp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_core_exe_0_fresp_bits_data_T_6 = _io_core_exe_0_fresp_bits_data_T_1 ? _io_core_exe_0_fresp_bits_data_T_4 : _io_core_exe_0_fresp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_7 = {_io_core_exe_0_fresp_bits_data_T_6, io_core_exe_0_fresp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_4 = _io_core_exe_0_fresp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_core_exe_0_fresp_bits_data_shifted_T_5 = _io_core_exe_0_fresp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_core_exe_0_fresp_bits_data_shifted_1 = _io_core_exe_0_fresp_bits_data_shifted_T_3 ? _io_core_exe_0_fresp_bits_data_shifted_T_4 : _io_core_exe_0_fresp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = io_core_exe_0_fresp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_9 = _io_core_exe_0_fresp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_10 = io_core_exe_0_fresp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_11 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_12 = {48{_io_core_exe_0_fresp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_13 = _io_core_exe_0_fresp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_core_exe_0_fresp_bits_data_T_14 = _io_core_exe_0_fresp_bits_data_T_9 ? _io_core_exe_0_fresp_bits_data_T_12 : _io_core_exe_0_fresp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_15 = {_io_core_exe_0_fresp_bits_data_T_14, io_core_exe_0_fresp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_7 = _io_core_exe_0_fresp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_core_exe_0_fresp_bits_data_shifted_T_8 = _io_core_exe_0_fresp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_core_exe_0_fresp_bits_data_shifted_2 = _io_core_exe_0_fresp_bits_data_shifted_T_6 ? _io_core_exe_0_fresp_bits_data_shifted_T_7 : _io_core_exe_0_fresp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = io_core_exe_0_fresp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_core_exe_0_fresp_bits_data_T_17 = _io_core_exe_0_fresp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_core_exe_0_fresp_bits_data_T_18 = io_core_exe_0_fresp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_core_exe_0_fresp_bits_data_T_19 = _GEN_150[_forward_uop_T_1] & _io_core_exe_0_fresp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_20 = {56{_io_core_exe_0_fresp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_21 = _io_core_exe_0_fresp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_core_exe_0_fresp_bits_data_T_22 = _io_core_exe_0_fresp_bits_data_T_17 ? _io_core_exe_0_fresp_bits_data_T_20 : _io_core_exe_0_fresp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_core_exe_0_fresp_bits_data_T_23 = {_io_core_exe_0_fresp_bits_data_T_22, io_core_exe_0_fresp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_core_exe_0_fresp_bits_data_0 = {1'h0, _GEN_1103 ? io_dmem_resp_0_bits_data_0 : _io_core_exe_0_fresp_bits_data_T_23}; // @[AMOALU.scala:45:16] wire [31:0] ldq_bits_debug_wb_data_shifted = _ldq_bits_debug_wb_data_shifted_T ? _ldq_bits_debug_wb_data_shifted_T_1 : _ldq_bits_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_bits_debug_wb_data_zeroed = ldq_bits_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_1 = _ldq_bits_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_2 = ldq_bits_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_3 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_bits_debug_wb_data_T_4 = {32{_ldq_bits_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_bits_debug_wb_data_T_6 = _ldq_bits_debug_wb_data_T_1 ? _ldq_bits_debug_wb_data_T_4 : _ldq_bits_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_7 = {_ldq_bits_debug_wb_data_T_6, ldq_bits_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_4 = _ldq_bits_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_bits_debug_wb_data_shifted_T_5 = _ldq_bits_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_bits_debug_wb_data_shifted_1 = _ldq_bits_debug_wb_data_shifted_T_3 ? _ldq_bits_debug_wb_data_shifted_T_4 : _ldq_bits_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_bits_debug_wb_data_zeroed_1 = ldq_bits_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_9 = _ldq_bits_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_10 = ldq_bits_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_11 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_bits_debug_wb_data_T_12 = {48{_ldq_bits_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_bits_debug_wb_data_T_13 = _ldq_bits_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_bits_debug_wb_data_T_14 = _ldq_bits_debug_wb_data_T_9 ? _ldq_bits_debug_wb_data_T_12 : _ldq_bits_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_15 = {_ldq_bits_debug_wb_data_T_14, ldq_bits_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_7 = _ldq_bits_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_bits_debug_wb_data_shifted_T_8 = _ldq_bits_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_bits_debug_wb_data_shifted_2 = _ldq_bits_debug_wb_data_shifted_T_6 ? _ldq_bits_debug_wb_data_shifted_T_7 : _ldq_bits_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_bits_debug_wb_data_zeroed_2 = ldq_bits_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_bits_debug_wb_data_T_17 = _ldq_bits_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_bits_debug_wb_data_T_18 = ldq_bits_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_bits_debug_wb_data_T_19 = _GEN_150[_forward_uop_T_1] & _ldq_bits_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_bits_debug_wb_data_T_20 = {56{_ldq_bits_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_bits_debug_wb_data_T_21 = _ldq_bits_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_bits_debug_wb_data_T_22 = _ldq_bits_debug_wb_data_T_17 ? _ldq_bits_debug_wb_data_T_20 : _ldq_bits_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_bits_debug_wb_data_T_23 = {_ldq_bits_debug_wb_data_T_22, ldq_bits_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] reg io_core_ld_miss_REG; // @[lsu.scala:1383:37] reg spec_ld_succeed_REG; // @[lsu.scala:1385:13] wire _spec_ld_succeed_T = ~spec_ld_succeed_REG; // @[lsu.scala:1385:{5,13}] reg [4:0] spec_ld_succeed_REG_1; // @[lsu.scala:1387:56] wire _spec_ld_succeed_T_1 = io_core_exe_0_iresp_bits_uop_ldq_idx_0 == spec_ld_succeed_REG_1; // @[lsu.scala:201:7, :1387:{45,56}] wire _spec_ld_succeed_T_2 = io_core_exe_0_iresp_valid_0 & _spec_ld_succeed_T_1; // @[lsu.scala:201:7, :1386:33, :1387:45] wire _spec_ld_succeed_T_3 = _spec_ld_succeed_T | _spec_ld_succeed_T_2; // @[lsu.scala:1385:{5,47}, :1386:33] wire _spec_ld_succeed_WIRE_0 = _spec_ld_succeed_T_3; // @[lsu.scala:263:49, :1385:47] assign io_core_ld_miss_0 = ~_spec_ld_succeed_WIRE_0 & io_core_ld_miss_REG; // @[lsu.scala:201:7, :263:49, :1383:{27,37}, :1390:26, :1391:21] wire st_brkilled_mask_0; // @[lsu.scala:1401:30] wire st_brkilled_mask_1; // @[lsu.scala:1401:30] wire st_brkilled_mask_2; // @[lsu.scala:1401:30] wire st_brkilled_mask_3; // @[lsu.scala:1401:30] wire st_brkilled_mask_4; // @[lsu.scala:1401:30] wire st_brkilled_mask_5; // @[lsu.scala:1401:30] wire st_brkilled_mask_6; // @[lsu.scala:1401:30] wire st_brkilled_mask_7; // @[lsu.scala:1401:30] wire st_brkilled_mask_8; // @[lsu.scala:1401:30] wire st_brkilled_mask_9; // @[lsu.scala:1401:30] wire st_brkilled_mask_10; // @[lsu.scala:1401:30] wire st_brkilled_mask_11; // @[lsu.scala:1401:30] wire st_brkilled_mask_12; // @[lsu.scala:1401:30] wire st_brkilled_mask_13; // @[lsu.scala:1401:30] wire st_brkilled_mask_14; // @[lsu.scala:1401:30] wire st_brkilled_mask_15; // @[lsu.scala:1401:30] wire st_brkilled_mask_16; // @[lsu.scala:1401:30] wire st_brkilled_mask_17; // @[lsu.scala:1401:30] wire st_brkilled_mask_18; // @[lsu.scala:1401:30] wire st_brkilled_mask_19; // @[lsu.scala:1401:30] wire st_brkilled_mask_20; // @[lsu.scala:1401:30] wire st_brkilled_mask_21; // @[lsu.scala:1401:30] wire st_brkilled_mask_22; // @[lsu.scala:1401:30] wire st_brkilled_mask_23; // @[lsu.scala:1401:30] wire [15:0] _stq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_0_bits_uop_br_mask_T_1 = stq_0_bits_uop_br_mask & _stq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1725 = io_core_brupdate_b1_mispredict_mask_0 & stq_0_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_0 = stq_0_valid & (|_T_1725); // @[util.scala:118:{51,59}] wire [15:0] _stq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_1_bits_uop_br_mask_T_1 = stq_1_bits_uop_br_mask & _stq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1735 = io_core_brupdate_b1_mispredict_mask_0 & stq_1_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_1 = stq_1_valid & (|_T_1735); // @[util.scala:118:{51,59}] wire [15:0] _stq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_2_bits_uop_br_mask_T_1 = stq_2_bits_uop_br_mask & _stq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1745 = io_core_brupdate_b1_mispredict_mask_0 & stq_2_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_2 = stq_2_valid & (|_T_1745); // @[util.scala:118:{51,59}] wire [15:0] _stq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_3_bits_uop_br_mask_T_1 = stq_3_bits_uop_br_mask & _stq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1755 = io_core_brupdate_b1_mispredict_mask_0 & stq_3_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_3 = stq_3_valid & (|_T_1755); // @[util.scala:118:{51,59}] wire [15:0] _stq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_4_bits_uop_br_mask_T_1 = stq_4_bits_uop_br_mask & _stq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1765 = io_core_brupdate_b1_mispredict_mask_0 & stq_4_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_4 = stq_4_valid & (|_T_1765); // @[util.scala:118:{51,59}] wire [15:0] _stq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_5_bits_uop_br_mask_T_1 = stq_5_bits_uop_br_mask & _stq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1775 = io_core_brupdate_b1_mispredict_mask_0 & stq_5_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_5 = stq_5_valid & (|_T_1775); // @[util.scala:118:{51,59}] wire [15:0] _stq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_6_bits_uop_br_mask_T_1 = stq_6_bits_uop_br_mask & _stq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1785 = io_core_brupdate_b1_mispredict_mask_0 & stq_6_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_6 = stq_6_valid & (|_T_1785); // @[util.scala:118:{51,59}] wire [15:0] _stq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_7_bits_uop_br_mask_T_1 = stq_7_bits_uop_br_mask & _stq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1795 = io_core_brupdate_b1_mispredict_mask_0 & stq_7_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_7 = stq_7_valid & (|_T_1795); // @[util.scala:118:{51,59}] wire [15:0] _stq_8_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_8_bits_uop_br_mask_T_1 = stq_8_bits_uop_br_mask & _stq_8_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1805 = io_core_brupdate_b1_mispredict_mask_0 & stq_8_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_8 = stq_8_valid & (|_T_1805); // @[util.scala:118:{51,59}] wire [15:0] _stq_9_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_9_bits_uop_br_mask_T_1 = stq_9_bits_uop_br_mask & _stq_9_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1815 = io_core_brupdate_b1_mispredict_mask_0 & stq_9_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_9 = stq_9_valid & (|_T_1815); // @[util.scala:118:{51,59}] wire [15:0] _stq_10_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_10_bits_uop_br_mask_T_1 = stq_10_bits_uop_br_mask & _stq_10_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1825 = io_core_brupdate_b1_mispredict_mask_0 & stq_10_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_10 = stq_10_valid & (|_T_1825); // @[util.scala:118:{51,59}] wire [15:0] _stq_11_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_11_bits_uop_br_mask_T_1 = stq_11_bits_uop_br_mask & _stq_11_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1835 = io_core_brupdate_b1_mispredict_mask_0 & stq_11_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_11 = stq_11_valid & (|_T_1835); // @[util.scala:118:{51,59}] wire [15:0] _stq_12_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_12_bits_uop_br_mask_T_1 = stq_12_bits_uop_br_mask & _stq_12_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1845 = io_core_brupdate_b1_mispredict_mask_0 & stq_12_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_12 = stq_12_valid & (|_T_1845); // @[util.scala:118:{51,59}] wire [15:0] _stq_13_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_13_bits_uop_br_mask_T_1 = stq_13_bits_uop_br_mask & _stq_13_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1855 = io_core_brupdate_b1_mispredict_mask_0 & stq_13_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_13 = stq_13_valid & (|_T_1855); // @[util.scala:118:{51,59}] wire [15:0] _stq_14_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_14_bits_uop_br_mask_T_1 = stq_14_bits_uop_br_mask & _stq_14_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1865 = io_core_brupdate_b1_mispredict_mask_0 & stq_14_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_14 = stq_14_valid & (|_T_1865); // @[util.scala:118:{51,59}] wire [15:0] _stq_15_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_15_bits_uop_br_mask_T_1 = stq_15_bits_uop_br_mask & _stq_15_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1875 = io_core_brupdate_b1_mispredict_mask_0 & stq_15_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_15 = stq_15_valid & (|_T_1875); // @[util.scala:118:{51,59}] wire [15:0] _stq_16_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_16_bits_uop_br_mask_T_1 = stq_16_bits_uop_br_mask & _stq_16_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1885 = io_core_brupdate_b1_mispredict_mask_0 & stq_16_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_16 = stq_16_valid & (|_T_1885); // @[util.scala:118:{51,59}] wire [15:0] _stq_17_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_17_bits_uop_br_mask_T_1 = stq_17_bits_uop_br_mask & _stq_17_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1895 = io_core_brupdate_b1_mispredict_mask_0 & stq_17_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_17 = stq_17_valid & (|_T_1895); // @[util.scala:118:{51,59}] wire [15:0] _stq_18_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_18_bits_uop_br_mask_T_1 = stq_18_bits_uop_br_mask & _stq_18_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1905 = io_core_brupdate_b1_mispredict_mask_0 & stq_18_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_18 = stq_18_valid & (|_T_1905); // @[util.scala:118:{51,59}] wire [15:0] _stq_19_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_19_bits_uop_br_mask_T_1 = stq_19_bits_uop_br_mask & _stq_19_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1915 = io_core_brupdate_b1_mispredict_mask_0 & stq_19_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_19 = stq_19_valid & (|_T_1915); // @[util.scala:118:{51,59}] wire [15:0] _stq_20_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_20_bits_uop_br_mask_T_1 = stq_20_bits_uop_br_mask & _stq_20_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1925 = io_core_brupdate_b1_mispredict_mask_0 & stq_20_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_20 = stq_20_valid & (|_T_1925); // @[util.scala:118:{51,59}] wire [15:0] _stq_21_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_21_bits_uop_br_mask_T_1 = stq_21_bits_uop_br_mask & _stq_21_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1935 = io_core_brupdate_b1_mispredict_mask_0 & stq_21_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_21 = stq_21_valid & (|_T_1935); // @[util.scala:118:{51,59}] wire [15:0] _stq_22_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_22_bits_uop_br_mask_T_1 = stq_22_bits_uop_br_mask & _stq_22_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1945 = io_core_brupdate_b1_mispredict_mask_0 & stq_22_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_22 = stq_22_valid & (|_T_1945); // @[util.scala:118:{51,59}] wire [15:0] _stq_23_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _stq_23_bits_uop_br_mask_T_1 = stq_23_bits_uop_br_mask & _stq_23_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _T_1955 = io_core_brupdate_b1_mispredict_mask_0 & stq_23_bits_uop_br_mask; // @[util.scala:118:51] assign st_brkilled_mask_23 = stq_23_valid & (|_T_1955); // @[util.scala:118:{51,59}] wire [15:0] _ldq_0_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_0_bits_uop_br_mask_T_1 = ldq_0_bits_uop_br_mask & _ldq_0_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_1_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_1_bits_uop_br_mask_T_1 = ldq_1_bits_uop_br_mask & _ldq_1_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_2_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_2_bits_uop_br_mask_T_1 = ldq_2_bits_uop_br_mask & _ldq_2_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_3_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_3_bits_uop_br_mask_T_1 = ldq_3_bits_uop_br_mask & _ldq_3_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_4_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_4_bits_uop_br_mask_T_1 = ldq_4_bits_uop_br_mask & _ldq_4_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_5_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_5_bits_uop_br_mask_T_1 = ldq_5_bits_uop_br_mask & _ldq_5_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_6_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_6_bits_uop_br_mask_T_1 = ldq_6_bits_uop_br_mask & _ldq_6_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_7_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_7_bits_uop_br_mask_T_1 = ldq_7_bits_uop_br_mask & _ldq_7_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_8_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_8_bits_uop_br_mask_T_1 = ldq_8_bits_uop_br_mask & _ldq_8_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_9_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_9_bits_uop_br_mask_T_1 = ldq_9_bits_uop_br_mask & _ldq_9_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_10_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_10_bits_uop_br_mask_T_1 = ldq_10_bits_uop_br_mask & _ldq_10_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_11_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_11_bits_uop_br_mask_T_1 = ldq_11_bits_uop_br_mask & _ldq_11_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_12_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_12_bits_uop_br_mask_T_1 = ldq_12_bits_uop_br_mask & _ldq_12_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_13_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_13_bits_uop_br_mask_T_1 = ldq_13_bits_uop_br_mask & _ldq_13_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_14_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_14_bits_uop_br_mask_T_1 = ldq_14_bits_uop_br_mask & _ldq_14_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_15_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_15_bits_uop_br_mask_T_1 = ldq_15_bits_uop_br_mask & _ldq_15_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_16_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_16_bits_uop_br_mask_T_1 = ldq_16_bits_uop_br_mask & _ldq_16_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_17_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_17_bits_uop_br_mask_T_1 = ldq_17_bits_uop_br_mask & _ldq_17_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_18_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_18_bits_uop_br_mask_T_1 = ldq_18_bits_uop_br_mask & _ldq_18_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_19_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_19_bits_uop_br_mask_T_1 = ldq_19_bits_uop_br_mask & _ldq_19_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_20_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_20_bits_uop_br_mask_T_1 = ldq_20_bits_uop_br_mask & _ldq_20_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_21_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_21_bits_uop_br_mask_T_1 = ldq_21_bits_uop_br_mask & _ldq_21_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_22_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_22_bits_uop_br_mask_T_1 = ldq_22_bits_uop_br_mask & _ldq_22_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire [15:0] _ldq_23_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23] wire [15:0] _ldq_23_bits_uop_br_mask_T_1 = ldq_23_bits_uop_br_mask & _ldq_23_bits_uop_br_mask_T; // @[util.scala:89:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:201:7, :1454:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:201:7, :1455:49] wire [4:0] idx = commit_store ? stq_commit_head : ldq_head; // @[lsu.scala:213:29, :217:29, :1454:49, :1456:18] wire _GEN_1107 = ~commit_store & commit_load; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31] wire _GEN_1108 = _GEN_1107 & ~reset; // @[lsu.scala:1460:31, :1461:14] wire wrap_12 = stq_commit_head == 5'h17; // @[util.scala:205:25] wire [4:0] _T_2025 = wrap_12 ? 5'h0 : stq_commit_head + 5'h1; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _T_2026 = commit_store ? _T_2025 : stq_commit_head; // @[util.scala:206:10] wire wrap_13 = ldq_head == 5'h17; // @[util.scala:205:25] wire [4:0] _T_2029 = wrap_13 ? 5'h0 : ldq_head + 5'h1; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _T_2030 = commit_load ? _T_2029 : ldq_head; // @[util.scala:206:10] wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:201:7, :1454:49] wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:201:7, :1455:49] wire [4:0] idx_1 = commit_store_1 ? _T_2026 : _T_2030; // @[lsu.scala:1454:49, :1456:18, :1485:31, :1489:31] wire _GEN_1109 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31] wire _GEN_1110 = _GEN_1109 & ~reset; // @[lsu.scala:1460:31, :1461:14] wire wrap_14 = _T_2026 == 5'h17; // @[util.scala:205:25] wire [4:0] _T_2041 = wrap_14 ? 5'h0 : _T_2026 + 5'h1; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _T_2042 = commit_store_1 ? _T_2041 : _T_2026; // @[util.scala:206:10] wire wrap_15 = _T_2030 == 5'h17; // @[util.scala:205:25] wire [4:0] _T_2045 = wrap_15 ? 5'h0 : _T_2030 + 5'h1; // @[util.scala:205:25, :206:{10,28}] wire [4:0] _T_2046 = commit_load_1 ? _T_2045 : _T_2030; // @[util.scala:206:10] wire commit_store_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_stq_0; // @[lsu.scala:201:7, :1454:49] wire commit_load_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_ldq_0; // @[lsu.scala:201:7, :1455:49] wire [4:0] idx_2 = commit_store_2 ? _T_2042 : _T_2046; // @[lsu.scala:1454:49, :1456:18, :1485:31, :1489:31] wire _GEN_1111 = ~commit_store_2 & commit_load_2; // @[lsu.scala:1454:49, :1455:49, :1458:5, :1460:31] wire _GEN_1112 = _GEN_1111 & ~reset; // @[lsu.scala:1460:31, :1461:14]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File HufCompressorController.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, HellaCacheArbiter} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.tilelink._ class HufCompressorControllerIO(implicit p: Parameters) extends Bundle { val src_info_in = Flipped(Decoupled(new StreamInfo)) val dst_info_in = Flipped(Decoupled(new DstWithValInfo)) val lit_src_info = Decoupled(new StreamInfo) val lit_dst_info = Decoupled(new DstInfo) val compressed_bytes = Flipped(Decoupled(UInt(64.W))) val hdr_dst_info = Decoupled(new DstInfo) val hdr_writes = Decoupled(new WriterBundle) val jt_dst_info = Decoupled(new DstInfo) val jt_writes = Decoupled(new WriterBundle) val weight_dst_info = Decoupled(new DstInfo) val weight_bytes = Flipped(Decoupled(UInt(64.W))) val header_size_info = Flipped(Decoupled(UInt(8.W))) val total_write_bytes = Decoupled(UInt(64.W)) val total_write_bytes2 = Decoupled(UInt(64.W)) val init_dictionary = Decoupled(Bool()) val bufs_completed = Output(UInt(64.W)) } // write header when # of io.compressed_bytes.fire === stream_cnt - 1.U & set end_of_message class HufCompressorController(val cmd_que_depth: Int)(implicit p: Parameters) extends Module { val io = IO(new HufCompressorControllerIO) // size_t const lhSize = 3 + (srcSize >= 1 KB) + (srcSize >= 16 KB); // U32 singleStream = srcSize < 256; // case 3: /* 2 - 2 - 10 - 10 */ // { U32 const lhc = hType + ((!singleStream) << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<14); // MEM_writeLE24(ostart, lhc); // break; // } // case 4: /* 2 - 2 - 14 - 14 */ // { U32 const lhc = hType + (2 << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<18); // MEM_writeLE32(ostart, lhc); // break; // } // case 5: /* 2 - 2 - 18 - 18 */ // { U32 const lhc = hType + (3 << 2) + ((U32)srcSize<<4) + ((U32)cLitSize<<22); // MEM_writeLE32(ostart, lhc); // ostart[4] = (BYTE)(cLitSize >> 10); // break; // } val sSendWeightDst = 0.U val sReceiveWrittenWeightBytes = 1.U val sKickoffEncoder = 2.U val sWriteJumpTable = 3.U val sWriteHeader = 4.U val hufCompressState = RegInit(0.U(3.W)) val KB = 1024 val srcSize = io.src_info_in.bits.isize val singleStream = srcSize < 256.U val written_weight_bytes = RegInit(0.U(64.W)) val clitSize = RegInit(0.U(64.W)) val hType = 2.U(2.W) // FIXME : Currently ignore rle & raw for now val totCompBytes = written_weight_bytes + Mux(singleStream, 0.U, 6.U) + clitSize // There are cases when (weights + jump table + compressed literals) > (src file size) happens. // In software, this is considered as a raw block by some heuristics, but it would be inefficient // to do something like compress -> check -> rollback. Hence, we just use the compressed results // with some modifications from the software. val lhSizeSrc = 3.U +& Mux(srcSize >= (1*KB).U, 1.U, 0.U) +& Mux(srcSize >= (16*KB).U, 1.U, 0.U) val lhSizeComp = 3.U +& Mux(totCompBytes >= (1*KB).U, 1.U, 0.U) +& Mux(totCompBytes >= (16*KB).U, 1.U, 0.U) val lhSize = Mux(totCompBytes < srcSize, lhSizeSrc, lhSizeComp) val lhc = WireInit(0.U(42.W)) when (lhSize === 3.U) { lhc := hType + Mux(singleStream, 0.U, (1 << 2).U) + (srcSize << 4.U) + (totCompBytes << 14.U) } .elsewhen (lhSize === 4.U) { lhc := hType + (2 << 2).U + (srcSize << 4.U) + (totCompBytes << 18.U) } .elsewhen (lhSize === 5.U) { lhc := hType + (3 << 2).U + (srcSize << 4.U) + (totCompBytes << 22.U) } val completed_streams = RegInit(0.U(3.W)) val num_streams = Mux(singleStream, 1.U, 4.U) val jump_table = RegInit(VecInit(Seq.fill(3)(0.U(16.W)))) val jump_table_concat = Cat(jump_table(2), jump_table(1), jump_table(0)) val segment_size = (srcSize + 3.U) >> 2.U val last_segment_size = srcSize - (segment_size * 3.U) val compressed_bytes_q = Module(new Queue(UInt(64.W), 4)) compressed_bytes_q.io.enq <> io.compressed_bytes when (io.compressed_bytes.fire) { completed_streams := completed_streams + 1.U clitSize := clitSize + io.compressed_bytes.bits jump_table(completed_streams) := io.compressed_bytes.bits CompressAccelLogger.logInfo("HUF_CONTROL_COMPRESSEDBYTES_FIRE\n") CompressAccelLogger.logInfo("completed_streams: %d, cBytes: %d\n", completed_streams, io.compressed_bytes.bits) } val weight_dst_fire = DecoupledHelper( io.src_info_in.valid, io.dst_info_in.valid, hufCompressState === sSendWeightDst) io.weight_dst_info.valid := weight_dst_fire.fire io.weight_dst_info.bits.op := io.dst_info_in.bits.op + lhSize + 1.U // weight compressor does not write the first byte(size of huf tree info) io.weight_dst_info.bits.cmpflag := 0.U when (weight_dst_fire.fire) { hufCompressState := sReceiveWrittenWeightBytes } io.weight_bytes.ready := (hufCompressState === sReceiveWrittenWeightBytes) when (io.weight_bytes.fire) { written_weight_bytes := io.weight_bytes.bits hufCompressState := sKickoffEncoder CompressAccelLogger.logInfo("huf_written_weight_bytes: %d\n", io.weight_bytes.bits) } val lit_src_info_q = Module(new Queue(new StreamInfo, 4)) val lit_dst_info_q = Module(new Queue(new DstInfo, 4)) io.lit_src_info <> lit_src_info_q.io.deq io.lit_dst_info <> lit_dst_info_q.io.deq val first_stream = RegInit(true.B) val kickoff_encoder = first_stream || compressed_bytes_q.io.deq.valid val kickoff_encoder_fire = DecoupledHelper( io.src_info_in.valid, io.dst_info_in.valid, lit_src_info_q.io.enq.ready, lit_dst_info_q.io.enq.ready, // io.lit_dst_info.ready, // io.lit_src_info.ready, kickoff_encoder, hufCompressState === sKickoffEncoder) compressed_bytes_q.io.deq.ready := kickoff_encoder_fire.fire(kickoff_encoder) val h_w_j_bytes = lhSize + written_weight_bytes + Mux(singleStream, 0.U, 6.U) lit_dst_info_q.io.enq.bits.op := io.dst_info_in.bits.op + h_w_j_bytes + clitSize lit_dst_info_q.io.enq.bits.cmpflag := 0.U lit_dst_info_q.io.enq.valid := kickoff_encoder_fire.fire(lit_dst_info_q.io.enq.ready, completed_streams < num_streams) lit_src_info_q.io.enq.bits.ip := io.src_info_in.bits.ip + completed_streams * segment_size lit_src_info_q.io.enq.bits.isize := Mux(!singleStream, Mux(completed_streams === 3.U, last_segment_size, segment_size), srcSize) lit_src_info_q.io.enq.valid := kickoff_encoder_fire.fire(lit_src_info_q.io.enq.ready, completed_streams < num_streams) // io.lit_dst_info.bits.op := io.dst_info_in.bits.op + h_w_j_bytes + clitSize // io.lit_dst_info.bits.cmpflag := 0.U // io.lit_dst_info.valid := kickoff_encoder_fire.fire(io.lit_dst_info.ready, completed_streams < num_streams) // io.lit_src_info.bits.ip := io.src_info_in.bits.ip + completed_streams * segment_size // io.lit_src_info.bits.isize := Mux(!singleStream, Mux(completed_streams === 3.U, last_segment_size, segment_size), // srcSize) // io.lit_src_info.valid := kickoff_encoder_fire.fire(io.lit_src_info.ready, completed_streams < num_streams) when (kickoff_encoder_fire.fire && first_stream) { first_stream := false.B } val last_kickoff_done = (completed_streams === num_streams) when (kickoff_encoder_fire.fire(lit_src_info_q.io.enq.ready) && last_kickoff_done) { hufCompressState := sWriteJumpTable CompressAccelLogger.logInfo("HUF_CONTROL_LAST_COMPRESS_BYTES_RECEIVED\n") } when (kickoff_encoder_fire.fire && !last_kickoff_done) { CompressAccelLogger.logInfo("HUF_CONTROL_KICKOFF_ENCODER\n") CompressAccelLogger.logInfo("h_w_j_bytes: %d\n", h_w_j_bytes) CompressAccelLogger.logInfo("lit_dst_info.op: 0x%x\n", io.lit_dst_info.bits.op) CompressAccelLogger.logInfo("lit_src_info.ip: 0x%x\n", io.lit_src_info.bits.ip) CompressAccelLogger.logInfo("lit_src_info.isize: %d\n", io.lit_src_info.bits.isize) CompressAccelLogger.logInfo("completed_streams: %d\n", completed_streams) CompressAccelLogger.logInfo("first_stream: %d\n", first_stream) } val write_jump_table_fire = DecoupledHelper( io.src_info_in.valid, io.dst_info_in.valid, io.jt_dst_info.ready, io.jt_writes.ready, hufCompressState === sWriteJumpTable) io.jt_dst_info.valid := write_jump_table_fire.fire(io.jt_dst_info.ready, !singleStream) io.jt_dst_info.bits.op := io.dst_info_in.bits.op + lhSize + written_weight_bytes io.jt_dst_info.bits.cmpflag := 0.U io.jt_writes.valid := write_jump_table_fire.fire(io.jt_writes.ready, !singleStream) io.jt_writes.bits.data := jump_table_concat io.jt_writes.bits.validbytes := 6.U io.jt_writes.bits.end_of_message := true.B when (write_jump_table_fire.fire) { hufCompressState := sWriteHeader when (!singleStream) { CompressAccelLogger.logInfo("jump_table: 0x%x\n", jump_table_concat) CompressAccelLogger.logInfo("jump_table0: %d\n", jump_table(0)) CompressAccelLogger.logInfo("jump_table1: %d\n", jump_table(1)) CompressAccelLogger.logInfo("jump_table2: %d\n", jump_table(2)) } } val header_size_info_q = Module(new Queue(UInt(8.W), 4)) header_size_info_q.io.enq <> io.header_size_info val write_header_fire = DecoupledHelper( io.src_info_in.valid, io.dst_info_in.valid, io.hdr_dst_info.ready, io.hdr_writes.ready, header_size_info_q.io.deq.valid, hufCompressState === sWriteHeader) when (hufCompressState === sWriteHeader) { CompressAccelLogger.logInfo("HUF_CONTROL_sWriteHeader\n") CompressAccelLogger.logInfo("io.src_info_in.valid: %d\n", io.src_info_in.valid) CompressAccelLogger.logInfo("io.dst_info_in.valid: %d\n", io.dst_info_in.valid) CompressAccelLogger.logInfo("io.hdr_dst_info.ready: %d\n", io.hdr_dst_info.ready) CompressAccelLogger.logInfo("io.hdr_writes.ready: %d\n", io.hdr_writes.ready) CompressAccelLogger.logInfo("header_size_info_q.io.deq.valid: %d\n", header_size_info_q.io.deq.valid) CompressAccelLogger.logInfo("io.total_write_bytes.ready: %d\n", io.total_write_bytes.ready) } io.hdr_dst_info.valid := write_header_fire.fire(io.hdr_dst_info.ready) io.hdr_dst_info.bits.cmpflag := io.dst_info_in.bits.cmpflag io.hdr_dst_info.bits.op := io.dst_info_in.bits.op header_size_info_q.io.deq.ready := write_header_fire.fire(header_size_info_q.io.deq.valid) val lhSize_4 = WireInit(0.U(4.W)) lhSize_4 := lhSize val header_with_size = lhc | (header_size_info_q.io.deq.bits << (lhSize_4 << 3.U)) io.hdr_writes.valid := write_header_fire.fire(io.hdr_writes.ready) io.hdr_writes.bits.data := header_with_size io.hdr_writes.bits.validbytes := lhSize +& 1.U io.hdr_writes.bits.end_of_message := true.B val bufs_completed = RegInit(0.U(64.W)) io.bufs_completed := bufs_completed val write_header_fired = RegInit(false.B) when (write_header_fire.fire) { write_header_fired := true.B CompressAccelLogger.logInfo("HUF_CONTROL_WRITE_HEADER\n") CompressAccelLogger.logInfo("header: 0x%x\n", lhc) CompressAccelLogger.logInfo("singleStream: %d\n", singleStream) CompressAccelLogger.logInfo("headerBytes: %d\n", lhSize) CompressAccelLogger.logInfo("header_size_info_q.io.deq.bits: %d\n", header_size_info_q.io.deq.bits) CompressAccelLogger.logInfo("io.hdr_writes.bits.data: 0x%x\n", io.hdr_writes.bits.data) CompressAccelLogger.logInfo("io.hdr_writes.bits.validbytes: 0x%x\n", io.hdr_writes.bits.validbytes) } val total_write_bytes_fire = DecoupledHelper( io.total_write_bytes.ready, io.total_write_bytes2.ready, io.init_dictionary.ready, io.src_info_in.valid, io.dst_info_in.valid, write_header_fired) io.total_write_bytes.valid := total_write_bytes_fire.fire(io.total_write_bytes.ready) io.total_write_bytes.bits := h_w_j_bytes + clitSize io.total_write_bytes2.valid := total_write_bytes_fire.fire(io.total_write_bytes2.ready) io.total_write_bytes2.bits := h_w_j_bytes + clitSize io.src_info_in.ready := total_write_bytes_fire.fire(io.src_info_in.valid) io.dst_info_in.ready := total_write_bytes_fire.fire(io.dst_info_in.valid) io.init_dictionary.valid := total_write_bytes_fire.fire(io.init_dictionary.ready) io.init_dictionary.bits := true.B when (total_write_bytes_fire.fire) { bufs_completed := bufs_completed + 1.U hufCompressState := sSendWeightDst written_weight_bytes := 0.U completed_streams := 0.U clitSize := 0.U jump_table(0) := 0.U jump_table(1) := 0.U jump_table(2) := 0.U first_stream := true.B write_header_fired := false.B CompressAccelLogger.logInfo("HUF_CONTROL_TOTAL_WRITE_BYTES\n") CompressAccelLogger.logInfo("total_write_bytes: %d\n", io.total_write_bytes.bits) CompressAccelLogger.logInfo("HEADER_SECTION: %d\n", lhSize) CompressAccelLogger.logInfo("WEIGHT_SECTION: %d\n", written_weight_bytes) CompressAccelLogger.logInfo("JUMP_TABLE: %d\n", Mux(singleStream, 0.U, 6.U)) CompressAccelLogger.logInfo("COMPRESSED_LITERALS: %d\n", clitSize) } }
module HufCompressorController( // @[HufCompressorController.scala:40:7] input clock, // @[HufCompressorController.scala:40:7] input reset, // @[HufCompressorController.scala:40:7] output io_src_info_in_ready, // @[HufCompressorController.scala:41:14] input io_src_info_in_valid, // @[HufCompressorController.scala:41:14] input [63:0] io_src_info_in_bits_ip, // @[HufCompressorController.scala:41:14] input [63:0] io_src_info_in_bits_isize, // @[HufCompressorController.scala:41:14] output io_dst_info_in_ready, // @[HufCompressorController.scala:41:14] input io_dst_info_in_valid, // @[HufCompressorController.scala:41:14] input [63:0] io_dst_info_in_bits_op, // @[HufCompressorController.scala:41:14] input [63:0] io_dst_info_in_bits_cmpflag, // @[HufCompressorController.scala:41:14] input [63:0] io_dst_info_in_bits_cmpval, // @[HufCompressorController.scala:41:14] input io_lit_src_info_ready, // @[HufCompressorController.scala:41:14] output io_lit_src_info_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_lit_src_info_bits_ip, // @[HufCompressorController.scala:41:14] output [63:0] io_lit_src_info_bits_isize, // @[HufCompressorController.scala:41:14] input io_lit_dst_info_ready, // @[HufCompressorController.scala:41:14] output io_lit_dst_info_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_lit_dst_info_bits_op, // @[HufCompressorController.scala:41:14] output [63:0] io_lit_dst_info_bits_cmpflag, // @[HufCompressorController.scala:41:14] output io_compressed_bytes_ready, // @[HufCompressorController.scala:41:14] input io_compressed_bytes_valid, // @[HufCompressorController.scala:41:14] input [63:0] io_compressed_bytes_bits, // @[HufCompressorController.scala:41:14] input io_hdr_dst_info_ready, // @[HufCompressorController.scala:41:14] output io_hdr_dst_info_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_hdr_dst_info_bits_op, // @[HufCompressorController.scala:41:14] output [63:0] io_hdr_dst_info_bits_cmpflag, // @[HufCompressorController.scala:41:14] input io_hdr_writes_ready, // @[HufCompressorController.scala:41:14] output io_hdr_writes_valid, // @[HufCompressorController.scala:41:14] output [255:0] io_hdr_writes_bits_data, // @[HufCompressorController.scala:41:14] output [5:0] io_hdr_writes_bits_validbytes, // @[HufCompressorController.scala:41:14] input io_jt_dst_info_ready, // @[HufCompressorController.scala:41:14] output io_jt_dst_info_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_jt_dst_info_bits_op, // @[HufCompressorController.scala:41:14] input io_jt_writes_ready, // @[HufCompressorController.scala:41:14] output io_jt_writes_valid, // @[HufCompressorController.scala:41:14] output [255:0] io_jt_writes_bits_data, // @[HufCompressorController.scala:41:14] input io_weight_dst_info_ready, // @[HufCompressorController.scala:41:14] output io_weight_dst_info_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_weight_dst_info_bits_op, // @[HufCompressorController.scala:41:14] output io_weight_bytes_ready, // @[HufCompressorController.scala:41:14] input io_weight_bytes_valid, // @[HufCompressorController.scala:41:14] input [63:0] io_weight_bytes_bits, // @[HufCompressorController.scala:41:14] output io_header_size_info_ready, // @[HufCompressorController.scala:41:14] input io_header_size_info_valid, // @[HufCompressorController.scala:41:14] input [7:0] io_header_size_info_bits, // @[HufCompressorController.scala:41:14] input io_total_write_bytes_ready, // @[HufCompressorController.scala:41:14] output io_total_write_bytes_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_total_write_bytes_bits, // @[HufCompressorController.scala:41:14] input io_total_write_bytes2_ready, // @[HufCompressorController.scala:41:14] output io_total_write_bytes2_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_total_write_bytes2_bits, // @[HufCompressorController.scala:41:14] input io_init_dictionary_ready, // @[HufCompressorController.scala:41:14] output io_init_dictionary_valid, // @[HufCompressorController.scala:41:14] output [63:0] io_bufs_completed // @[HufCompressorController.scala:41:14] ); wire _header_size_info_q_io_deq_valid; // @[HufCompressorController.scala:225:34] wire [7:0] _header_size_info_q_io_deq_bits; // @[HufCompressorController.scala:225:34] wire _lit_dst_info_q_io_enq_ready; // @[HufCompressorController.scala:140:30] wire _lit_src_info_q_io_enq_ready; // @[HufCompressorController.scala:139:30] wire _compressed_bytes_q_io_deq_valid; // @[HufCompressorController.scala:105:34] wire io_src_info_in_valid_0 = io_src_info_in_valid; // @[HufCompressorController.scala:40:7] wire [63:0] io_src_info_in_bits_ip_0 = io_src_info_in_bits_ip; // @[HufCompressorController.scala:40:7] wire [63:0] io_src_info_in_bits_isize_0 = io_src_info_in_bits_isize; // @[HufCompressorController.scala:40:7] wire io_dst_info_in_valid_0 = io_dst_info_in_valid; // @[HufCompressorController.scala:40:7] wire [63:0] io_dst_info_in_bits_op_0 = io_dst_info_in_bits_op; // @[HufCompressorController.scala:40:7] wire [63:0] io_dst_info_in_bits_cmpflag_0 = io_dst_info_in_bits_cmpflag; // @[HufCompressorController.scala:40:7] wire [63:0] io_dst_info_in_bits_cmpval_0 = io_dst_info_in_bits_cmpval; // @[HufCompressorController.scala:40:7] wire io_lit_src_info_ready_0 = io_lit_src_info_ready; // @[HufCompressorController.scala:40:7] wire io_lit_dst_info_ready_0 = io_lit_dst_info_ready; // @[HufCompressorController.scala:40:7] wire io_compressed_bytes_valid_0 = io_compressed_bytes_valid; // @[HufCompressorController.scala:40:7] wire [63:0] io_compressed_bytes_bits_0 = io_compressed_bytes_bits; // @[HufCompressorController.scala:40:7] wire io_hdr_dst_info_ready_0 = io_hdr_dst_info_ready; // @[HufCompressorController.scala:40:7] wire io_hdr_writes_ready_0 = io_hdr_writes_ready; // @[HufCompressorController.scala:40:7] wire io_jt_dst_info_ready_0 = io_jt_dst_info_ready; // @[HufCompressorController.scala:40:7] wire io_jt_writes_ready_0 = io_jt_writes_ready; // @[HufCompressorController.scala:40:7] wire io_weight_dst_info_ready_0 = io_weight_dst_info_ready; // @[HufCompressorController.scala:40:7] wire io_weight_bytes_valid_0 = io_weight_bytes_valid; // @[HufCompressorController.scala:40:7] wire [63:0] io_weight_bytes_bits_0 = io_weight_bytes_bits; // @[HufCompressorController.scala:40:7] wire io_header_size_info_valid_0 = io_header_size_info_valid; // @[HufCompressorController.scala:40:7] wire [7:0] io_header_size_info_bits_0 = io_header_size_info_bits; // @[HufCompressorController.scala:40:7] wire io_total_write_bytes_ready_0 = io_total_write_bytes_ready; // @[HufCompressorController.scala:40:7] wire io_total_write_bytes2_ready_0 = io_total_write_bytes2_ready; // @[HufCompressorController.scala:40:7] wire io_init_dictionary_ready_0 = io_init_dictionary_ready; // @[HufCompressorController.scala:40:7] wire io_hdr_writes_bits_end_of_message = 1'h1; // @[HufCompressorController.scala:40:7] wire io_jt_writes_bits_end_of_message = 1'h1; // @[HufCompressorController.scala:40:7] wire io_init_dictionary_bits = 1'h1; // @[HufCompressorController.scala:40:7] wire [63:0] io_jt_dst_info_bits_cmpflag = 64'h0; // @[HufCompressorController.scala:40:7] wire [63:0] io_weight_dst_info_bits_cmpflag = 64'h0; // @[HufCompressorController.scala:40:7] wire [5:0] io_jt_writes_bits_validbytes = 6'h6; // @[HufCompressorController.scala:40:7] wire [15:0] _jump_table_WIRE_0 = 16'h0; // @[HufCompressorController.scala:99:35] wire [15:0] _jump_table_WIRE_1 = 16'h0; // @[HufCompressorController.scala:99:35] wire [15:0] _jump_table_WIRE_2 = 16'h0; // @[HufCompressorController.scala:99:35] wire [3:0] _lhc_T_18 = 4'hE; // @[HufCompressorController.scala:93:18] wire [3:0] _lhc_T_10 = 4'hA; // @[HufCompressorController.scala:91:18] wire [4:0] _lhc_T_17 = 5'hE; // @[HufCompressorController.scala:93:18] wire [4:0] _lhc_T_9 = 5'hA; // @[HufCompressorController.scala:91:18] wire _io_src_info_in_ready_T_3; // @[Misc.scala:26:53] wire _io_dst_info_in_ready_T_3; // @[Misc.scala:26:53] wire [63:0] io_hdr_dst_info_bits_op_0 = io_dst_info_in_bits_op_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_hdr_dst_info_bits_cmpflag_0 = io_dst_info_in_bits_cmpflag_0; // @[HufCompressorController.scala:40:7] wire _io_hdr_dst_info_valid_T_3; // @[Misc.scala:26:53] wire _io_hdr_writes_valid_T_3; // @[Misc.scala:26:53] wire _io_jt_dst_info_valid_T_4; // @[Misc.scala:26:53] wire [63:0] _io_jt_dst_info_bits_op_T_3; // @[HufCompressorController.scala:206:61] wire _io_jt_writes_valid_T_4; // @[Misc.scala:26:53] wire _io_weight_dst_info_valid_T_1; // @[Misc.scala:29:18] wire [63:0] _io_weight_dst_info_bits_op_T_3; // @[HufCompressorController.scala:123:65] wire _io_weight_bytes_ready_T; // @[HufCompressorController.scala:131:46] wire _io_total_write_bytes_valid_T_3; // @[Misc.scala:26:53] wire [63:0] _io_total_write_bytes_bits_T_1; // @[HufCompressorController.scala:286:44] wire _io_total_write_bytes2_valid_T_3; // @[Misc.scala:26:53] wire [63:0] _io_total_write_bytes2_bits_T_1; // @[HufCompressorController.scala:289:45] wire _io_init_dictionary_valid_T_3; // @[Misc.scala:26:53] wire io_src_info_in_ready_0; // @[HufCompressorController.scala:40:7] wire io_dst_info_in_ready_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_lit_src_info_bits_ip_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_lit_src_info_bits_isize_0; // @[HufCompressorController.scala:40:7] wire io_lit_src_info_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_lit_dst_info_bits_op_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_lit_dst_info_bits_cmpflag_0; // @[HufCompressorController.scala:40:7] wire io_lit_dst_info_valid_0; // @[HufCompressorController.scala:40:7] wire io_compressed_bytes_ready_0; // @[HufCompressorController.scala:40:7] wire io_hdr_dst_info_valid_0; // @[HufCompressorController.scala:40:7] wire [255:0] io_hdr_writes_bits_data_0; // @[HufCompressorController.scala:40:7] wire [5:0] io_hdr_writes_bits_validbytes_0; // @[HufCompressorController.scala:40:7] wire io_hdr_writes_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_jt_dst_info_bits_op_0; // @[HufCompressorController.scala:40:7] wire io_jt_dst_info_valid_0; // @[HufCompressorController.scala:40:7] wire [255:0] io_jt_writes_bits_data_0; // @[HufCompressorController.scala:40:7] wire io_jt_writes_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_weight_dst_info_bits_op_0; // @[HufCompressorController.scala:40:7] wire io_weight_dst_info_valid_0; // @[HufCompressorController.scala:40:7] wire io_weight_bytes_ready_0; // @[HufCompressorController.scala:40:7] wire io_header_size_info_ready_0; // @[HufCompressorController.scala:40:7] wire io_total_write_bytes_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_total_write_bytes_bits_0; // @[HufCompressorController.scala:40:7] wire io_total_write_bytes2_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_total_write_bytes2_bits_0; // @[HufCompressorController.scala:40:7] wire io_init_dictionary_valid_0; // @[HufCompressorController.scala:40:7] wire [63:0] io_bufs_completed_0; // @[HufCompressorController.scala:40:7] reg [2:0] hufCompressState; // @[HufCompressorController.scala:68:33] wire singleStream = io_src_info_in_bits_isize_0 < 64'h100; // @[HufCompressorController.scala:40:7, :72:30] reg [63:0] written_weight_bytes; // @[HufCompressorController.scala:73:37] reg [63:0] clitSize; // @[HufCompressorController.scala:74:25] wire [2:0] _T_178 = singleStream ? 3'h0 : 3'h6; // @[HufCompressorController.scala:72:30, :77:48] wire [2:0] _totCompBytes_T; // @[HufCompressorController.scala:77:48] assign _totCompBytes_T = _T_178; // @[HufCompressorController.scala:77:48] wire [2:0] _h_w_j_bytes_T_2; // @[HufCompressorController.scala:158:56] assign _h_w_j_bytes_T_2 = _T_178; // @[HufCompressorController.scala:77:48, :158:56] wire [64:0] _GEN = {1'h0, written_weight_bytes}; // @[HufCompressorController.scala:73:37, :77:43] wire [64:0] _totCompBytes_T_1 = _GEN + {62'h0, _totCompBytes_T}; // @[HufCompressorController.scala:77:{43,48}] wire [63:0] _totCompBytes_T_2 = _totCompBytes_T_1[63:0]; // @[HufCompressorController.scala:77:43] wire [64:0] _GEN_0 = {1'h0, clitSize}; // @[HufCompressorController.scala:74:25, :77:73] wire [64:0] _totCompBytes_T_3 = {1'h0, _totCompBytes_T_2} + _GEN_0; // @[HufCompressorController.scala:77:{43,73}] wire [63:0] totCompBytes = _totCompBytes_T_3[63:0]; // @[HufCompressorController.scala:77:73] wire _lhSizeSrc_T = |(io_src_info_in_bits_isize_0[63:10]); // @[HufCompressorController.scala:40:7, :83:38] wire _lhSizeSrc_T_1 = _lhSizeSrc_T; // @[HufCompressorController.scala:83:{29,38}] wire [2:0] _lhSizeSrc_T_2 = {2'h0, _lhSizeSrc_T_1} + 3'h3; // @[HufCompressorController.scala:83:{23,29}] wire _lhSizeSrc_T_3 = |(io_src_info_in_bits_isize_0[63:14]); // @[HufCompressorController.scala:40:7, :83:76] wire _lhSizeSrc_T_4 = _lhSizeSrc_T_3; // @[HufCompressorController.scala:83:{67,76}] wire [3:0] lhSizeSrc = {1'h0, _lhSizeSrc_T_2} + {3'h0, _lhSizeSrc_T_4}; // @[HufCompressorController.scala:83:{23,61,67}] wire _lhSizeComp_T = |(totCompBytes[63:10]); // @[HufCompressorController.scala:77:73, :84:44] wire _lhSizeComp_T_1 = _lhSizeComp_T; // @[HufCompressorController.scala:84:{30,44}] wire [2:0] _lhSizeComp_T_2 = {2'h0, _lhSizeComp_T_1} + 3'h3; // @[HufCompressorController.scala:84:{24,30}] wire _lhSizeComp_T_3 = |(totCompBytes[63:14]); // @[HufCompressorController.scala:77:73, :84:87] wire _lhSizeComp_T_4 = _lhSizeComp_T_3; // @[HufCompressorController.scala:84:{73,87}] wire [3:0] lhSizeComp = {1'h0, _lhSizeComp_T_2} + {3'h0, _lhSizeComp_T_4}; // @[HufCompressorController.scala:84:{24,67,73}] wire _lhSize_T = totCompBytes < io_src_info_in_bits_isize_0; // @[HufCompressorController.scala:40:7, :77:73, :85:33] wire [3:0] lhSize = _lhSize_T ? lhSizeSrc : lhSizeComp; // @[HufCompressorController.scala:83:61, :84:67, :85:{19,33}] wire [3:0] lhSize_4 = lhSize; // @[HufCompressorController.scala:85:19, :252:26] wire [41:0] lhc; // @[HufCompressorController.scala:87:21] wire [2:0] _lhc_T = {~singleStream, 2'h0}; // @[HufCompressorController.scala:72:30, :89:23] wire [3:0] _lhc_T_1 = {1'h0, _lhc_T} + 4'h2; // @[HufCompressorController.scala:89:{18,23}] wire [2:0] _lhc_T_2 = _lhc_T_1[2:0]; // @[HufCompressorController.scala:89:18] wire [70:0] _GEN_1 = {3'h0, io_src_info_in_bits_isize_0, 4'h0}; // @[HufCompressorController.scala:40:7, :89:66] wire [70:0] _lhc_T_3; // @[HufCompressorController.scala:89:66] assign _lhc_T_3 = _GEN_1; // @[HufCompressorController.scala:89:66] wire [70:0] _lhc_T_11; // @[HufCompressorController.scala:91:42] assign _lhc_T_11 = _GEN_1; // @[HufCompressorController.scala:89:66, :91:42] wire [70:0] _lhc_T_19; // @[HufCompressorController.scala:93:42] assign _lhc_T_19 = _GEN_1; // @[HufCompressorController.scala:89:66, :93:42] wire [71:0] _lhc_T_4 = {69'h0, _lhc_T_2} + {1'h0, _lhc_T_3}; // @[HufCompressorController.scala:89:{18,55,66}] wire [70:0] _lhc_T_5 = _lhc_T_4[70:0]; // @[HufCompressorController.scala:89:55] wire [78:0] _lhc_T_6 = {1'h0, totCompBytes, 14'h0}; // @[HufCompressorController.scala:77:73, :89:90] wire [79:0] _lhc_T_7 = {9'h0, _lhc_T_5} + {1'h0, _lhc_T_6}; // @[HufCompressorController.scala:89:{55,74,90}] wire [78:0] _lhc_T_8 = _lhc_T_7[78:0]; // @[HufCompressorController.scala:89:74] wire [71:0] _lhc_T_12 = {1'h0, _lhc_T_11} + 72'hA; // @[HufCompressorController.scala:91:{31,42}] wire [70:0] _lhc_T_13 = _lhc_T_12[70:0]; // @[HufCompressorController.scala:91:31] wire [94:0] _lhc_T_14 = {13'h0, totCompBytes, 18'h0}; // @[HufCompressorController.scala:77:73, :91:66] wire [95:0] _lhc_T_15 = {25'h0, _lhc_T_13} + {1'h0, _lhc_T_14}; // @[HufCompressorController.scala:91:{31,50,66}] wire [94:0] _lhc_T_16 = _lhc_T_15[94:0]; // @[HufCompressorController.scala:91:50] wire [71:0] _lhc_T_20 = {1'h0, _lhc_T_19} + 72'hE; // @[HufCompressorController.scala:93:{31,42}] wire [70:0] _lhc_T_21 = _lhc_T_20[70:0]; // @[HufCompressorController.scala:93:31] wire [94:0] _lhc_T_22 = {9'h0, totCompBytes, 22'h0}; // @[HufCompressorController.scala:77:73, :93:66] wire [95:0] _lhc_T_23 = {25'h0, _lhc_T_21} + {1'h0, _lhc_T_22}; // @[HufCompressorController.scala:93:{31,50,66}] wire [94:0] _lhc_T_24 = _lhc_T_23[94:0]; // @[HufCompressorController.scala:93:50] assign lhc = lhSize == 4'h3 ? _lhc_T_8[41:0] : lhSize == 4'h4 ? _lhc_T_16[41:0] : lhSize == 4'h5 ? _lhc_T_24[41:0] : 42'h0; // @[HufCompressorController.scala:85:19, :87:21, :88:{16,25}, :89:{9,74}, :90:{23,32}, :91:{9,50}, :92:{23,32}, :93:{9,50}] reg [2:0] completed_streams; // @[HufCompressorController.scala:96:34] wire [2:0] num_streams = singleStream ? 3'h1 : 3'h4; // @[HufCompressorController.scala:72:30, :97:24] reg [15:0] jump_table_0; // @[HufCompressorController.scala:99:27] reg [15:0] jump_table_1; // @[HufCompressorController.scala:99:27] reg [15:0] jump_table_2; // @[HufCompressorController.scala:99:27] wire [31:0] jump_table_concat_hi = {jump_table_2, jump_table_1}; // @[HufCompressorController.scala:99:27, :100:30] wire [47:0] jump_table_concat = {jump_table_concat_hi, jump_table_0}; // @[HufCompressorController.scala:99:27, :100:30] wire [64:0] _segment_size_T = {1'h0, io_src_info_in_bits_isize_0} + 65'h3; // @[HufCompressorController.scala:40:7, :102:31] wire [63:0] _segment_size_T_1 = _segment_size_T[63:0]; // @[HufCompressorController.scala:102:31] wire [63:0] segment_size = {2'h0, _segment_size_T_1[63:2]}; // @[HufCompressorController.scala:102:{31,38}] wire [65:0] _GEN_2 = {2'h0, segment_size}; // @[HufCompressorController.scala:102:38, :103:51] wire [65:0] _last_segment_size_T = _GEN_2 * 66'h3; // @[HufCompressorController.scala:103:51] wire [66:0] _last_segment_size_T_1 = {3'h0, io_src_info_in_bits_isize_0} - {1'h0, _last_segment_size_T}; // @[HufCompressorController.scala:40:7, :103:{35,51}] wire [65:0] last_segment_size = _last_segment_size_T_1[65:0]; // @[HufCompressorController.scala:103:35] wire _T_3 = io_compressed_bytes_ready_0 & io_compressed_bytes_valid_0; // @[Decoupled.scala:51:35] wire [3:0] _completed_streams_T = {1'h0, completed_streams} + 4'h1; // @[HufCompressorController.scala:96:34, :108:44] wire [2:0] _completed_streams_T_1 = _completed_streams_T[2:0]; // @[HufCompressorController.scala:108:44] wire [64:0] _clitSize_T = _GEN_0 + {1'h0, io_compressed_bytes_bits_0}; // @[HufCompressorController.scala:40:7, :77:73, :109:26] wire [63:0] _clitSize_T_1 = _clitSize_T[63:0]; // @[HufCompressorController.scala:109:26] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire _T_13 = hufCompressState == 3'h0; // @[HufCompressorController.scala:68:33, :120:22] wire _T_124 = io_src_info_in_valid_0 & io_dst_info_in_valid_0; // @[Misc.scala:29:18] wire _io_weight_dst_info_valid_T; // @[Misc.scala:29:18] assign _io_weight_dst_info_valid_T = _T_124; // @[Misc.scala:29:18] wire _compressed_bytes_q_io_deq_ready_T; // @[Misc.scala:26:53] assign _compressed_bytes_q_io_deq_ready_T = _T_124; // @[Misc.scala:26:53, :29:18] wire _lit_dst_info_q_io_enq_valid_T_1; // @[Misc.scala:26:53] assign _lit_dst_info_q_io_enq_valid_T_1 = _T_124; // @[Misc.scala:26:53, :29:18] wire _lit_src_info_q_io_enq_valid_T_1; // @[Misc.scala:26:53] assign _lit_src_info_q_io_enq_valid_T_1 = _T_124; // @[Misc.scala:26:53, :29:18] wire _io_jt_dst_info_valid_T_1; // @[Misc.scala:26:53] assign _io_jt_dst_info_valid_T_1 = _T_124; // @[Misc.scala:26:53, :29:18] wire _io_jt_writes_valid_T_1; // @[Misc.scala:26:53] assign _io_jt_writes_valid_T_1 = _T_124; // @[Misc.scala:26:53, :29:18] wire _io_hdr_dst_info_valid_T; // @[Misc.scala:26:53] assign _io_hdr_dst_info_valid_T = _T_124; // @[Misc.scala:26:53, :29:18] wire _header_size_info_q_io_deq_ready_T; // @[Misc.scala:26:53] assign _header_size_info_q_io_deq_ready_T = _T_124; // @[Misc.scala:26:53, :29:18] wire _io_hdr_writes_valid_T; // @[Misc.scala:26:53] assign _io_hdr_writes_valid_T = _T_124; // @[Misc.scala:26:53, :29:18] assign _io_weight_dst_info_valid_T_1 = _io_weight_dst_info_valid_T & _T_13; // @[Misc.scala:29:18] assign io_weight_dst_info_valid_0 = _io_weight_dst_info_valid_T_1; // @[Misc.scala:29:18] wire [64:0] _GEN_3 = {1'h0, io_dst_info_in_bits_op_0}; // @[HufCompressorController.scala:40:7, :123:56] wire [64:0] _GEN_4 = {61'h0, lhSize}; // @[HufCompressorController.scala:85:19, :123:56] wire [64:0] _GEN_5 = _GEN_3 + _GEN_4; // @[HufCompressorController.scala:123:56] wire [64:0] _io_weight_dst_info_bits_op_T; // @[HufCompressorController.scala:123:56] assign _io_weight_dst_info_bits_op_T = _GEN_5; // @[HufCompressorController.scala:123:56] wire [64:0] _io_jt_dst_info_bits_op_T; // @[HufCompressorController.scala:206:52] assign _io_jt_dst_info_bits_op_T = _GEN_5; // @[HufCompressorController.scala:123:56, :206:52] wire [63:0] _io_weight_dst_info_bits_op_T_1 = _io_weight_dst_info_bits_op_T[63:0]; // @[HufCompressorController.scala:123:56] wire [64:0] _io_weight_dst_info_bits_op_T_2 = {1'h0, _io_weight_dst_info_bits_op_T_1} + 65'h1; // @[HufCompressorController.scala:123:{56,65}] assign _io_weight_dst_info_bits_op_T_3 = _io_weight_dst_info_bits_op_T_2[63:0]; // @[HufCompressorController.scala:123:65] assign io_weight_dst_info_bits_op_0 = _io_weight_dst_info_bits_op_T_3; // @[HufCompressorController.scala:40:7, :123:65] assign _io_weight_bytes_ready_T = hufCompressState == 3'h1; // @[HufCompressorController.scala:68:33, :131:46] assign io_weight_bytes_ready_0 = _io_weight_bytes_ready_T; // @[HufCompressorController.scala:40:7, :131:46] wire _T_16 = io_weight_bytes_ready_0 & io_weight_bytes_valid_0; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg first_stream; // @[HufCompressorController.scala:144:29] wire kickoff_encoder = first_stream | _compressed_bytes_q_io_deq_valid; // @[HufCompressorController.scala:105:34, :144:29, :145:38] wire _T_21 = hufCompressState == 3'h2; // @[HufCompressorController.scala:68:33, :154:22] wire _compressed_bytes_q_io_deq_ready_T_1 = _compressed_bytes_q_io_deq_ready_T & _lit_src_info_q_io_enq_ready; // @[Misc.scala:26:53] wire _compressed_bytes_q_io_deq_ready_T_2 = _compressed_bytes_q_io_deq_ready_T_1 & _lit_dst_info_q_io_enq_ready; // @[Misc.scala:26:53] wire _compressed_bytes_q_io_deq_ready_T_3 = _compressed_bytes_q_io_deq_ready_T_2 & _T_21; // @[Misc.scala:26:53] wire [64:0] _h_w_j_bytes_T = _GEN_4 + _GEN; // @[HufCompressorController.scala:77:43, :123:56, :158:28] wire [63:0] _h_w_j_bytes_T_1 = _h_w_j_bytes_T[63:0]; // @[HufCompressorController.scala:158:28] wire [64:0] _h_w_j_bytes_T_3 = {1'h0, _h_w_j_bytes_T_1} + {62'h0, _h_w_j_bytes_T_2}; // @[HufCompressorController.scala:158:{28,51,56}] wire [63:0] h_w_j_bytes = _h_w_j_bytes_T_3[63:0]; // @[HufCompressorController.scala:158:51] wire [64:0] _GEN_6 = {1'h0, h_w_j_bytes}; // @[HufCompressorController.scala:158:51, :160:59] wire [64:0] _lit_dst_info_q_io_enq_bits_op_T = _GEN_3 + _GEN_6; // @[HufCompressorController.scala:123:56, :160:59] wire [63:0] _lit_dst_info_q_io_enq_bits_op_T_1 = _lit_dst_info_q_io_enq_bits_op_T[63:0]; // @[HufCompressorController.scala:160:59] wire [64:0] _lit_dst_info_q_io_enq_bits_op_T_2 = {1'h0, _lit_dst_info_q_io_enq_bits_op_T_1} + _GEN_0; // @[HufCompressorController.scala:77:73, :160:{59,73}] wire [63:0] _lit_dst_info_q_io_enq_bits_op_T_3 = _lit_dst_info_q_io_enq_bits_op_T_2[63:0]; // @[HufCompressorController.scala:160:73] wire _GEN_7 = completed_streams < num_streams; // @[HufCompressorController.scala:96:34, :97:24, :162:107] wire _lit_dst_info_q_io_enq_valid_T; // @[HufCompressorController.scala:162:107] assign _lit_dst_info_q_io_enq_valid_T = _GEN_7; // @[HufCompressorController.scala:162:107] wire _lit_src_info_q_io_enq_valid_T; // @[HufCompressorController.scala:167:107] assign _lit_src_info_q_io_enq_valid_T = _GEN_7; // @[HufCompressorController.scala:162:107, :167:107] wire _lit_dst_info_q_io_enq_valid_T_2 = _lit_dst_info_q_io_enq_valid_T_1 & _lit_src_info_q_io_enq_ready; // @[Misc.scala:26:53] wire _lit_dst_info_q_io_enq_valid_T_3 = _lit_dst_info_q_io_enq_valid_T_2 & kickoff_encoder; // @[Misc.scala:26:53] wire _lit_dst_info_q_io_enq_valid_T_4 = _lit_dst_info_q_io_enq_valid_T_3 & _T_21; // @[Misc.scala:26:53] wire _lit_dst_info_q_io_enq_valid_T_5 = _lit_dst_info_q_io_enq_valid_T_4 & _lit_dst_info_q_io_enq_valid_T; // @[Misc.scala:26:53] wire [66:0] _lit_src_info_q_io_enq_bits_ip_T = {64'h0, completed_streams} * {3'h0, segment_size}; // @[HufCompressorController.scala:96:34, :102:38, :164:79] wire [67:0] _lit_src_info_q_io_enq_bits_ip_T_1 = {4'h0, io_src_info_in_bits_ip_0} + {1'h0, _lit_src_info_q_io_enq_bits_ip_T}; // @[HufCompressorController.scala:40:7, :164:{59,79}] wire [66:0] _lit_src_info_q_io_enq_bits_ip_T_2 = _lit_src_info_q_io_enq_bits_ip_T_1[66:0]; // @[HufCompressorController.scala:164:59] wire _lit_src_info_q_io_enq_bits_isize_T = ~singleStream; // @[HufCompressorController.scala:72:30, :165:43] wire _lit_src_info_q_io_enq_bits_isize_T_1 = completed_streams == 3'h3; // @[HufCompressorController.scala:96:34, :165:80] wire [65:0] _lit_src_info_q_io_enq_bits_isize_T_2 = _lit_src_info_q_io_enq_bits_isize_T_1 ? last_segment_size : _GEN_2; // @[HufCompressorController.scala:103:{35,51}, :165:{61,80}] wire [65:0] _lit_src_info_q_io_enq_bits_isize_T_3 = _lit_src_info_q_io_enq_bits_isize_T ? _lit_src_info_q_io_enq_bits_isize_T_2 : {2'h0, io_src_info_in_bits_isize_0}; // @[HufCompressorController.scala:40:7, :165:{42,43,61}] wire _lit_src_info_q_io_enq_valid_T_2 = _lit_src_info_q_io_enq_valid_T_1 & _lit_dst_info_q_io_enq_ready; // @[Misc.scala:26:53] wire _lit_src_info_q_io_enq_valid_T_3 = _lit_src_info_q_io_enq_valid_T_2 & kickoff_encoder; // @[Misc.scala:26:53] wire _lit_src_info_q_io_enq_valid_T_4 = _lit_src_info_q_io_enq_valid_T_3 & _T_21; // @[Misc.scala:26:53] wire _lit_src_info_q_io_enq_valid_T_5 = _lit_src_info_q_io_enq_valid_T_4 & _lit_src_info_q_io_enq_valid_T; // @[Misc.scala:26:53] wire last_kickoff_done = completed_streams == num_streams; // @[HufCompressorController.scala:96:34, :97:24, :182:46] wire _T_32 = _T_124 & _lit_dst_info_q_io_enq_ready & kickoff_encoder & _T_21 & last_kickoff_done; // @[Misc.scala:26:53, :29:18] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] wire _T_72 = hufCompressState == 3'h3; // @[HufCompressorController.scala:68:33, :203:22] wire _io_jt_dst_info_valid_T = ~singleStream; // @[HufCompressorController.scala:72:30, :165:43, :205:76] wire _io_jt_dst_info_valid_T_2 = _io_jt_dst_info_valid_T_1 & io_jt_writes_ready_0; // @[Misc.scala:26:53] wire _io_jt_dst_info_valid_T_3 = _io_jt_dst_info_valid_T_2 & _T_72; // @[Misc.scala:26:53] assign _io_jt_dst_info_valid_T_4 = _io_jt_dst_info_valid_T_3 & _io_jt_dst_info_valid_T; // @[Misc.scala:26:53] assign io_jt_dst_info_valid_0 = _io_jt_dst_info_valid_T_4; // @[Misc.scala:26:53] wire [63:0] _io_jt_dst_info_bits_op_T_1 = _io_jt_dst_info_bits_op_T[63:0]; // @[HufCompressorController.scala:206:52] wire [64:0] _io_jt_dst_info_bits_op_T_2 = {1'h0, _io_jt_dst_info_bits_op_T_1} + _GEN; // @[HufCompressorController.scala:77:43, :206:{52,61}] assign _io_jt_dst_info_bits_op_T_3 = _io_jt_dst_info_bits_op_T_2[63:0]; // @[HufCompressorController.scala:206:61] assign io_jt_dst_info_bits_op_0 = _io_jt_dst_info_bits_op_T_3; // @[HufCompressorController.scala:40:7, :206:61] wire _io_jt_writes_valid_T = ~singleStream; // @[HufCompressorController.scala:72:30, :165:43, :209:72] wire _io_jt_writes_valid_T_2 = _io_jt_writes_valid_T_1 & io_jt_dst_info_ready_0; // @[Misc.scala:26:53] wire _io_jt_writes_valid_T_3 = _io_jt_writes_valid_T_2 & _T_72; // @[Misc.scala:26:53] assign _io_jt_writes_valid_T_4 = _io_jt_writes_valid_T_3 & _io_jt_writes_valid_T; // @[Misc.scala:26:53] assign io_jt_writes_valid_0 = _io_jt_writes_valid_T_4; // @[Misc.scala:26:53] assign io_jt_writes_bits_data_0 = {208'h0, jump_table_concat}; // @[HufCompressorController.scala:40:7, :100:30, :210:26] wire _T_76 = _T_124 & io_jt_dst_info_ready_0 & io_jt_writes_ready_0 & _T_72; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] wire _T_95 = hufCompressState == 3'h4; // @[HufCompressorController.scala:68:33, :234:22] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] wire _io_hdr_dst_info_valid_T_1 = _io_hdr_dst_info_valid_T & io_hdr_writes_ready_0; // @[Misc.scala:26:53] wire _io_hdr_dst_info_valid_T_2 = _io_hdr_dst_info_valid_T_1 & _header_size_info_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_hdr_dst_info_valid_T_3 = _io_hdr_dst_info_valid_T_2 & _T_95; // @[Misc.scala:26:53] assign io_hdr_dst_info_valid_0 = _io_hdr_dst_info_valid_T_3; // @[Misc.scala:26:53] wire _header_size_info_q_io_deq_ready_T_1 = _header_size_info_q_io_deq_ready_T & io_hdr_dst_info_ready_0; // @[Misc.scala:26:53] wire _header_size_info_q_io_deq_ready_T_2 = _header_size_info_q_io_deq_ready_T_1 & io_hdr_writes_ready_0; // @[Misc.scala:26:53] wire _header_size_info_q_io_deq_ready_T_3 = _header_size_info_q_io_deq_ready_T_2 & _T_95; // @[Misc.scala:26:53] wire [6:0] _header_with_size_T = {lhSize_4, 3'h0}; // @[HufCompressorController.scala:252:26, :255:77] wire [134:0] _header_with_size_T_1 = {127'h0, _header_size_info_q_io_deq_bits} << _header_with_size_T; // @[HufCompressorController.scala:225:34, :255:{64,77}] wire [134:0] header_with_size = {93'h0, lhc} | _header_with_size_T_1; // @[HufCompressorController.scala:87:21, :255:{30,64}] wire _io_hdr_writes_valid_T_1 = _io_hdr_writes_valid_T & io_hdr_dst_info_ready_0; // @[Misc.scala:26:53] wire _io_hdr_writes_valid_T_2 = _io_hdr_writes_valid_T_1 & _header_size_info_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_hdr_writes_valid_T_3 = _io_hdr_writes_valid_T_2 & _T_95; // @[Misc.scala:26:53] assign io_hdr_writes_valid_0 = _io_hdr_writes_valid_T_3; // @[Misc.scala:26:53] assign io_hdr_writes_bits_data_0 = {121'h0, header_with_size}; // @[HufCompressorController.scala:40:7, :255:30, :257:27] wire [4:0] _io_hdr_writes_bits_validbytes_T = {1'h0, lhSize} + 5'h1; // @[HufCompressorController.scala:85:19, :258:43] assign io_hdr_writes_bits_validbytes_0 = {1'h0, _io_hdr_writes_bits_validbytes_T}; // @[HufCompressorController.scala:40:7, :258:{33,43}] reg [63:0] bufs_completed; // @[HufCompressorController.scala:261:31] assign io_bufs_completed_0 = bufs_completed; // @[HufCompressorController.scala:40:7, :261:31] reg write_header_fired; // @[HufCompressorController.scala:264:35] wire _T_128 = _T_124 & io_hdr_dst_info_ready_0 & io_hdr_writes_ready_0 & _header_size_info_q_io_deq_valid & _T_95; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] wire _io_total_write_bytes_valid_T = io_total_write_bytes2_ready_0 & io_init_dictionary_ready_0; // @[Misc.scala:26:53] wire _io_total_write_bytes_valid_T_1 = _io_total_write_bytes_valid_T & io_src_info_in_valid_0; // @[Misc.scala:26:53] wire _io_total_write_bytes_valid_T_2 = _io_total_write_bytes_valid_T_1 & io_dst_info_in_valid_0; // @[Misc.scala:26:53] assign _io_total_write_bytes_valid_T_3 = _io_total_write_bytes_valid_T_2 & write_header_fired; // @[Misc.scala:26:53] assign io_total_write_bytes_valid_0 = _io_total_write_bytes_valid_T_3; // @[Misc.scala:26:53] wire [64:0] _GEN_8 = _GEN_6 + _GEN_0; // @[HufCompressorController.scala:77:73, :160:59, :286:44] wire [64:0] _io_total_write_bytes_bits_T; // @[HufCompressorController.scala:286:44] assign _io_total_write_bytes_bits_T = _GEN_8; // @[HufCompressorController.scala:286:44] wire [64:0] _io_total_write_bytes2_bits_T; // @[HufCompressorController.scala:289:45] assign _io_total_write_bytes2_bits_T = _GEN_8; // @[HufCompressorController.scala:286:44, :289:45] assign _io_total_write_bytes_bits_T_1 = _io_total_write_bytes_bits_T[63:0]; // @[HufCompressorController.scala:286:44] assign io_total_write_bytes_bits_0 = _io_total_write_bytes_bits_T_1; // @[HufCompressorController.scala:40:7, :286:44] wire _io_total_write_bytes2_valid_T = io_total_write_bytes_ready_0 & io_init_dictionary_ready_0; // @[Misc.scala:26:53] wire _io_total_write_bytes2_valid_T_1 = _io_total_write_bytes2_valid_T & io_src_info_in_valid_0; // @[Misc.scala:26:53] wire _io_total_write_bytes2_valid_T_2 = _io_total_write_bytes2_valid_T_1 & io_dst_info_in_valid_0; // @[Misc.scala:26:53] assign _io_total_write_bytes2_valid_T_3 = _io_total_write_bytes2_valid_T_2 & write_header_fired; // @[Misc.scala:26:53] assign io_total_write_bytes2_valid_0 = _io_total_write_bytes2_valid_T_3; // @[Misc.scala:26:53] assign _io_total_write_bytes2_bits_T_1 = _io_total_write_bytes2_bits_T[63:0]; // @[HufCompressorController.scala:289:45] assign io_total_write_bytes2_bits_0 = _io_total_write_bytes2_bits_T_1; // @[HufCompressorController.scala:40:7, :289:45] wire _T_157 = io_total_write_bytes_ready_0 & io_total_write_bytes2_ready_0; // @[Misc.scala:26:53] wire _io_src_info_in_ready_T; // @[Misc.scala:26:53] assign _io_src_info_in_ready_T = _T_157; // @[Misc.scala:26:53] wire _io_dst_info_in_ready_T; // @[Misc.scala:26:53] assign _io_dst_info_in_ready_T = _T_157; // @[Misc.scala:26:53] wire _io_init_dictionary_valid_T; // @[Misc.scala:26:53] assign _io_init_dictionary_valid_T = _T_157; // @[Misc.scala:26:53] wire _io_src_info_in_ready_T_1 = _io_src_info_in_ready_T & io_init_dictionary_ready_0; // @[Misc.scala:26:53] wire _io_src_info_in_ready_T_2 = _io_src_info_in_ready_T_1 & io_dst_info_in_valid_0; // @[Misc.scala:26:53] assign _io_src_info_in_ready_T_3 = _io_src_info_in_ready_T_2 & write_header_fired; // @[Misc.scala:26:53] assign io_src_info_in_ready_0 = _io_src_info_in_ready_T_3; // @[Misc.scala:26:53] wire _io_dst_info_in_ready_T_1 = _io_dst_info_in_ready_T & io_init_dictionary_ready_0; // @[Misc.scala:26:53] wire _io_dst_info_in_ready_T_2 = _io_dst_info_in_ready_T_1 & io_src_info_in_valid_0; // @[Misc.scala:26:53] assign _io_dst_info_in_ready_T_3 = _io_dst_info_in_ready_T_2 & write_header_fired; // @[Misc.scala:26:53] assign io_dst_info_in_ready_0 = _io_dst_info_in_ready_T_3; // @[Misc.scala:26:53] wire _io_init_dictionary_valid_T_1 = _io_init_dictionary_valid_T & io_src_info_in_valid_0; // @[Misc.scala:26:53] wire _io_init_dictionary_valid_T_2 = _io_init_dictionary_valid_T_1 & io_dst_info_in_valid_0; // @[Misc.scala:26:53] assign _io_init_dictionary_valid_T_3 = _io_init_dictionary_valid_T_2 & write_header_fired; // @[Misc.scala:26:53] assign io_init_dictionary_valid_0 = _io_init_dictionary_valid_T_3; // @[Misc.scala:26:53] wire _T_161 = _T_157 & io_init_dictionary_ready_0 & io_src_info_in_valid_0 & io_dst_info_in_valid_0 & write_header_fired; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[HufCompressorController.scala:261:31, :298:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[HufCompressorController.scala:298:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulRawFN_19( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_19 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }
module SwitchArbiter_145( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [4:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [4:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [4:0] unassigned = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [4:0] mask; // @[SwitchAllocator.scala:27:21] wire [4:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [9:0] sel = _sel_T_1[0] ? 10'h1 : _sel_T_1[1] ? 10'h2 : _sel_T_1[2] ? 10'h4 : _sel_T_1[3] ? 10'h8 : _sel_T_1[4] ? 10'h10 : unassigned[0] ? 10'h20 : unassigned[1] ? 10'h40 : unassigned[2] ? 10'h80 : unassigned[3] ? 10'h100 : {unassigned[4], 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_valids = {io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [4:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[4:0] | sel[9:5]; // @[Mux.scala:50:70] wire [4:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [3:0] _GEN = chosen[3:0] | chosen[4:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_0 = _GEN[2:0] | chosen[4:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_1 = _GEN_0[1:0] | chosen[4:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 5'h0; // @[SwitchAllocator.scala:24:38] mask <= 5'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_4_bits_tail, io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (|_io_out_0_valid_T) ? {chosen[4], _GEN[3], _GEN_0[2], _GEN_1[1], _GEN_1[0] | chosen[4]} : (&mask) ? 5'h0 : {mask[3:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_120( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_376 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_105( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_193 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_72( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File TLChannelCompactor.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ trait TLFieldHelper { def getBodyFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.mask, b.data, b.corrupt) case b: TLBundleB => Seq(b.mask, b.data, b.corrupt) case b: TLBundleC => Seq( b.data, b.corrupt) case b: TLBundleD => Seq( b.data, b.corrupt) case b: TLBundleE => Seq() } def getConstFields(b: TLChannel): Seq[Data] = b match { case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address ) case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo ) case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied) case b: TLBundleE => Seq( b.sink ) } def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits)) } class TLBeat(val beatWidth: Int) extends Bundle { val payload = UInt(beatWidth.W) val head = Bool() val tail = Bool() } abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val beat = Decoupled(new TLBeat(beatWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) q.io.enq <> io.protocol val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.beat.valid := protocol.valid protocol.ready := io.beat.ready && (is_body || !has_body) io.beat.bits.head := head && !is_body io.beat.bits.tail := tail && (is_body || !has_body) io.beat.bits.payload := Mux(is_body, body, const) when (io.beat.fire && io.beat.bits.head) { is_body := true.B } when (io.beat.fire && io.beat.bits.tail) { is_body := false.B } } abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper { override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_") val beatWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val beat = Flipped(Decoupled(new TLBeat(beatWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) io.protocol <> protocol val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg) io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.beat.bits.payload, body_fields) when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload } when (io.beat.fire && io.beat.bits.tail) { is_const := true.B } } class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) } class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) { when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p) class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) { has_body := edgeOut.hasData(protocol.bits) } class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p) class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) { has_body := edgeIn.hasData(protocol.bits) } class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)
module TLBFromBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:120:7] input clock, // @[TLChannelCompactor.scala:120:7] input reset, // @[TLChannelCompactor.scala:120:7] output io_beat_ready, // @[TLChannelCompactor.scala:75:14] input io_beat_valid, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14] input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14] ); reg is_const; // @[TLChannelCompactor.scala:88:25] wire io_beat_ready_0 = is_const & ~io_beat_bits_tail; // @[TLChannelCompactor.scala:88:25, :91:{30,33}] wire _GEN = io_beat_ready_0 & io_beat_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TLChannelCompactor.scala:120:7] if (reset) // @[TLChannelCompactor.scala:120:7] is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25, :120:7] else // @[TLChannelCompactor.scala:120:7] is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const; // @[Decoupled.scala:51:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_54( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1151 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1151; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1151; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1224 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1224; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1224; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1224; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1077 = _T_1151 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1077 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1077 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1077 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1077 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1077 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1123 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1123 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1092 = _T_1224 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1092 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1092 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1092 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1195 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1195 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1177 = _T_1224 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1177 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1177 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1177 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFNToRaw_postMul_e8_s24_44( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_414( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_6( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_8 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_115( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_17( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule